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// *****************************************************************************
//  @(#)rl_jtag_cntl.v	1.11 11/23/93
//  (Copied from Tsunami rl_jtag_cntl.v	1.21)
//
//  Description:
//  this is the top level JTAG controller module that instantiates various
//  sub modules that is needed to generate the control signals. the control
//  signals are routed to the internal Tsunami core for scan testing and to
//  the external boundary scan cells. this controller has been designed
//  per the IEEE P1149.1 protocols and strictly follows all the rules
//  stated in there.
//
//  This module instantiates all the submodules that reside in jtag_subblocks.v
//
// *****************************************************************************


//  removed the dcr module and a 7 bit signal coming from dcr to the top level
//  of JTAG module(mem_test_control signal).  (May 10, 1991)

//  added one extra port (shft)at this level and this will be used for 
//  tristating the jtag_tdo signal at the jtag_tdo output pad (July 10, 1991)

module  rl_jtag_cntl (
bscan_clk_a, bscan_clk_b, bscan_clk_upd, bscan_clk_cap, bscan_sel_ff,
bscan_mode,
cap_shft_clk,
clk_rst_l, tdo, sys_sen, testclk, testclken,jtag_tdo_oen_l,
tg_strobe,tck, tms, tdi, trst_l, isr_tdo, isr_tdi,
bsr_tdo, stopped, spare_ccr, logic_0, logic_1
);

// Boundary scan control interface:

    // bscan_clk_a and bscan_clk_b are non-overlapping latch enables (master
    //     and slave clocks, respectively).  bscan_clk_a is active-high,
    //     bscan_clk_b is active-low (sorry about the missing '_l' - I got
    //     the names from the library cell ports).
    //     To avoid pass-gate conflicts with bscan_clk_cap within the
    //     boundary cells, bscan_clk_a and bscan_clk_b must both be held low
    //     when not shifting.  Called 'A' and 'B', respectively. 
    output bscan_clk_a, bscan_clk_b ;

    // Capture clock (positive edge-triggered).  Must be held high when not
    //     capturing, to avoid pass-gate conflicts with bscan_clk_a/b.
    //     Called 'CK' in the library cells.
    output bscan_clk_cap ;

    // Update clock.  Active-high latch enable.  Must be held low when not
    //     updating, so that the output latch doesn't change during a shift
    //     or capture.  Called 'UP' in the library cells.
    output bscan_clk_upd ;

    // Mux selects: select the update latch output onto input or output.
    //     Called 'MD2' (select input)  and 'MD1' (select output) in
    //     the library cells.  1 -> select the latch.
    output bscan_sel_ff ;

    // Boundary scan shift mode.  Called 'SM_' in the library
    //     cells.
    output bscan_mode;

output  clk_rst_l, tdo, sys_sen, testclk, testclken,tg_strobe, jtag_tdo_oen_l;
input   tck,tms, tdi, trst_l,isr_tdo, bsr_tdo, stopped, spare_ccr;
output isr_tdi ;
input   logic_0, logic_1 ;
output cap_shft_clk ;


wire	bscan_mode_l;
wire 	bscan_mode = ~bscan_mode_l;

// S1inv_g inv6(tckbar, tck); // put a big drive inverter to drive lots of
				  // falling edge f/fs in jtag block
wire tckbar = ~tck;

    // We need to hardcode this buffer for synopsys.
    JBUFDA buf1 (tdi, isr_tdi) ;

tap_fsm tapsm(
a,b, c, d, 
tms, trst_l, tck
); 

// Added to clock during Capture or Shift stages
//  8/26/96

wire capture, shft ;
wire cap_shft_clk_enb ;

//assign cap_shft_clk = ( capture | shft ) & tck ;
Mflipflop bndy_cell_clk ( cap_shft_clk_enb, ( capture | shft ), tckbar, 1'b0 );
assign cap_shft_clk = cap_shft_clk_enb & tck ;

tap_decode tapdcd(
capture,shft, update_mc, tap_reset_l, 
sir, sdr,run_idle,cken_ctl,uden,sys_scan_mode,a, 
b, c,d, tck, trst_l,tckbar,logic_1, logic_0,
jtag_tdo_oen_l);

wire [5:0] inst;
ir inreg(
clk_rst_l, sel_int_scan,sel_ccr, sel_debug_scan, sel_et,
sel_sa, sel_byp, sel_id,sel_in,sel_ain,sel_all_ring, sel_all_block,et_d,in_d,ain_d, sa_d, 
id_d,byp_d, cisc_d, ccr_d, inst, uen, ir_tdo, 
sir,capture,shft, uden,tdi, tck,tckbar, tap_reset_l,trst_l,run_idle,sdr, logic_0, logic_1
);

    wire [1:0] sel_scan = { sel_int_scan, sel_debug_scan};

bsr_control bsrc(
    bscan_clk_a, bscan_clk_b,
    bscan_clk_cap, bscan_mode_l, bscan_clk_upd, bscan_sel_ff,
    sel_et, sel_sa, sel_in, sel_ain, capture, shft, uden,
    sel_all_ring, sel_all_block, cisc_d, et_d, uen, in_d, ain_d,
    tap_reset_l, tck,tckbar,trst_l, logic_1
);

isr_control isrc(
sys_sen, scan_clk_hold, tg_strobe, shft , capture,
sel_scan, sel_in, run_idle, trst_l, tck,tckbar, update_mc,tms,sys_scan_mode);

scanclock_control sckc(
testclk, testclken, et_d, sa_d, id_d,byp_d,
ccr_d,tap_reset_l, scan_clk_hold, tck, trst_l, uen
);


bypass byp(
byp_tdo, sel_byp, capture,shft,tdi,tck , logic_0
);

idreg idr(
id_tdo, sel_id, capture,shft,tdi,tck, logic_0, logic_1
);

// Changed here so that CCR is scannable -  8/26/96

ccr clkc(
//ccr_tdo, sel_ccr,shft, tck,trst_l,stopped, spare_ccr, logic_0
ccr_tdo, sel_ccr,  capture, shft, tdi, tck,trst_l,stopped, spare_ccr, logic_0
);

tdo_control tdoc(
tdo,inst,sel_id, isr_tdo,ccr_tdo, bsr_tdo, id_tdo, byp_tdo, ir_tdo,
sir,tckbar, tdi,trst_l,logic_0
);

endmodule