/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)clk_misc.v 1.21 4/30/93
module clk_misc
(
bscan_clk_a,
bscan_clk_b,
bscan_clk_upd,
bscan_clk_cap,
bscan_sel_ff,
bscan_mode,
pll_byp_l,
cap_shft_clk,
tmr_clk,
gclk_unbuf,
gclk_unbuf_,
gclk_1st_phase,
rcc_clk_unbuf,
pci_refclk_unbuf,
pci_refclk_unbuf_,
rcc_clk,
rfr_clock_unbuf,
rfr_late_unbuf,
sboclk_unbuf,
ss_clock_unbuf,
// add the following two outputs for 2.0
pci_rst_pin_out_l,
pci_rst_int_l,
memif_idle,
pcic_idle,
ic_standby_f,
dc_standby_w,
standby_req,
standby_dsbl_tlb,
reset_iu,
reset,
ss_scan_mode,
tg_strobe,
jtag_tdo_oen_l,
jtag_tdo,
int_event_l,
//sbus_clk_unbuf,
standby,
div_ctl,
jtag_ck,
jtag_ms,
jtag_tdi,
jtag_trst_l,
csl_scan_out1,
csl_scan_out2,
csl_scan_out3,
csl_scan_out4,
csl_scan_mode,
//csl_scan_in1,
//csl_scan_in2,
//csl_scan_in3,
//csl_scan_in4,
w_jtag_tdo_scan_out1,
w_procmon,
// w_cp_stat_l,
// any_intrnl_int_l,
w_rom_oe_l,
w_rom_cs_l,
w_rom_oe_ls,
w_rom_cs_ls,
input_reset_l,
// add the following for sw reset in 2.0
sw_rst,
en_sw_rst_nonwd,
pci_slave_mode,
en_pci_sw_rst,
pci_rst_pin_in_l,
ext_event_l,
ss_misc_scan_in,
isr_tdi,
bsr_tdo,
iu_error,
iu_error_l,
mm_hold_rst,
mm_event,
iu_event,
last_phi,
next2last_phi,
first_phi,
logic_0,
logic_1,
input_clock
);
output bscan_clk_a
;
output bscan_clk_b
;
output bscan_clk_upd
;
output bscan_clk_cap
;
output bscan_sel_ff
;
output bscan_mode
;
input pll_byp_l
;
output cap_shft_clk
;
output tmr_clk
;
output gclk_unbuf
;
output gclk_unbuf_
;
output gclk_1st_phase
;
output w_jtag_tdo_scan_out1
;
output w_procmon
;
// output [1:0] w_cp_stat_l ;
output w_rom_oe_ls
;
output w_rom_cs_ls
;
output rcc_clk_unbuf
;
output pci_refclk_unbuf
;
output pci_refclk_unbuf_
;
input rcc_clk
;
output jtag_tdo_oen_l
;
output jtag_tdo
;
output int_event_l
;
output rfr_clock_unbuf
;
output rfr_late_unbuf
;
//output sbus_clk_unbuf ;
output sboclk_unbuf
;
output ss_clock_unbuf
;
// add the following 2 outputs for 2.0
output pci_rst_pin_out_l
;
output pci_rst_int_l
;
input standby
;
input [1:0] div_ctl
;
input jtag_ck
;
input jtag_ms
;
input jtag_tdi
;
input jtag_trst_l
;
input csl_scan_out1
;
input csl_scan_out2
;
input csl_scan_out3
;
input csl_scan_out4
;
input csl_scan_mode
;
//input csl_scan_in1 ;
//input csl_scan_in2 ;
//input csl_scan_in3 ;
//input csl_scan_in4 ;
// input any_intrnl_int_l ;
input w_rom_oe_l
;
input w_rom_cs_l
;
input input_reset_l
;
// add the following for resets in 2.0
input sw_rst
;
input en_sw_rst_nonwd
;
input pci_slave_mode
;
input en_pci_sw_rst
;
input pci_rst_pin_in_l
;
input ext_event_l
;
input input_clock
;
input memif_idle
;
input pcic_idle
;
input ic_standby_f
;
input dc_standby_w
;
output standby_req
;
output standby_dsbl_tlb
;
output reset_iu
;
output reset
;
output ss_scan_mode
;
output tg_strobe
;
input ss_misc_scan_in
;
output isr_tdi
;
input bsr_tdo
;
input iu_error
;
output iu_error_l
;
input mm_hold_rst
;
input mm_event
;
input iu_event
;
output last_phi
;
output next2last_phi
;
output first_phi
;
output logic_0
;
output logic_1
;
wire [2:0] free_phase_late_a1
;
wire [1:0] gclk_phase_late_a1
;
wire ss_misc_scan_out
;
// Additions for scan chains ( 4 )
//wire csl_scan_in1, csl_scan_in2, csl_scan_in3, csl_scan_in4 ;
//wire csl_scan_out1, csl_scan_out2, csl_scan_out3, csl_scan_out4 ;
wire procmon_out
;
// wire [1:0] w_cp_stat_l ;
wire w_jtag_tdo_scan_out1 = csl_scan_mode ? csl_scan_out1 : jtag_tdo;
wire w_procmon = csl_scan_mode ? csl_scan_out2 : procmon_out;
// assign w_cp_stat_l[0] = csl_scan_mode ? csl_scan_out3 : any_intrnl_int_l;
// assign w_cp_stat_l[1] = csl_scan_mode ? csl_scan_out4 : iu_error_l;
wire w_rom_oe_ls = csl_scan_mode ? csl_scan_out3 : w_rom_oe_l;
wire w_rom_cs_ls = csl_scan_mode ? csl_scan_out4 : w_rom_cs_l;
// During Scan mode the jtag_clk should be selected
wire raw_tmr_clk
, raw_gclk_unbuf
, raw_gclk_unbuf_
, raw_rcc_clk_unbuf
,
raw_ss_clock_unbuf
, raw_sboclk_unbuf
, raw_rfr_clock_unbuf
,
raw_rfr_late_unbuf
, raw_pci_refclk_unbuf
, raw_pci_refclk_unbuf_
;
assign tmr_clk = csl_scan_mode ? jtag_ck : raw_tmr_clk ;
assign gclk_unbuf = csl_scan_mode ? jtag_ck : raw_gclk_unbuf ;
assign gclk_unbuf_ = csl_scan_mode ? jtag_ck : raw_gclk_unbuf_ ;
assign rcc_clk_unbuf = csl_scan_mode ? jtag_ck : raw_rcc_clk_unbuf ;
assign ss_clock_unbuf = csl_scan_mode ? jtag_ck : raw_ss_clock_unbuf ;
assign sboclk_unbuf = csl_scan_mode ? jtag_ck : raw_sboclk_unbuf ;
assign rfr_clock_unbuf = csl_scan_mode ? jtag_ck : raw_rfr_clock_unbuf ;
assign rfr_late_unbuf = csl_scan_mode ? jtag_ck : raw_rfr_late_unbuf ;
assign pci_refclk_unbuf = csl_scan_mode ? jtag_ck : raw_pci_refclk_unbuf ;
assign pci_refclk_unbuf_ = csl_scan_mode ? jtag_ck : raw_pci_refclk_unbuf_ ;
// End additions
misc ssparc_misc(
.gclk_phase_late_a1 (gclk_phase_late_a1[1:0]),
.gclk_1st_phase (gclk_1st_phase),
.standby_dsbl_sysclk_a1 (standby_dsbl_sysclk_a1
),
.standby_dsbl_tlb (standby_dsbl_tlb),
.standby_req (standby_req),
.standby (standby),
.pcic_idle (pcic_idle),
.memif_idle (memif_idle),
.ic_standby_f (ic_standby_f),
.dc_standby_w (dc_standby_w),
.div_ctl (div_ctl[1:0]),
.rcc_clk (rcc_clk), //buffered version of rcc_clk_unbuf with skew matched
// to ss_clk
.reset_any (reset_iu), // reset to internal blocks
.reset_nonwd (reset), // reset to internal blocks
.ss_scan_mode (ss_scan_mode),// scan enable
// change to isr_tdi so that we can use logic in rl_clk_stop via
// jtag.
// .ss_misc_scan_in (ss_misc_scan_in),
.ss_misc_scan_in (isr_tdi),
.ss_misc_scan_out (ss_misc_scan_out),
.input_reset_l (input_reset_l), // input reset from MACIO
// add the following for 2.0 resets, inputs
.sw_rst (sw_rst),
.en_sw_rst_nonwd (en_sw_rst_nonwd),
.pci_slave_mode (pci_slave_mode),
.en_pci_sw_rst (en_pci_sw_rst),
.pci_rst_pin_in_l (pci_rst_pin_in_l),
// add the following for 2.0 resets, outputs
.pci_rst_pin_out_l (pci_rst_pin_out_l),
.pci_rst_int_l (pci_rst_int_l),
.iu_error (iu_error), // from iu error mode
.iu_error_l (iu_error_l),
.mm_hold_rst (mm_hold_rst),
// Event inputs to clock stop control
.mm_event (mm_event),
.iu_event (iu_event),
.ext_event_l (ext_event_l),
.int_event_l (int_event_l),
.rcc_rst_l (rcc_rst_l
),
.stop (stop
),
.start (start
),
.rs_dsbl_clocks_in (rs_dsbl_clocks_in
),
.free_phase_late_a1 (free_phase_late_a1[2:0]),
.last_phi (last_phi),
.next2last_phi (next2last_phi),
.first_phi (first_phi),
.stop_after_0 (stop_after_0
),
.stop_after_1 (stop_after_1
),
.stop_after_2 (stop_after_2
),
.stop_after_3 (stop_after_3
),
.stop_after_4 (stop_after_4
),
.logic_0 (logic_0),
.logic_1 (logic_1)
);
// This module contains all of the input_clock-frequency logic
rl_clk_cntl clk_cntl(
.logic_0 (logic_0),
.tmr_clk (raw_tmr_clk),
.gclk_unbuf (raw_gclk_unbuf),
.gclk_unbuf_ (raw_gclk_unbuf_),
.gclk_phase_late_a1 (gclk_phase_late_a1[1:0]),
.tc_scan_clk (testclk
),
.jtag_trst_l (jtag_trst_l),
.input_reset_l (input_reset_l),
.rcc_rst_l (rcc_rst_l),
.testclken (testclken
),
.start (start),
.stop (stop),
.pll_byp_l (pll_byp_l),
.stop_after_0 (stop_after_0),
.stop_after_1 (stop_after_1),
.stop_after_2 (stop_after_2),
.stop_after_3 (stop_after_3),
.stop_after_4 (stop_after_4),
.stopped (stopped
),
.rcc_clk_unbuf (raw_rcc_clk_unbuf),
.free_phase_late_a1 (free_phase_late_a1[2:0]),
.rs_dsbl_clocks_in (rs_dsbl_clocks_in),
.ss_clock_unbuf (raw_ss_clock_unbuf),
//.sbus_clk (sbus_clk_unbuf),
.sboclk (raw_sboclk_unbuf),
.rfr_clock (raw_rfr_clock_unbuf),
.rfr_late (raw_rfr_late_unbuf),
.standby_dsbl_sysclk_a1 (standby_dsbl_sysclk_a1),
.clk_rst_l (clk_rst_l
),
.pci_refclk_unbuf (raw_pci_refclk_unbuf),
.pci_refclk_unbuf_ (raw_pci_refclk_unbuf_),
.div_ctl (div_ctl[1:0]),
.input_clock (input_clock)
) ;
rl_jtag_cntl jtag_cntl(
.bscan_clk_a (bscan_clk_a),
.bscan_clk_b (bscan_clk_b),
.bscan_clk_upd (bscan_clk_upd),
.bscan_clk_cap (bscan_clk_cap),
.bscan_sel_ff (bscan_sel_ff),
.bscan_mode (bscan_mode),
.cap_shft_clk (cap_shft_clk),
.clk_rst_l (clk_rst_l),
.jtag_tdo_oen_l (jtag_tdo_oen_l),
.tdo (jtag_tdo),
.sys_sen (ss_scan_mode),
.testclk (testclk),
.testclken (testclken),
.tg_strobe (tg_strobe),
.tck (jtag_ck),
.tms (jtag_ms),
.tdi (jtag_tdi),
.trst_l (jtag_trst_l),
.isr_tdo (isr_tdo
),
.isr_tdi (isr_tdi),
.bsr_tdo (bsr_tdo),
// CCR scan chain bits (scanout only, synchronized within)
.stopped (stopped),
.spare_ccr (logic_0),
.logic_0 (logic_0),
.logic_1 (logic_1)
) ;
// Added spare cells
spares clk_misc_spares ();
// Misc is the last block in the scan chain.
assign isr_tdo = ss_misc_scan_out ;
endmodule
This page: |
Created: | Thu Aug 19 11:59:35 1999 |
| From: |
../../../sparc_v8/ssparc/clk_misc/rtl/clk_misc.v
|