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//***************************************************************************** // @(#)jtag_subblocks.v 1.23 1/13/95
// (Modified from Tsunami jtag_subblocks.v 1.37)
//
// Description:
//
// The JTAG controller has been broken up into smaller modules and each
// one generates a sub set of the signals needed to control the internal
// and external scan chain.
//
// Created: Oct 25, 1990
//
//
//*****************************************************************************
// the following module is the JTAG TAP(test access protocol) state machine
// and it's inputs are tms(test mode signal), tck(test clock) and trst_l(test
// reset, all of which are direct inputs from external pins. the four outputs
// (state variables) of this block, along with their complements are used to
// decode the various states that the testing process will be in.
![[Up: rl_jtag_cntl tapsm]](v2html-up.gif)
module tap_fsm
(
a,b, c, d,
tms, trst_l, tck
);
output a, b, c, d;
input tms, trst_l, tck;
// declare all tap states
wire [3:0] tapc_state, tapc_state_l ;
wire [3:0] tapc_nstate ;
// this is a 4-variable, 16 state finite state machine
// which operates on Moore machine model.
// State must reset to 1111, so store it inverted in this register.
Mflipflop_ar_4 fsm(tapc_state_l, ~tapc_nstate, trst_l, tck);
assign tapc_state = ~tapc_state_l ;
// the next states are assigned thro the following Boolean
// equations
// reset on trst_l(active low) to Test_Logic_Reset state
// replace existing synchronous reset flops with asynchronously presettable f/f
assign tapc_nstate[3] = (~tms & tapc_state[2]&~tapc_state[1]) |
(tapc_state[3]& ~tapc_state[2]) | (tapc_state[3]& tapc_state[1]) |
(~tapc_state[3]& tapc_state[2] & ~tapc_state[1]) & ~tapc_state[0] ;
assign tapc_nstate[2] = (tms&~tapc_state[1]) | (tapc_state[2]&
~tapc_state[1]) | ( tapc_state[2]&tapc_state[0]) ;
assign tapc_nstate[1] = (~tms&tapc_state[1]&~tapc_state[0]) |
(~tms & ~tapc_state[2]) | (~tms & ~tapc_state[3] &tapc_state[1]) |
(~tms & ~tapc_state[3]& ~tapc_state[0]) | (tms & tapc_state[2]&
~tapc_state[1]) | (tms & tapc_state[3]&tapc_state[2]& tapc_state[0]);
assign tapc_nstate[0] = (~tms&~tapc_state[2]&tapc_state[0])|
(tms &~tapc_state[1]) | (tms & ~tapc_state[0]) | (tms&tapc_state[3]&
tapc_state[2]) ;
// compute the value of a, b, c, d using tapc_nstate instead and clock them
// on the rising edge in the tapdcd module (May 17, 1991)
// Change tapc_nstate to tapc_state - 8/21/96
//wire d = tapc_nstate[3] | ~trst_l ;
//wire c = tapc_nstate[2] | ~trst_l ;
//wire b = tapc_nstate[1] | ~trst_l ;
//wire a = tapc_nstate[0] | ~trst_l ;
wire d = tapc_state[3] | ~trst_l ;
wire c = tapc_state[2] | ~trst_l ;
wire b = tapc_state[1] | ~trst_l ;
wire a = tapc_state[0] | ~trst_l ;
endmodule
// in the following module, the state variables are decoded to generate the
// appropriate , capture or update signal. the tap_reset signal
// corresponds to the test-logic-reset state of the tap_fsm and indicates
// that the component can be in the normal operating mode. this signal is used
// to reset the latches used within the JTAG controller,except the fsm itself.
module tap_decode ( capture, Shift, update_mc,
tap_reset_l, sir,sdr,
run_idle, cken_ctl,uden,sys_scan_mode, a, b, c, d,tck, trst_l,tckbar,logic_1, logic_0,
jtag_tdo_oen_l);
output capture, Shift, update_mc, tap_reset_l,
sir, sdr,run_idle, cken_ctl,uden,sys_scan_mode,jtag_tdo_oen_l;
input a, b, c,d,tck, trst_l,tckbar,logic_1, logic_0 ;
// the following signals are decodes of the state variables from the tap_fsm
// capture_en and shift_en are the key signals needed during scan test of
// of a block, where capture will cause the capture of next state and
// would enable the scan_mode for all the scan f/f's
// added one more decode signal exit_ir to control tck_en (May 16, 91)
//wire capture_en = ~a & b & c ;
//wire shift_en = ~a & b & ~c ;
//wire update_en = a & ~b & c ;
//wire tap_reset_en = a & b & c & d ;
//wire exit1_ir = a & ~b & ~c & d ;
//wire update_dr = a & ~b & c & ~d ;
wire capture = ~a & b & c ;
wire Shift = ~a & b & ~c ;
wire uden = a & ~b & c ; // UDR or UIR
wire tap_reset_en = a & b & c & d ; // TLR
wire cken_ctl = a & ~b & ~c & d ; // E1IR
wire update_mc = a & ~b & c & ~d ; // UDR
// added the decode from tap state to have the scan_mode signal
// asserted during the traversal thro exit1, pause and exit2 (DR)states ,
// back to the Shift state and continue shifting thro the chain. This
// helps in keeping the tristates disabled while in these three states
// before continuing the Shift sequence. Due to the encoding of
// these four states(0000,0001,0010,0011) the decoding reduces to
// just (July 24, 1991)
//wire scan_mode = ~c & ~d ;
wire sys_scan_mode = ~c & ~d ;
// added the following decode for supporting INTEST instruction (April 22, 1991)
//wire run_idle_test = ~a & ~b & c & d ;
wire run_idle = ~a & ~b & c & d ; // RTI
//wire select_ir = d;
//wire select_dr = ~d;
wire selir = d;
wire seldr = ~d ;
// following f/fs has been changed to asynchronously resettable f/fs
//Mflipflop_ar l1(capture, capture_en, trst_l, tck);
// **** GATE FIX FOR BUG 1059 ECN xx (jtag_oen on tckbar instead of tck)
// add new async ff to design. send jtag_tdo_oen to IO_ring
Mflipflop_ar ff_bug1059(jtag_tdo_oen, Shift, trst_l, tckbar) ;
wire jtag_tdo_oen_l = ~jtag_tdo_oen ;
// **** GATE FIX DONE
//Mflipflop_ar l2(Shift, shift_en, trst_l, tck);
//Mflipflop_ar l3(update_mc, update_dr, trst_l, tck);
//Mflipflop_ar l5(run_idle, run_idle_test, trst_l, tck);
//Mflipflop_ar l6(cken_ctl, exit1_ir, trst_l, tck);
//Mflipflop_ar l7(sdr, select_dr, trst_l, tck);
//Mflipflop_ar l8(uden, update_en, trst_l, tck);
//Mflipflop_ar l9(selir, select_ir, trst_l, tck);
//Mflipflop_ar l10(sys_scan_mode, scan_mode, trst_l, tck);
// following f/f has been changed to asynchronously presettable f/f
// changed tck to tckbar in order to allow bout_mode and tclken happen at
// the falling edge of tck and avoid bus contention during single step
// of sunergy system (sep 25,1991)
// added one more ff to delay the tap_reset signal so that b_mode and
// testclken signal will change state only on the falling edge of tck after
// reaching the test_logic_reset state(at the rising edge of tck) (Oct 9, 91)
Mflipflop_noop spare_gate_bugfix_1018(delayed_tap_reset_en, tap_reset_en, tck) ;
// trst must force tap_reset, so store tap_reset inverted in this FF.
Mflipflop_ar l4(tap_reset_l, ~delayed_tap_reset_en, trst_l, tckbar);
// to inhibit sel_ir signal during tap_state run_test_idle and tap_logic_reset
assign sir = selir & ~(run_idle | ~tap_reset_l) ;
// to inhibit select dr signal during sel-IR-scan chain
wire sel_ir_scan = ~a & ~b & c & ~d ;
assign sdr = seldr & ~sel_ir_scan ;
endmodule
// the following module does 50% of the work in the JTAG controller.
// JTAG instructions are scanned into the instruction register in this
// module and they are decoded based on pre assigned 6 bit values per
// instruction. after the decode of each instruction, the decoded signals
// are latched to maintain the value of that control signal throughout
// that particular test operation.
module ir (clk_rst_l, iu_ring,
ccr_ring, cisc_ring, et_ring,
sa_ring, byp_ring, id_ring,in_ring,ain_ring, all_ring, all_block, et_d,
in_d,ain_d, sa_d, id_d,byp_d, cisc_d, ccr_d, inst, uen, sout,
sir,cap, te, update, ti, tck,tckbar, tap_reset_l,trst_l, run_idle,
sdr, logic_0, logic_1
);
output clk_rst_l, iu_ring,
ccr_ring, cisc_ring, et_ring,
sa_ring, byp_ring, id_ring,in_ring,ain_ring,all_ring, all_block, et_d,
sa_d, id_d,in_d,ain_d, byp_d, cisc_d, ccr_d, uen, sout ;
output [5:0] inst;
input sir,cap, te, update,ti, tck,tckbar, tap_reset_l,trst_l, run_idle,sdr,logic_0,
logic_1;
wire [5:0] irq ;
wire [5:0] inst ;
// the two LSB of the Instruction register is hardwired to 01 per the JTAG
// protocol to enable testing the TDI line when starting the test process
// thro JTAG control. The remaining 4 bits can be set to any value or tied to
// some status lines
// wire [5:0] din = 6'b000001;
wire [5:0] din = {{5{logic_0}}, logic_1};
// the following signals are needed by the instruction register for lodaing,
// scanning in the instruction to IR and updating it in the instruction latch
wire cap_ir = (cap & sir);
wire te_ir = te & sir;
wire uen = update & sir;
wire uen_l = ~uen ;
// the following is the actual instruction register
// 7-15-96 : removed scan flops
Mflipflop_sh_6 ld16(irq, din, te_ir, {ti,irq[5:1]}, ~cap_ir, tck) ;
//Mflipflop_h_6 ld16(irq, din, ~cap_ir, tck) ;
wire rst_l = trst_l & tap_reset_l;
// changed ck to ckbar to comply with rule 6.2.1.e of the 1149.1
// IEEE protocol that states IDCODE to be latched on falling tck
// S1inv_c inv4(ckbar, tck);
// Mlatch6LA2 la26(inst,instn,irq,ckbar,uen,rst);
// unravelled the above 6 bit register into individual f/fs, so that
// synposis and motive constraints can be easily specified
// following f/fs has been changed to asynchronously resettable f/fs
Mflipflop_arh inst_latch_l1(inst[5], irq[5], uen_l, rst_l, tckbar);
Mflipflop_arh inst_latch_l2(inst[4], irq[4], uen_l, rst_l, tckbar);
Mflipflop_arh inst_latch_l3(inst[3], irq[3], uen_l, rst_l, tckbar);
Mflipflop_arh inst_latch_l4(inst[2], irq[2], uen_l, rst_l, tckbar);
Mflipflop_arh inst_latch_l5(inst[1], irq[1], uen_l, rst_l, tckbar);
Mflipflop_arh inst_latch_l6(inst[0], irq[0], uen_l, rst_l, tckbar);
// the LSB of the Instruction register is the scan_out bit
wire sout = irq[0];
// the output of the instruction register are decoded here before being
// latched
// the following are instructions pertaining to scan test of internal blocks and
// decode of certain control registers like clock control reg
// These instructions are private instructions and not usually visible
// to the users of the chip
wire iu_d, id_la;
assign iu_d = (irq[5:0] == 6'b010000) ?1'b1 : 1'b0 ;
assign ccr_d = (irq[5:0] == 6'b011110) ?1'b1 : 1'b0 ;
assign cisc_d = (irq[5:0] == 6'b011111) ?1'b1 : 1'b0 ;
// This instruction asserts clk_rst_l for as long as the instruction
// is in the output latches.
wire clk_rst_d = (irq[5:0] == 6'b110000) ;
// the following instructions are mandated by the JTAG(IEEE1149.1) protocol
// and are part of the public instructions accessible by the users of the
// chip. The minimal requirement is, at least to have extest, sample and
// bypass instructions. The rest of them are optional.
assign et_d = (irq[5:0] == 6'b000000) ?1'b1 : 1'b0 ;
assign sa_d = (irq[5:0] == 6'b000001) ?1'b1 : 1'b0 ;
assign id_d = (irq[5:0] == 6'b100000) ?1'b1 : 1'b0 ;
assign id_la =(~inst[5] == 1'b1 & inst[4:0] == 5'b00000) ?1'b1 : 1'b0 ;
// Following is the instruction called ATEINTEST to support slow speed testing
// of the on chip system logic (pp.7.17 of the 1149.1 protocol document)
assign in_d = (irq[5:0] == 6'b000011) ?1'b1 : 1'b0 ;
// The following instruction called INTEST will support the application of
// ATPG vectors (in conjunction with sel_int_scan instruction) to Tsunami
assign ain_d = (irq[5:0] == 6'b000010) ?1'b1 : 1'b0 ;
// bypass instruction should be selected when no other JTAG instructions in
// Tsunami are selected(rule 7.1.1d of 1149.1 IEEE protocol)
assign byp_d = ~( iu_d | cisc_d | ccr_d | et_d | sa_d | id_d |in_d | ain_d ) ;
wire [2:0] dpr_sig;
wire [5:0] dpu_sig;
assign dpr_sig = {iu_d,ccr_d, cisc_d};
assign dpu_sig = {ain_d,et_d, sa_d, byp_d,id_d,in_d};
wire [2:0] dpr ;
wire [5:0] dpu ;
// latched the decoded instrtuctions on falling edge of tck (7/22/91)
// S1inv_c inv5(ckbar, tck);
// Mlatch3LA2 la2(dpr, dpr_l, dpr_sig,ckbar, uen,tap_reset_l);
// unravelled the above 3 bit register into individual f/fs, so that
// synposis and motive constraints can be easily specified
// following f/fs has been changed to asynchronously resettable f/fs
Mflipflop_arh dcd_l1(dpr[2], dpr_sig[2], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l2(dpr[1], dpr_sig[1], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l3(dpr[0], dpr_sig[0], uen_l, tap_reset_l, tckbar);
Mflipflop_arh crl(clk_rst, clk_rst_d, uen_l, tap_reset_l, tckbar);
wire clk_rst_l = ~clk_rst ;
// Mlatch6LA2 la3(dpu, dpu_l, dpu_sig,ckbar, uen,tap_reset_l);
// unravelled the above 6 bit register into individual f/fs, so that
// synposis and motive constraints can be easily specified
// following f/fs has been changed to asynchronously resettable f/fs
Mflipflop_arh dcd_l4(dpu[5], dpu_sig[5], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l5(dpu[4], dpu_sig[4], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l6(dpu[3], dpu_sig[3], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l7(dpu[2], dpu_sig[2], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l8(dpu[1], dpu_sig[1], uen_l, tap_reset_l, tckbar);
Mflipflop_arh dcd_l9(dpu[0], dpu_sig[0], uen_l, tap_reset_l, tckbar);
// the latched signals are gated with sdr(during data cycle of TAP)
// to generate the actual select control signals that select each block for
// scan testing
// iu_ring -- sel_int_scan, cisc_ring -- sel_dbg_scan, ccr_ring -- sel_ccr
// ain_ring -- INTEST, in_ring -- ATEINTEST, sa_ring -- SAMPLE
// byp_ring -- BYPASS, id_ring -- IDCODE, et_ring -- EXTEST
assign iu_ring = sdr & dpr[2];
assign ccr_ring = sdr & dpr[1];
assign cisc_ring = sdr & dpr[0];
assign et_ring = sdr & dpu[4];
assign sa_ring = sdr & dpu[3];
assign byp_ring = sdr & dpu[2];
assign ain_ring = sdr & dpu[5];
// modified in_ring definition with run_idle signal, so that in_ring wouldn't
// die without sel_dr (April 23, 1991)
assign in_ring = (run_idle | sdr) & dpu[0];
// the following logic is added to ensure that the id_reg is selected as soon
// as the tap gets into the test_logic_reset state or, when the actual id_reg
// instruction is scanned into the id_reg. we should also be cautious not to
// have id_reg selected when extest has been selected (since id_la is decoded
// soon after "inst" is initialized at reset and is 1 for both extest and
// initialization condition. Hence the (~dpu[4])term is added to the definition
// of id_ring
wire selid = sdr & id_d ;
wire selida = id_la & (~dpu[4]);
assign id_ring = selid | selida;
assign all_ring = iu_ring ;
assign all_block = iu_d ;
endmodule
// this module generates the control signal needed for controlling the
// external boundary scan cells, both input and output
module bsr_control(
bscan_clk_a, bscan_clk_b,
bscan_clk_cap, bscan_mode_l, bscan_clk_upd, bscan_sel_ff,
sel1, sel2,sel3, sel4, cap,
te, uden, all_ring, all_block,cisc_d, extest, update,intest,aintest,
tap_reset_l, tck,tckbar, trst_l, logic_1
);
// sel1 -- sa_ring, sel2 -- et_ring, sel3 -- in_ring, sel4 -- ain_ring
output bscan_clk_a, bscan_clk_b,
bscan_clk_cap, bscan_mode_l, bscan_clk_upd, bscan_sel_ff ;
input sel1, sel2,sel3, sel4,cap,te, uden, all_ring, all_block,cisc_d, extest,
update, intest,aintest, tap_reset_l, tck,tckbar, trst_l, logic_1 ;
wire sel = sel1 | sel2;
// the following scan_mode(sen) signal enables scanning thro the bsr to get
// to the internal scan chain
wire bsen_nodelay = (sel | sel3 | sel4 ) & te ;
// Need to latch bsen on the falling edge of tck to ensure no race
// between tck and the scan_mode signal to boundary f/fs. (7/25/91)
// following f/f has been changed to asynchronously resettable f/f
Mflipflop_ar bsen_fe2(bsen, bsen_nodelay, trst_l, tckbar) ;
// added the following gating to ensure no x's on sen without tck,
// which happens during normal simulation (July 10, 1991)
// Disabled bscan_mode_l for bug #600. (See bug report #600 for more
// detailes. (11/22/93)
wire bscan_mode_l = ~(bsen & trst_l) ;
//wire bscan_mode_l = logic_1;
// The following signal uen updates the boundary scan latch during
// update-DR state(falling tck)
wire uen1 = (sel4|sel3|sel) & uden ;
wire uen3 = ~(uen1) ;
// The following equation is written using actual gates for synopsys
// S1nor2_d uen_bctl1_buf1(buen, tck, uen3) ;
wire buen = ~(tck | uen3) ;
// added the following gating to ensure no x's on uen without tck,
// which happens during normal simulation (July 10, 1991)
wire bscan_clk_upd = (buen & trst_l) ;
// Because of bidirectional boundary cell design,
// no longer implements separate input and output capture signals;
// thus, we do not follow recommendations 7.7.1g and 7.8.1f .
// Gated tck, held high. Logically, it is the OR of Tsunami's
// out_cap and in_cap, gating tck.
// NOT used in EAGLE
wire bscan_clk_cap =
~(~tck & cap & trst_l & (all_ring | sel1 | sel2 | sel3 | sel4)) ;
// use falling edge of tck to clock out mode signal during update-IR state
// This is used to control the mux in the boundary scan f/f
// added cisc_d term to the din signal so that mode is 1 during sel_dbg_scan
wire din = (all_block | extest| intest|aintest|cisc_d) ;
// following f/f has been changed to asynchronously resettable f/f
Mflipflop_arh la1(imode, din, ~update, tap_reset_l, tckbar);
// hardwired the mode signal to ensure no x's on mode without tck,
// which happens during normal simulation (July 10, 1991)
wire bscan_sel_ff = (imode & trst_l) ;
ACABGEN abgen(tck, bsen_nodelay, bscan_clk_a, bscan_clk_b) ;
endmodule
// the scan_mode signal needed for all internal blocks is generated in this
// block, by using the , capture signal from tap_decode and the sel_ring
// from the instruction register module
module isr_control(ssen, scan_clk_hold, tstrobe, sen, cap, sel_scan, sel_in, run_idle, trst_l, tck,tckbar, update_mc,tms,sys_scan_mode);
output ssen, scan_clk_hold, tstrobe ;
input sen, cap, sel_in, run_idle, trst_l,tck,tckbar,update_mc,tms,sys_scan_mode;
input [1:0] sel_scan;
// the scan_mode signal(ssen) for internal scan f/f's is generated by gating
// the decoded signal from the TAP FSM with appropriate ring select signal
// use sys_scan_mode signal instead of sen(Shift) to generate the ssen
// signal. This helps keep the tristates disabled during the entire Shift
// cycle that includes the traversal thro pause state. (7/25/91)
wire ssen_nodelay = sys_scan_mode & (sel_scan[0] | sel_scan[1] );
// had to latch the ssen_nodelay signal on falling tck in order to slow it down
// by at least half a clock and allow the extra testclk pulse to happen
// during the capture state (July 9, 1991). This delay by half a clock fixes
// the race condition between testclk and scanmode
// following f/f has been changed to asynchronously resettable f/f
Mflipflop_ar fe2(scan_en, ssen_nodelay, trst_l, tckbar) ;
// use trst_l to qualify ssen so that functional sim will work (July 10, 1991)
// hard code the AND gate and mark it dont touch in synopsys
wire ssen = (scan_en & trst_l) ;
// the clock_en signal is used to enable the clock only during and
// capture states of TAP FSM , except the cap clock is disabled during
// the debug scan operation(allscan)
wire ck_en1 = sen & (sel_scan[0] | sel_scan[1] );
wire ck_en2 = cap & (sel_scan[1] );
// generate ck_en3 term for single stepping during ATEINTEST
// *** GATE FIX FOR BUG 1045 ECN xx (glitch problem on Jtag_ck due to Jtag_ms)
// ff added and input of ck_en3 changed from update_mc to update_mc_delayed
//S1dffsrh_d __spare_gate_S1dffsrh_373(
//.hold(logic_0),
//.reset_n(logic_1),
//.scanen(logic_0),
//.din(update_mc),
//.sin(logic_0),
//.q(update_mc_delayed),
//.clk(tck));
Mflipflop_noop __spare_gate_S1dffsrh_373(update_mc_delayed, update_mc, tck) ;
wire ck_en3 = run_idle & update_mc_delayed & sel_in;
// wire ck_en3 = ~tms & update_mc & sel_in; <- old definition
// *** GATE FIX DONE
// added ck_en3 term to scan_clock_hold to apply single step clocks to
// tsunami core during ATEINTEST instruction
wire scan_clk_hold = (~(ck_en1 | ck_en2) &~( ck_en3)) | ~trst_l ;
// the strobe is needed to test the megacell ram arrays and is part of the
// megacell spec. after the address and control are scannned in, the scan_mode
// ( state) signal is deasserted, and when the tap_fsm enters the update
// state, a pulse is generated and gated with the sel_int_scan(sel_scan[0]
// and sel_debug_scan (sel_scan[1]) signal.
// This strobe(tstrobe) is used to start the internal(megacell) self-timed
// circuits for SRAM access(R/W and clear)
wire strobe = (sel_scan[0] | sel_scan[1] ) & update_mc;
// following f/f has been changed to asynchronously resettable f/f
Mflipflop_ar la1(rstrobe, strobe, trst_l, tck);
// added the following gating to ensure no x's on tstrobe without tck,
// which happens during normal simulation (July 10, 1991)
// S1nand2_d tstrobe_buf1 (tstrobe, rstrobe, trst_l) ;
wire tstrobe = ~(rstrobe & trst_l) ;
endmodule
// this module generates the clock needed for the internal scan registers
// along with the clock enable signal that needs to control the above
// clock within the clock controller block
// ****** FIX FOR BUG 1062 *** ECN xx
// change testclken signal generation -- use uen instead of cken_ctl, since
// this may caues testclken to change state while scanning instructions thro
// Tsunami to adjacent chips on the board level scan chain
module scanclock_control(testclk, testclken, extest, sample, idreg,bypass, clockctl, tap_reset_l, scan_clk_hold, tck, trst_l, uen
);
output testclk, testclken ;
input extest , sample , idreg , bypass , clockctl,
tap_reset_l, scan_clk_hold, tck, trst_l, uen ;
// rewrite the following as an OR gate to facilitate synopsys constraints
// we will lose some optimization here, but this is not critical.
// assign testclk = scan_clk_hold | tck ;
// S1or2_d testclk_buf1 (testclk, tck, scan_clk_hold) ;
wire testclk = (tck | scan_clk_hold) ;
wire pub_inst = ~(extest | sample | idreg | bypass | clockctl) ;
// wire din = cken_ctl & pub_inst ;
// the tck_en signal when '0' will inhibit the testclk during
// extest, sample, bypass, idreg, and clockcontrol mode. during
// these modes, the system clock and the tck would be free running, except
// when the system is in debug mode, when the system clock would be
// controlled by the contents of the clock control register(single step,
// start, stop, burst mode)
// generate tck_en one cycle before to take care of issues realted to
// synchronization of testclcken in the clock module. (May 16, 91)
// following f/f has been changed to asynchronously resettable f/f
// Mlatch1LA2 mla2(tck_en,tck_en_l, din,tck, cken_ctl, tap_reset_l);
// changed the hold signal from cken_ctl to uen --- FIX FOR BUG 1062
Mflipflop_arh mla2(tck_en, pub_inst, ~uen, tap_reset_l, tck);
assign testclken = trst_l & tck_en ;
endmodule
// this is a one bit register used to bypass the scan chain within a component
// when accessing other chips on the board
module bypass(sout,sel, capture, sen, ti, tck,logic_0
);
output sout ;
input sel, capture, sen, ti, tck, logic_0 ;
// the data bit is tied to '0' so that when the chip comes up, it
// will tell us whether there is a id register or not by looking at the
// tdo. if it is a '0', then it doesn't have a id register. if it is a
// '1' , then there is a id register
// Translation of the above: rule 9.1.1b states that the bypass register must
// be parallel-loaded with 0 in Capture-DR of all bypass instructions.
// Chapter 11 state that the LSB of the ID Code must be 1. Rule 6.2.1e
// states that in Test-Logic-Reset state, either the IDCODE instruction
// or (if IDCODE is not implemented) the BYPASS instruction must be
// parallel-loaded into the instruction register. Thus, we can tell
// whether IDCODE is implemented for a specific part by doing a 1-bit
// data Shift after Test-Logic-Reset.
wire din = logic_0;
wire cap = sel & capture;
wire te = sel & sen;
Mflipflop_sh dffld1(sout, din, te, ti, ~cap, tck) ;
//Mflipflop_h dffld1(sout, din, ~cap, tck) ;
endmodule
// this register provides the identity of the component and can be read
// by scanning out its contents. this is needed to identify each component
// after they are assembled on the board.
module idreg(sout,sel, capture, sen, ti, tck, logic_0, logic_1
);
output sout ;
input sel, capture, sen, ti, tck, logic_0, logic_1 ;
// the LSB is tied to '1', to indicate the presence of id register, when
// the chip comes up
// the contents of ID register is defined by three fields as follows
// VER is the version number which is 0x3 for pg3.0
// Part number is TBD - use 0x0000 (re Mogens' mail, 12/11/92)
// Manufacturer ID as per JEDEC is 0x04
// MSB LSB
// | | |
// BIT: 31 28|27 12|11 1|0
// 0101|0000000000000000|00000000100|1
// VER | PART NUMBER |FJ MANUF ID|
// 4-B | 16 BITS | 11 BITS |
// For pg3.1 tapeout, ver change from 4 to 5 (2/17/94)
// For pg2.6, version changed from 5 to 6 (5/18/94 athena)
// For pg3.2, version changed from 6 to 7 (5/19/94 athena)
// For pg3.4, version changed from 7 to 8 (8/29/94 athena)
// For EAGLE JTAG ID Register: 0x1016d06d
// for eagle 2.1 change to ver = 0x3 -
// wire [31:0] din = 32'h0000202F;
wire [31:0] din = {logic_0,
logic_0,
// logic_0,
logic_1,
logic_1,
logic_0,
logic_0,
logic_0,
logic_0,
logic_0,
logic_0,
logic_0,
logic_1,
logic_0,
logic_1,
logic_1,
logic_0,
logic_1,
logic_1,
logic_0,
logic_1,
logic_0,
logic_0,
logic_0,
logic_0,
logic_0,
logic_1,
logic_1,
logic_0,
logic_1,
logic_1,
logic_0,
logic_1};
wire cap = sel & capture;
wire te = sel & sen;
wire [31:0] out ;
wire sout = out[0] ;
Mflipflop_sh_32 ff1(out, din, te, {ti,out[31:1]}, ~cap, tck) ;
//Mflipflop_h_32 ff1(out, din, ~cap, tck) ;
endmodule
// this is the clock control register which is used to sample the stopped
// signal coming in from the clock_controller.
// Changed CCR so that it is scannable during CLKCTL instruction - 8/26/96
module ccr(sout, sel, capture, sen, ti, tck, trst_l, stopped, spare_ccr, logic_0);
output sout;
input sel, capture, sen, ti, tck, trst_l, stopped, spare_ccr, logic_0 ;
syncff_b sff1( out1, stopped, tck);
syncff_b sff2( sync_stopped, out1, tck);
syncff_b sff3( out2, spare_ccr, tck);
syncff_b sff4( sync_spare_ccr, out2, tck);
wire cap = sel & capture;
wire te = sel & sen;
//wire ti = logic_0 ;
Mflipflop_sh dffld1( stpd, sync_stopped, te, ti, ~cap, tck) ;
//Mflipflop_sr dffld1(stpd, sync_stopped, te, ti, trst_l, tck);
//Mflipflop_r dffld1(stpd, sync_stopped, trst_l, tck);
// Bit 0 of CCR not used - keep it in to maintain
// compatibility with Tsunami/Tsupernami.
Mflipflop_sh dffld2( sout, sync_spare_ccr, te, stpd, ~cap, tck) ;
//Mflipflop_sr dffld2(sout, sync_spare_ccr, te, stpd, trst_l, tck);
//Mflipflop_r dffld2(sout, sync_spare_ccr, trst_l, tck);
endmodule
// this module collects tdo(scan out) from all blocks and muxes them
// appropriately based on the block/mode that is being currently tested
module tdo_control(out4_tdo, inst,id_ring, isr_tdo, ccr_tdo,
bsr_tdo, id_tdo, byp_tdo, ir_tdo, sir, tckbar,tdi,trst_l, logic_0
);
output out4_tdo;
input [5:0] inst ;
input id_ring, isr_tdo, ccr_tdo, bsr_tdo, id_tdo,
byp_tdo, ir_tdo, sir, tckbar,tdi,trst_l, logic_0;
// See Bug 501 - must decode all the opcodes
wire selected_tdo =
// Shift-IR
sir ? ir_tdo : (
// idreg, or special reset action (see rule 6.2.1d)
((inst==6'b100000)||id_ring) ? id_tdo : (
// sel_int_scan or sel_dbg_scan
((inst==6'b010000)||(inst==6'b011111)) ? isr_tdo : (
// extest, ateintest, intest, sample
(inst[5:2]==4'b0000) ? bsr_tdo : (
// sel_ccr
(inst==6'b011110) ? ccr_tdo : (
// Default = bypass
byp_tdo ))))) ;
// the tdo outputs are finally clocked out on the falling edge of tck
// per the IEEE JTAG protocol.
// jtag_tdo signal (clock is inverted because the jtag spec says to latch the
// tdo signal on falling edge of the jtag clock). It will work even if it
// were to be clocked on the rising tck(and meet hold time for the
// succeding connection to the TDI port off chip. But we will abide by the spec.
// S1inv_c inv6(ckbar, tckbar);
// S1dff_d fe1(out3_tdo, out2_tdo, tckbar);
Mflipflop_noop fe1(out3_tdo, selected_tdo, tckbar);
// since the tdo output has to be active only during the Shift state(per
// IEEE JTAG protocol, the tdo output is enabled only during the
// Shift state. The shft signal called jtga_tdo_en is an output of JTAG block
// and will control the tristate buf at the JTAG_TDO ouput signal pad.
// added the following gating to ensure no x's on tdo without tck,
// which happens during normal simulation (July 10, 1991)
wire out4_tdo = (out3_tdo & trst_l) ;
endmodule
module syncff_b (
q, d, clk
);
output q ;
input d ;
input clk ;
Mflipflop_noop sff (q, d, clk) ;
endmodule
module MUX21(Z, A, B, S);
output Z;
input A, B,S;
wire Z = S ? B : A ;
endmodule
module MUX41(Z, D0, D1, D2, D3, A, B);
output Z;
input D0, D1, D2, D3, A, B;
wire w01, w23 ;
MUX21 m(Z, w01, w23, A) ;
MUX21 m01(w01, D0, D1, B) ;
MUX21 m23(w23, D2, D3, B) ;
endmodule
module Mflipflop_arh (out,in,enable_l,reset_l,clock);
output out;
input in;
input enable_l;
input reset_l;
input clock;
wire t;
MUX21 i0(t,in, out, enable_l);
Mflipflop_ar ar(out, t, reset_l, clock) ;
endmodule
// Remove this when it appears in cells.v
module Mflipflop_ar(out, in, async_reset_l, clock) ;
output out ;
input in ;
input async_reset_l ;
input clock ;
JSRFFA dff (.D(in), .CK(clock), .CL(async_reset_l), .PR(1'b1), .Q(out)) ;
endmodule
module Mflipflop_ar_4(out, in, async_reset_l, clock) ;
output [3:0] out ;
input [3:0] in ;
input async_reset_l ;
input clock ;
Mflipflop_ar Mflipflop_ar_3_0(out[0], in[0], async_reset_l, clock) ;
Mflipflop_ar Mflipflop_ar_3_1(out[1], in[1], async_reset_l, clock) ;
Mflipflop_ar Mflipflop_ar_3_2(out[2], in[2], async_reset_l, clock) ;
Mflipflop_ar Mflipflop_ar_3_3(out[3], in[3], async_reset_l, clock) ;
endmodule
| This page: |
Created: | Thu Aug 19 11:59:57 1999 |
| From: |
../../../sparc_v8/ssparc/clk_misc/rl_jtag_cntl/rtl/jtag_subblocks.v
|