assign  ld_ct     = ~dly_bsy ;

    assign  mode_ct   = ( ((cyc_reg == `DRD32N)|(cyc_reg == `DRD32P)) ?
                                1'b1 : 1'b0 );
    
    assign  inc_ct    = ~mc_mstb_l || (curr_st == `L3_WRP03C);

// add graphics control for add. incrementer.
	assign gr_s_blk	= ((curr_st >= `L3_GRDT7)&(curr_st <= `L3_GRDTB)) | 
			  ((curr_st >= `L3_GRDTC)&(curr_st <= `L3_GRDTL))|
			  ((curr_st >= `L3_GWRT4)&(curr_st <= `L3_GWRT6));
//			  ((curr_st >= L3_GWRTD)&(curr_st <= L3_GWRTF));

	assign 	gr_mode_ct =  ( ((cyc_reg == `GRD32P)|(cyc_reg == `GRD32H)) ?
                                1'b1 : 1'b0 );

	assign gr_inc_ct = ~mc_mstb_l || (curr_st == `L3_GWRT3) ;


    /* Generate the DPC control bus (dpct[5:0]) going to modules DPC_Core
     * and DPC_Cont (in dpc.v).
     * Generate new logic where needed (eg. registering bits 0 & 1 of MMU
     * addr bits) or alias existing signals to appropriate mc_dpct[] bits
     * (eg already registerd bit 2 of MMU address).  */
    /*==================================================================*/
    GReg1       ffh_dpct0(mc_dpct[0], mm_pa00, ss_clock, hld_mm );
    GReg1       ffh_dpct1(mc_dpct[1], mm_pa01, ss_clock, hld_mm );

    assign  mc_dpct[2] = qpa02 ;

    /* bit3 is 0 if access is for a byte only. Otherwize it is set to 1.*/
    assign  mc_dpct[3]	=	(	((cyc_reg==`DRMW1N)|(cyc_reg==`DRMW1P))
							 	? 1'b0 : 1'b1 );

    /* bit4 is set to 1 if the access is word or dword.*/
    assign  mc_dpct[4] = ( ((cyc_reg==`DRMW1N)|(cyc_reg==`DRMW2N)|
                            (cyc_reg==`DRMW1P)|(cyc_reg==`DRMW2P))
                           ? 1'b0 : 1'b1 );

    /* When bit5 is set to 1, it indicates a read cycle.*/
    assign  mc_dpct[5] = ~qwen ;


    /* Generate the acknowledge to RFR request.*/
    /*==================================================================*/
    assign  rf_ack_l    = ( (curr_st == `L3_CBR01) ? 1'b0 : 1'b1) ;

// IIe note : From PROM write, the IIe using the same protocol as the afx
//	      write. However, the IIe afx fifo counter will not be used
//	      for all prom access, a prom_p_reply is created to distinguish
//	      afx and prom p_reply.


    wire	prom_access_en  =   (falcon_exists & (mm_pa28==1'b0) & mm_fb_req & mm_issue_req & 
				    ((curr_st==`L1_IDLE) || (curr_st==`L1_CHECK))) ;

    wire	prom_access_dis =    (rst || (curr_st==`L2_CYCEND) || (curr_st==`L3_GRDTN)  ||
                                            ((curr_st==`L3_GWRT2) && (prom_p_reply==2'b10) &&
						~(cyc_reg==`GWR16H) && ~(cyc_reg==`GWR16P)) ||
                                            ((curr_st==`L3_GWRT8) && (prom_p_reply==2'b10))) ;

    S_sr_ff     ffsr_prom_ac(prom_access, prom_access_en, prom_access_dis , ss_clock);

    // wire	prom_wr_en	=    (prom_access & (cyc_reg[6:4]==3'b011) & s_reply);

    wire	prom_wr_en	=    (falcon_exists && (mm_pa28==1'b0) && 
				        ((`G_REQ)&&(`G_PAGE) && ~(`MM_RDX) && sync_t0 &&
					     ((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK)))) ||
				     (prom_access && (
					 (((curr_st==`L3_SYNC)&&sync_t0) && `GWRPX ) ||
					 (curr_st==`L3_GWRT3)  || 
					 ((curr_st==`L3_GROT3) && `GWRHX )));

    wire	prom_wr_dis	=    ((prom_p_reply==2'b10) || rst);

    S_sr_ff     ffsr_prom_wr(prom_wr_bsy, prom_wr_en, prom_wr_dis , ss_clock);

    wire	[1:0]	afx_p_reply;
// delete the prom_access qualifier.  This was causing failures in the lab
// on sumatra board when a pio write was immediately followed by an I-cache
// miss.  (The pio write reply was negated because of the prom access.  This
// caused the afxq to become busy and the mmu to hang waiting for an afx 
// timeout.)  
//    assign	afx_p_reply[1]  =   (pcic_p_reply[1] | p_reply[1]) & ~prom_access;
//    assign	afx_p_reply[0]  =   (pcic_p_reply[0] | p_reply[0]) & ~prom_access;
    assign	afx_p_reply[1]  =   (pcic_p_reply[1] | p_reply[1]) ;
    assign	afx_p_reply[0]  =   (pcic_p_reply[0] | p_reply[0]) ;

//
// logic for graphic control

//remove hold
//    GReg1       ffh_sync_t1(sync_t1, sync_t0, ss_clock, Gnd );
    Mflipflop_noop_1       ffh_sync_t1(sync_t1, sync_t0, ss_clock );
// since afx_to is already at sync_t1, no need to re-qualify

    assign  read_single = (p_reply[1] & p_reply[0]) |
			  (pcic_p_reply[1] & pcic_p_reply[0]) |
			  (prom_p_reply[1] & prom_p_reply[0]) | afx_to;

//    assign  read_single = p_reply[1] & ~p_reply[0];
//    assign  fifo_full = 1'b0;
//    assign  dead_cyc = 1'b0;
//	wire p_reply_err;
	
	wire	[2:0] dead_cyc_dr_dec;
	wire	[2:0] dead_cyc_gr_dec;
	wire	[2:0] dead_cyc_gw_dec;


	p_reply_count 	afx_count(fifo_full, afx_p_reply, prom_access,
				  dead_cyc_dr_dec, dead_cyc_gr_dec, dead_cyc_gw_dec,
				  p_reply_dec, incr_w_p_reply,
				  curr_st, rst,sync_t1, ss_clock, cyc_reg,
				  sp_sel, sp_sel_1, sp_sel_2, afx_to);

	timeout_count	afx_timeout_count(afx_to,
                        p_reply_dec,
                        curr_st,rst, aen,
                        sync_t1, ss_clock);

// only page req needs to count out.
// dr, (gr | gw)
// gw, (gr | rmw)
// gr, gw, -- not needed
// gr, (dr, dw, )
// gw, (dr, dw, )
// dw, (dr, gr, gw) -- not needed
// dr, dw -- done previously

// no need for MM_WR2 | MM_WR1 in dead_cyc_idle since greq

	wire	dead_cyc_idle;	
/*
	assign	dead_cyc_idle = (G_REQ)&&(G_PAGE) && ( 
				  ~(dead_cyc_dr_dec == 3'b000) ||
				  (~(dead_cyc_gw_dec <= 3'b010) && 
				   (`MM_RDX ))) 			||

				(MM_REQ)&&(IS_PAGE) && 
				 ((~(dead_cyc_gr_dec == 3'b000) ) ||
				  ~(dead_cyc_gw_dec == 3'b000));
*/
	wire	dead_cyc_idle_g_en;
	wire	dead_cyc_idle_d_en;
	assign	dead_cyc_idle_g_en = (`G_PAGE) && (~(dead_cyc_dr_dec == 3'b000) ||
                                     (~(dead_cyc_gw_dec <= 3'b010) &&
                                     (`MM_RDX )));
	assign	dead_cyc_idle_d_en = (`IS_PAGE) && ((~(dead_cyc_gr_dec == 3'b000) ) ||
                                     ~(dead_cyc_gw_dec == 3'b000));
	assign	dead_cyc_idle = dead_cyc_idle_g_en && (`G_REQ) || 
				dead_cyc_idle_d_en && (`MM_REQ) ;
// was this, timing = 6.39 set up, checked as 12.2
//	assign	dead_cyc_idle = dead_cyc_idle_g_en && (G_REQ2) || 
//				dead_cyc_idle_d_en && (MM_REQ2) ;

	wire	dead_idle_hld;
	wire	dead_cyc_idle_n;
	assign 	dead_idle_hld = mc_mbsy & odat_hld;

    GReg1   ffh_dead_idle_reg (dead_cyc_idle_n, dead_cyc_idle, ss_clock, dead_idle_hld );

// following is replacing the commented portion; 
 
        wire    dead_cyc_idle_n_en;
        assign  dead_cyc_idle_n_en = (dead_cyc_idle_n & (
                                 ~(dead_cyc_dr_dec == 3'b000)                           |
                                 ~(dead_cyc_gr_dec == 3'b000)                           |
                                 (~(dead_cyc_gw_dec <= 3'b010) &&
                                  (`GRDPX | `GRDHX))                    |
                                 (~(dead_cyc_gw_dec == 3'b000) &&
                                  ~(`GRDPX | `GRDHX)) ));
 
        assign  dead_cyc = dead_cyc_idle | dead_cyc_idle_n_en ;
 
 

/*
	assign	dead_cyc = dead_cyc_idle | 
			       (dead_cyc_idle_n & (
				 ~(dead_cyc_dr_dec == 3'b000) 				|
				 ~(dead_cyc_gr_dec == 3'b000) 				|
				 (~(dead_cyc_gw_dec <= 3'b010) && 
				  (`GRDPX | `GRDHX))			|
				 (~(dead_cyc_gw_dec == 3'b000) &&
				  ~(`GRDPX | `GRDHX)) ));
*/

endmodule

// This is the p_reply & dead_cyc counter


module p_reply_count(fifo_full, p_reply, prom_access,
			dead_cyc_dr_dec, dead_cyc_gr_dec, dead_cyc_gw_dec,
			p_reply_dec, incr_w_p_reply,
			curr_st,rst,
			sync_t1, ss_clock, cyc_reg, sp_sel, sp_sel_1, sp_sel_2, afx_to
			);
	output	fifo_full;
	output	[2:0] dead_cyc_dr_dec;
	output	[2:0] dead_cyc_gr_dec;
	output	[2:0] dead_cyc_gw_dec;
	output 	[2:0] p_reply_dec;
	output 	[2:0] incr_w_p_reply;
	input	[1:0] p_reply;
        input   [8:0] curr_st;
	input	rst;
	input	sync_t1;
	input	ss_clock;
	input	[6:0] cyc_reg;
	input	sp_sel;
	input	sp_sel_1;
	input	sp_sel_2;
	input	afx_to;
	input	prom_access;
//	wire [2:0] p_reply_dec;
	wire [2:0] dead_cyc_dr_dec;
	wire [2:0] dead_cyc_gr_dec;
	wire [2:0] dead_cyc_gw_dec;

//    assign  dead_cyc = 1'b0;
//	assign 	dead_cyc = ~(dead_cyc_dec == 3'b000);

    assign  fifo_full = (p_reply_dec == 3'b100);
//	assign p_reply_err = (p_reply_dec == 3'b101)|(p_reply_dec == 3'b110)|(p_reply_dec==3'b111);

	wire Gnd;
	assign Gnd = 1'b0;
// p_reply  counter specific.
//    wire    [2:0]   incr_w_p_reply;
        wire    ld_ct_p_reply, dec_ct_p_reply, inc_ct_p_reply;
        assign dec_ct_p_reply = (sync_t1 && (p_reply == 2'b10));
//        assign dec_ct_p_reply = (sync_t1 && (p_reply == 2'b11));
        assign inc_ct_p_reply = (((curr_st==`L3_GWRT1)||(curr_st==`L3_GWRT4)) && ~prom_access);

        assign ld_ct_p_reply = rst | afx_to;
 
    //------------- incr function --------------------------------
    //  Is a 2 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [2:0] f_decr_p_reply;
        input [2:0]     p_reply_dec;
        input           ld_ct_p_reply, inc_ct_p_reply, dec_ct_p_reply;
 
        begin
            f_decr_p_reply = p_reply_dec;
            if ( ld_ct_p_reply == 1'b1 ) begin  /* load the input. */
		f_decr_p_reply = 3'b000;
                end
            else if (( dec_ct_p_reply == 1'b1 )&(~(inc_ct_p_reply == 1'b1)) &
			(p_reply_dec > 3'b000)) begin  /* count up.*/
                        f_decr_p_reply    = p_reply_dec - 3'b001; // Modulo-2 counter.
                end
	    else if ((~(dec_ct_p_reply == 1'b1))&(inc_ct_p_reply == 1'b1 ))begin  /* count up.*/
                        f_decr_p_reply    = p_reply_dec + 3'b001; // Modulo-2 counter.
                end
        end
    endfunction
//remove hold
//    GReg3   ffh_col_inc_p_reply (p_reply_dec[2:0], incr_w_p_reply[2:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_p_reply (p_reply_dec[2:0], incr_w_p_reply[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_p_reply = f_decr_p_reply(p_reply_dec,ld_ct_p_reply,inc_ct_p_reply,dec_ct_p_reply);
// end p_reply counter

// dead_cyc_dr (loaded at RDP02B, ) counter specific.
    wire    [2:0]   incr_w_dead_cyc_dr;
        wire    ld_ct_dead_cyc_dr, dec_ct_dead_cyc_dr;
        assign dec_ct_dead_cyc_dr = ~ld_ct_dead_cyc_dr;
//        assign dec_ct_dead_cyc_dr = (curr_st==`L3_RDP02B) ;
        assign ld_ct_dead_cyc_dr = (curr_st==`L3_RDP02B) | rst ;
 
    //------------- incr function --------------------------------
    //  Is a 3 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [2:0] f_decr_dead_cyc_dr;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input [2:0]     dead_cyc_dr_dec;
        input           ld_ct_dead_cyc_dr, dec_ct_dead_cyc_dr;
 
        begin
            f_decr_dead_cyc_dr = dead_cyc_dr_dec;
            if ( ld_ct_dead_cyc_dr == 1'b1 ) begin  /* load the input. */
 
                case (({sp_sel_2, sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_dead_cyc_dr = 3'b010;
                        3'b001:  f_decr_dead_cyc_dr = 3'b011;
                        3'b010:  f_decr_dead_cyc_dr = 3'b011;
                        3'b011:  f_decr_dead_cyc_dr = 3'b100;
                        3'b100:  f_decr_dead_cyc_dr = 3'b101;
                        3'b101:  f_decr_dead_cyc_dr = 3'b101;
                        3'b110:  f_decr_dead_cyc_dr = 3'b110;
                        3'b111:  f_decr_dead_cyc_dr = 3'b110;
                        endcase
 
                end
            else if ( dec_ct_dead_cyc_dr == 1'b1 ) begin  /* count up.*/

		case (dead_cyc_dr_dec)
			3'b111:	f_decr_dead_cyc_dr = 3'b110;
			3'b110:	f_decr_dead_cyc_dr = 3'b101;
			3'b101:	f_decr_dead_cyc_dr = 3'b100;
			3'b100:	f_decr_dead_cyc_dr = 3'b011;
			3'b011:	f_decr_dead_cyc_dr = 3'b010;
			3'b010:	f_decr_dead_cyc_dr = 3'b001;
			3'b001:	f_decr_dead_cyc_dr = 3'b000;
			3'b000:	f_decr_dead_cyc_dr = 3'b000;
			endcase
                end
        end
    endfunction
//remove hold
//    GReg3   ffh_col_inc_dead_cyc_dr (dead_cyc_dr_dec[2:0], incr_w_dead_cyc_dr[2:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_dead_cyc_dr (dead_cyc_dr_dec[2:0], incr_w_dead_cyc_dr[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_dead_cyc_dr = f_decr_dead_cyc_dr(sp_sel,sp_sel_1,sp_sel_2,dead_cyc_dr_dec,ld_ct_dead_cyc_dr,dec_ct_dead_cyc_dr);
// end dead_cyc_dr counter

// dead_cyc_gr (loaded at L3_GRDTN, ) counter specific.
    wire    [2:0]   incr_w_dead_cyc_gr;
        wire    ld_ct_dead_cyc_gr, dec_ct_dead_cyc_gr;
        assign dec_ct_dead_cyc_gr = ~ld_ct_dead_cyc_gr;
//        assign dec_ct_dead_cyc_gr = (curr_st==`L3_RDP02B) ;
        assign ld_ct_dead_cyc_gr =  (curr_st==`L3_GRDTN) | rst ;
 
    //------------- incr function --------------------------------
    //  Is a 3 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [2:0] f_decr_dead_cyc_gr;
        input           sp_sel, sp_sel_1, sp_sel_2;
        input [2:0]     dead_cyc_gr_dec;
        input           ld_ct_dead_cyc_gr, dec_ct_dead_cyc_gr;
 
        begin
            f_decr_dead_cyc_gr = dead_cyc_gr_dec;
            if ( ld_ct_dead_cyc_gr == 1'b1 ) begin  /* load the input. */
 
                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_dead_cyc_gr = 3'b100;
                        3'b001:  f_decr_dead_cyc_gr = 3'b100;
                        3'b010:  f_decr_dead_cyc_gr = 3'b100;
                        3'b011:  f_decr_dead_cyc_gr = 3'b100;
                        3'b100:  f_decr_dead_cyc_gr = 3'b101;
                        3'b101:  f_decr_dead_cyc_gr = 3'b101;
                        3'b110:  f_decr_dead_cyc_gr = 3'b110;
                        3'b111:  f_decr_dead_cyc_gr = 3'b110;
                        endcase
 
                end
            else if ( dec_ct_dead_cyc_gr == 1'b1 ) begin  /* count up.*/

                case (dead_cyc_gr_dec)
                        3'b111: f_decr_dead_cyc_gr = 3'b110;
                        3'b110: f_decr_dead_cyc_gr = 3'b101;
                        3'b101: f_decr_dead_cyc_gr = 3'b100;
                        3'b100: f_decr_dead_cyc_gr = 3'b011;
                        3'b011: f_decr_dead_cyc_gr = 3'b010;
                        3'b010: f_decr_dead_cyc_gr = 3'b001;
                        3'b001: f_decr_dead_cyc_gr = 3'b000;
                        3'b000: f_decr_dead_cyc_gr = 3'b000;
                        endcase
                end
        end
    endfunction
//remove hold
//    GReg3   ffh_col_inc_dead_cyc_gr (dead_cyc_gr_dec[2:0], incr_w_dead_cyc_gr[2:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_dead_cyc_gr (dead_cyc_gr_dec[2:0], incr_w_dead_cyc_gr[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_dead_cyc_gr = f_decr_dead_cyc_gr(sp_sel,sp_sel_1,sp_sel_2,dead_cyc_gr_dec,ld_ct_dead_cyc_gr,dec_ct_dead_cyc_gr);
// end dead_cyc_gr counter
 
// dead_cyc_gw (loaded at L3_GWRT8, L3_GWRT2 & ~dword, ) counter specific.
    wire    [2:0]   incr_w_dead_cyc_gw;
        wire    ld_ct_dead_cyc_gw, dec_ct_dead_cyc_gw;
        assign dec_ct_dead_cyc_gw = ~ld_ct_dead_cyc_gw;
//        assign dec_ct_dead_cyc_gw = (curr_st==`L3_RDP02B) ;
        assign ld_ct_dead_cyc_gw =  rst | (curr_st==`L3_GWRT8) |
                                    ((curr_st==`L3_GWRT2) & ~((cyc_reg == `GWR16P) |
                                                          (cyc_reg == `GWR16H)))
                                                        ; 
 
    //------------- incr function --------------------------------
    //  Is a 3 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [2:0] f_decr_dead_cyc_gw;
        input           sp_sel, sp_sel_1,sp_sel_2;
        input [2:0]     dead_cyc_gw_dec;
        input           ld_ct_dead_cyc_gw, dec_ct_dead_cyc_gw;
 
        begin
            f_decr_dead_cyc_gw = dead_cyc_gw_dec;
            if ( ld_ct_dead_cyc_gw == 1'b1 ) begin  /* load the input. */
 
                case (({sp_sel_2,sp_sel_1,sp_sel}))      //PARALLEL_CASE
                        3'b000:  f_decr_dead_cyc_gw = 3'b100;
                        3'b001:  f_decr_dead_cyc_gw = 3'b100;
                        3'b010:  f_decr_dead_cyc_gw = 3'b100;
                        3'b011:  f_decr_dead_cyc_gw = 3'b100;
                        3'b100:  f_decr_dead_cyc_gw = 3'b101;
                        3'b101:  f_decr_dead_cyc_gw = 3'b101;
                        3'b110:  f_decr_dead_cyc_gw = 3'b110;
                        3'b111:  f_decr_dead_cyc_gw = 3'b110;
                        endcase
 
                end
            else if ( dec_ct_dead_cyc_gw == 1'b1 ) begin  /* count up.*/

                case (dead_cyc_gw_dec)
                        3'b111: f_decr_dead_cyc_gw = 3'b110;
                        3'b110: f_decr_dead_cyc_gw = 3'b101;
                        3'b101: f_decr_dead_cyc_gw = 3'b100;
                        3'b100: f_decr_dead_cyc_gw = 3'b011;
                        3'b011: f_decr_dead_cyc_gw = 3'b010;
                        3'b010: f_decr_dead_cyc_gw = 3'b001;
                        3'b001: f_decr_dead_cyc_gw = 3'b000;
                        3'b000: f_decr_dead_cyc_gw = 3'b000;
                        endcase
                end
        end
    endfunction
//remove hold
//    GReg3   ffh_col_inc_dead_cyc_gw (dead_cyc_gw_dec[2:0], incr_w_dead_cyc_gw[2:0], ss_clock, Gnd );
    Mflipflop_noop_3   ffh_col_inc_dead_cyc_gw (dead_cyc_gw_dec[2:0], incr_w_dead_cyc_gw[2:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_dead_cyc_gw = f_decr_dead_cyc_gw(sp_sel,sp_sel_1,sp_sel_2,dead_cyc_gw_dec,ld_ct_dead_cyc_gw,dec_ct_dead_cyc_gw);
// end dead_cyc_gw counter
 

 

endmodule



module timeout_count(afx_to, 
                        p_reply_dec,
                        curr_st,rst, aen,
                        sync_t1, ss_clock);
        output  afx_to;
        input   [2:0] p_reply_dec;
        input   [8:0] curr_st;
        input   rst;
        input   aen;
        input   sync_t1;
        input   ss_clock;

    wire    [10:0]   timeout_dec;
    wire    [10:0]   incr_w_timeout;
        wire    ld_ct_timeout, inc_ct_timeout;


    assign  afx_to = (timeout_dec == 11'b11111111111) & inc_ct_timeout;

        wire Gnd;
        assign Gnd = 1'b0;
// timeout  counter specific.
        assign inc_ct_timeout = sync_t1 & (!(p_reply_dec == 3'b000) 
					    || (curr_st == `L3_GRDT4) || (curr_st == `L3_GRDTA) || (curr_st == `L3_GRDTG)
					    || (curr_st == `L3_GRDTM) );
        assign ld_ct_timeout = rst | (sync_t1 & aen);
 
    //------------- incr function --------------------------------
    //  Is a 2 bit loadable-decrementor used for decrementing the
    //  column address in block type accesses (I$, D$, SBus).
    //-------------------------------------------------------------
    function [10:0] f_decr_timeout;
        input [10:0]     timeout_dec;
        input           ld_ct_timeout, inc_ct_timeout;
 
        begin
            f_decr_timeout = timeout_dec;
            if ( ld_ct_timeout == 1'b1 ) begin  /* load the input. */
                f_decr_timeout = 11'b00000000000;
                end
            else if ((timeout_dec < 11'b11111111111)&(inc_ct_timeout == 1'b1 ))begin  /* count up.*/
                        f_decr_timeout    = timeout_dec + 11'b00000000001; // Modulo-2 counter.
                end
        end
    endfunction
//remove hold
//    GReg11   ffh_col_inc_timeout (timeout_dec[10:0], incr_w_timeout[10:0], ss_clock, Gnd );
    Mflipflop_noop_11   ffh_col_inc_timeout (timeout_dec[10:0], incr_w_timeout[10:0], ss_clock );
    //-------------------------------------------------------------
    assign  incr_w_timeout = f_decr_timeout(timeout_dec,ld_ct_timeout,inc_ct_timeout);
// end timeout counter
 

endmodule