/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/******************************************************************************/
/****************************************************************************
* @(#)rl_rfr.v 1.13 7/28/93
* rl_rfr.v
*
* Description:
* The RFR block.
* After reset, RFR will enter the force-refresh state, where it
* asserts "rf_cbr" and "rf_rreq_l" signal to MCB. It will stay
* in this state until MCB has returned "mc_rack_l" 8 times,
* confirming that 8 CbR refresh cycles are performed (required
* for proper init of DRAMs after powerup). At this time, RFR
* will negate both the "rf_rreq_l" and "rf_cbr" and will enter
* its normal operation mode, where it will assert "rf_rreq_l" in
* the intervals determined by the state of "mm_rfr_cntl" bits.
* NOTE:
* 1) For proper initialization (per DRAM spec), after power-up,
* DRAMs require a 200us 'quiet' time (no cycles) followed by
* 8 refresh cycles (CbR refs in this case).
* The reset input to 'tsunami' must ensure that it will be
* longer than 200us for power-up reset, but for any subsequent
* resets, it must ensure it will be no longer than ~100us, so
* as not to loose DRAM data during non-powerup resets. This
* 100us is equal to ~7 normal CbR intervals (~15us each). If
* a reset pulse takes this long, it will be like loosing 7
* CbR refresh cycles, which will be cought up by the 8 CbR
* refresh cycles that happen immidiatelly after reset.
* 2) The 8 Cbr ref cycles take about 75 ss_clock periods.
* 3) There is no way to avoid the initial 8 CbR ref-cycs,
* unless verilog "force" command is used to fake the states.
*
*
* Dependencies:
*
*
*
*
****************************************************************************/
/************************************************************************
* A 6-bit counter, used to devide the system clock by 64, to generate
* a slow clock (mc64_l) which is used by other counters and timers in
* RFR block.
* Note:!!! mc64_l has a 64:1 duty cycle.... ie. It is Low for 1 ss_clock
* and High for 63 ss_clocks. This allows it to be used as a
* gate-signal for ss_clock (gate when Low!). It also remains asserted
* (Low) during reset, which allows rest of refresh circuit to be
* clocked at ss_clock speed, init-ing itself.
* (A simple 6 FF chain, forming a ripple counter by 2 added FFs as
* final stage sync-ers with ss_clock, will be a simpler circuit.)
*/
![[Up: rl_rfr div64]](v2html-up.gif)
module rl_div64
(mc64_l, ss_clock, rf_cbr);
output mc64_l;
input rf_cbr;
input ss_clock;
wire [05:00] fnc_in; /* Input to the div_fnc (register o/p).*/
wire [05:00] fnc_out; /* Output from div_fnc (register i/p).*/
wire Gnd = 1'b0;
//remove hold
// GReg6 ffh_div64(fnc_in[5:0], fnc_out[5:0], ss_clock, Gnd) ;
// GReg1 ffh_fnc5dly(fnc5dly, fnc_in[5], ss_clock, Gnd) ;
Mflipflop_noop_6 ffh_div64(fnc_in[5:0], fnc_out[5:0], ss_clock) ;
Mflipflop_noop_1 ffh_fnc5dly(fnc5dly, fnc_in[5], ss_clock) ;
/*----------------- div_fnc function -------------------------------
* This is the combo-logic to generate a 6-bit counter/divider, when
* coupled with 6 d-flops (Div64 instance of GReg6).
*--------------------------------------------------------------------*/
function [5:0] div_fnc;
input [05:00] fnc_in;
input rf_cbr;
begin
if (rf_cbr == 1'b1) begin
div_fnc = 6'b000000 ;
end
else begin
div_fnc = fnc_in + 1'b1 ;
end
end
endfunction
/*-------------------------------------------------------------------*/
assign fnc_out = div_fnc(fnc_in, rf_cbr) ;
assign mc64_l = ( (rf_cbr |(fnc_in[5] & ~fnc5dly)) ? 1'b0 : 1'b1 ) ;
endmodule
// Mhz higher, refresh frequency lower
/************************************************************************
* The Refresh-rate lookup table!
* mm_rf_cntl[2:0] start_count
* [0 1 1 ] [ 3 2 1 0 ] Ref.Rate
* ------------- ----------- --------------------------------------
* 0 0 0 0 0 1 0 10MHz sys clock (ref every 128 clks)
* 0 0 1 0 0 0 0 No Refresh
* 0 1 0 1 0 1 1 48MHz sys clock (ref every 704 clks)
* 0 1 1 1 1 1 0 60MHz sys clock (ref every 896 clks)
*
* 1 0 0 1 0 0 1 1 83MHz sys clock (ref every 1216 clks)
* 1 0 1 1 0 1 0 0 0 0 45MHz for low refresh DRAM.(5120 ck)
* 1 1 0 1 0 1 1 0 100MHz sys clock (ref every 1408 clks)
* 1 1 1 1 1 1 0 0 100MHz sys clock (ref every 1792 clks)
*power_down & 1 x x x 1 0 1 1 1 1 1 self refresh DRAM.(12032 ck)(deleted)
*/
module rl_refrate ( start_count, mm_rf_cntl
);
output [6:0] start_count;
input [2:0] mm_rf_cntl;
wire Gnd = 1'b0;
assign start_count[0] = ( (mm_rf_cntl[2:0]==3'b010 | mm_rf_cntl[2:0]==3'b100) ? 1'b1 : 1'b0 );
assign start_count[1] = ( (mm_rf_cntl[2:0]==3'b000 | mm_rf_cntl[2:0]==3'b010
| mm_rf_cntl[2:0]==3'b011 | mm_rf_cntl[2:0]==3'b100
| mm_rf_cntl[2:0]==3'b110) ? 1'b1 : 1'b0 );
assign start_count[2] = ( (mm_rf_cntl[2:0]==3'b011 | mm_rf_cntl[2:0]==3'b110
| mm_rf_cntl[2:0]==3'b111) ? 1'b1 : 1'b0 );
assign start_count[3] = ( (mm_rf_cntl[2:0]==3'b011 | mm_rf_cntl[2:0]==3'b010
| mm_rf_cntl[2:0]==3'b111) ? 1'b1 : 1'b0 );
assign start_count[4] = ( (mm_rf_cntl[2]==1'b1) ? 1'b1 : 1'b0 );
// assign start_count[4] = ( (mm_rf_cntl[2:0]==3'b100 | mm_rf_cntl[2:0]==3'b101) ? 1'b1 : 1'b0 );
assign start_count[5] = 1'b0;
assign start_count[6] = ( (mm_rf_cntl[2:0]==3'b101) ? 1'b1 : 1'b0 );
endmodule
/************************************************************************
* The 7-bit loadable down-counter, generating the refresh request interval.
*/
module rl_reqtimer( uflow, start_count, mc64_l, ss_clock, rf_cbr);
output uflow;
input [6:0] start_count;
input mc64_l, ss_clock, rf_cbr;
wire [6:0] dc_in_unqual;
wire [6:0] dc_in; /* Input to the ref_tim_fnc (register o/p).*/
wire [6:0] dc_out; /* Output from ref_tim_fnc (register i/p).*/
wire hld ;
GReg7 ffh_reqtim(dc_in[6:0], dc_out[6:0], ss_clock, hld) ;
/*----------------- ref_tim_fnc function -------------------------------
* This is the combo-logic to generate a 7-bit down-counter, which
* reloads itself at 0 and generates an under-flow flag (1cycle long).
*--------------------------------------------------------------------*/
// function [7:0] ref_tim_fnc;
function [6:0] ref_tim_fnc;
input [6:0] dc_in;
input [6:0] start_count;
input rf_cbr;
begin
if (rf_cbr==1'b1)
begin
ref_tim_fnc = 7'h00;
end
else begin
case (dc_in)
7'h7f : ref_tim_fnc[6:0] = 7'h7e;
7'h7e : ref_tim_fnc[6:0] = 7'h7d;
7'h7d : ref_tim_fnc[6:0] = 7'h7c;
7'h7c : ref_tim_fnc[6:0] = 7'h7b;
7'h7b : ref_tim_fnc[6:0] = 7'h7a;
7'h7a : ref_tim_fnc[6:0] = 7'h79;
7'h79 : ref_tim_fnc[6:0] = 7'h78;
7'h78 : ref_tim_fnc[6:0] = 7'h77;
7'h77 : ref_tim_fnc[6:0] = 7'h76;
7'h76 : ref_tim_fnc[6:0] = 7'h75;
7'h75 : ref_tim_fnc[6:0] = 7'h74;
7'h74 : ref_tim_fnc[6:0] = 7'h73;
7'h73 : ref_tim_fnc[6:0] = 7'h72;
7'h72 : ref_tim_fnc[6:0] = 7'h71;
7'h71 : ref_tim_fnc[6:0] = 7'h70;
7'h70 : ref_tim_fnc[6:0] = 7'h6f;
7'h6f : ref_tim_fnc[6:0] = 7'h6e;
7'h6e : ref_tim_fnc[6:0] = 7'h6d;
7'h6d : ref_tim_fnc[6:0] = 7'h6c;
7'h6c : ref_tim_fnc[6:0] = 7'h6b;
7'h6b : ref_tim_fnc[6:0] = 7'h6a;
7'h6a : ref_tim_fnc[6:0] = 7'h69;
7'h69 : ref_tim_fnc[6:0] = 7'h68;
7'h68 : ref_tim_fnc[6:0] = 7'h67;
7'h67 : ref_tim_fnc[6:0] = 7'h66;
7'h66 : ref_tim_fnc[6:0] = 7'h65;
7'h65 : ref_tim_fnc[6:0] = 7'h64;
7'h64 : ref_tim_fnc[6:0] = 7'h63;
7'h63 : ref_tim_fnc[6:0] = 7'h62;
7'h62 : ref_tim_fnc[6:0] = 7'h61;
7'h61 : ref_tim_fnc[6:0] = 7'h60;
7'h60 : ref_tim_fnc[6:0] = 7'h5f;
7'h5f : ref_tim_fnc[6:0] = 7'h5e;
7'h5e : ref_tim_fnc[6:0] = 7'h5d;
7'h5d : ref_tim_fnc[6:0] = 7'h5c;
7'h5c : ref_tim_fnc[6:0] = 7'h5b;
7'h5b : ref_tim_fnc[6:0] = 7'h5a;
7'h5a : ref_tim_fnc[6:0] = 7'h59;
7'h59 : ref_tim_fnc[6:0] = 7'h58;
7'h58 : ref_tim_fnc[6:0] = 7'h57;
7'h57 : ref_tim_fnc[6:0] = 7'h56;
7'h56 : ref_tim_fnc[6:0] = 7'h55;
7'h55 : ref_tim_fnc[6:0] = 7'h54;
7'h54 : ref_tim_fnc[6:0] = 7'h53;
7'h53 : ref_tim_fnc[6:0] = 7'h52;
7'h52 : ref_tim_fnc[6:0] = 7'h51;
7'h51 : ref_tim_fnc[6:0] = 7'h50;
7'h50 : ref_tim_fnc[6:0] = 7'h4f;
7'h4f : ref_tim_fnc[6:0] = 7'h4e;
7'h4e : ref_tim_fnc[6:0] = 7'h4d;
7'h4d : ref_tim_fnc[6:0] = 7'h4c;
7'h4c : ref_tim_fnc[6:0] = 7'h4b;
7'h4b : ref_tim_fnc[6:0] = 7'h4a;
7'h4a : ref_tim_fnc[6:0] = 7'h49;
7'h49 : ref_tim_fnc[6:0] = 7'h48;
7'h48 : ref_tim_fnc[6:0] = 7'h47;
7'h47 : ref_tim_fnc[6:0] = 7'h46;
7'h46 : ref_tim_fnc[6:0] = 7'h45;
7'h45 : ref_tim_fnc[6:0] = 7'h44;
7'h44 : ref_tim_fnc[6:0] = 7'h43;
7'h43 : ref_tim_fnc[6:0] = 7'h42;
7'h42 : ref_tim_fnc[6:0] = 7'h41;
7'h41 : ref_tim_fnc[6:0] = 7'h40;
7'h40 : ref_tim_fnc[6:0] = 7'h3f;
7'h3f : ref_tim_fnc[6:0] = 7'h3e;
7'h3e : ref_tim_fnc[6:0] = 7'h3d;
7'h3d : ref_tim_fnc[6:0] = 7'h3c;
7'h3c : ref_tim_fnc[6:0] = 7'h3b;
7'h3b : ref_tim_fnc[6:0] = 7'h3a;
7'h3a : ref_tim_fnc[6:0] = 7'h39;
7'h39 : ref_tim_fnc[6:0] = 7'h38;
7'h38 : ref_tim_fnc[6:0] = 7'h37;
7'h37 : ref_tim_fnc[6:0] = 7'h36;
7'h36 : ref_tim_fnc[6:0] = 7'h35;
7'h35 : ref_tim_fnc[6:0] = 7'h34;
7'h34 : ref_tim_fnc[6:0] = 7'h33;
7'h33 : ref_tim_fnc[6:0] = 7'h32;
7'h32 : ref_tim_fnc[6:0] = 7'h31;
7'h31 : ref_tim_fnc[6:0] = 7'h30;
7'h30 : ref_tim_fnc[6:0] = 7'h2f;
7'h2f : ref_tim_fnc[6:0] = 7'h2e;
7'h2e : ref_tim_fnc[6:0] = 7'h2d;
7'h2d : ref_tim_fnc[6:0] = 7'h2c;
7'h2c : ref_tim_fnc[6:0] = 7'h2b;
7'h2b : ref_tim_fnc[6:0] = 7'h2a;
7'h2a : ref_tim_fnc[6:0] = 7'h29;
7'h29 : ref_tim_fnc[6:0] = 7'h28;
7'h28 : ref_tim_fnc[6:0] = 7'h27;
7'h27 : ref_tim_fnc[6:0] = 7'h26;
7'h26 : ref_tim_fnc[6:0] = 7'h25;
7'h25 : ref_tim_fnc[6:0] = 7'h24;
7'h24 : ref_tim_fnc[6:0] = 7'h23;
7'h23 : ref_tim_fnc[6:0] = 7'h22;
7'h22 : ref_tim_fnc[6:0] = 7'h21;
7'h21 : ref_tim_fnc[6:0] = 7'h20;
7'h20 : ref_tim_fnc[6:0] = 7'h1f;
7'h1f : ref_tim_fnc[6:0] = 7'h1e;
7'h1e : ref_tim_fnc[6:0] = 7'h1d;
7'h1d : ref_tim_fnc[6:0] = 7'h1c;
7'h1c : ref_tim_fnc[6:0] = 7'h1b;
7'h1b : ref_tim_fnc[6:0] = 7'h1a;
7'h1a : ref_tim_fnc[6:0] = 7'h19;
7'h19 : ref_tim_fnc[6:0] = 7'h18;
7'h18 : ref_tim_fnc[6:0] = 7'h17;
7'h17 : ref_tim_fnc[6:0] = 7'h16;
7'h16 : ref_tim_fnc[6:0] = 7'h15;
7'h15 : ref_tim_fnc[6:0] = 7'h14;
7'h14 : ref_tim_fnc[6:0] = 7'h13;
7'h13 : ref_tim_fnc[6:0] = 7'h12;
7'h12 : ref_tim_fnc[6:0] = 7'h11;
7'h11 : ref_tim_fnc[6:0] = 7'h10;
7'h10 : ref_tim_fnc[6:0] = 7'h0f;
7'h0f : ref_tim_fnc[6:0] = 7'h0e;
7'h0e : ref_tim_fnc[6:0] = 7'h0d;
7'h0d : ref_tim_fnc[6:0] = 7'h0c;
7'h0c : ref_tim_fnc[6:0] = 7'h0b;
7'h0b : ref_tim_fnc[6:0] = 7'h0a;
7'h0a : ref_tim_fnc[6:0] = 7'h09;
7'h09 : ref_tim_fnc[6:0] = 7'h08;
7'h08 : ref_tim_fnc[6:0] = 7'h07;
7'h07 : ref_tim_fnc[6:0] = 7'h06;
7'h06 : ref_tim_fnc[6:0] = 7'h05;
7'h05 : ref_tim_fnc[6:0] = 7'h04;
7'h04 : ref_tim_fnc[6:0] = 7'h03;
7'h03 : ref_tim_fnc[6:0] = 7'h02;
7'h02 : ref_tim_fnc[6:0] = 7'h01;
7'h01 : ref_tim_fnc[6:0] = 7'h00;
7'h00 : ref_tim_fnc[6:0] = start_count[6:0];
//synopsys translate_off
default begin
ref_tim_fnc[6:0] = 7'h7f;
//$display("DEFAULT!!!");
end
//synopsys translate_on
endcase
end
end
endfunction
/*--------------------------------------------------------------------*/
assign dc_out[6:0] = ref_tim_fnc(dc_in[6:0], start_count[6:0], rf_cbr);
assign hld = (mc64_l==1'b1) & (dc_in[6:0]!=7'h1) ;
assign uflow = ( (dc_in[6:0]==7'h1) ? 1'b1 : 1'b0);
endmodule
/************************************************************************
* The logic to generate the 1st 8 CbRs after reset and then generate
* normal requests.
*/
module rl_reqgen( rf_cbr, rf_rreq_l, uflow, mc_rack_l, rst, ss_clock
);
output rf_cbr; /* High while in initial CbR stage.*/
output rf_rreq_l; /* Ref request to MCB.*/
// power_down_mode is deactivated.
input uflow; /* High for 1 ss_clock when Req-timer overflows.*/
input mc_rack_l; /* Ref-req acknowledge from MCB.*/
input rst, ss_clock;
wire [02:00] fnc_in; /* Input to the wait8 (register o/p).*/
wire [02:00] fnc_out; /* Output from wait8 (register i/p).*/
wire end_cbr;
wire no_cbr;
wire do_req;
wire mc_rack;
wire Gnd = 1'b0;
assign end_cbr= ( (fnc_in==3'b111) ? 1'b1 : 1'b0 );
S_sr_ff ffsr_cbr_end(cbr_end, end_cbr, rst, ss_clock);
assign no_cbr= (cbr_end & ~mc_rack_l);
S_sr_ff ffsr_rf_cbr(rf_cbr, rst, no_cbr, ss_clock);
assign mc_rack = ~mc_rack_l; /* the SET sig to "Req" S_sr_ff.*/
assign do_req = ~cbr_end | uflow ; /* the RESET sig to "Req" S_sr_ff.*/
// S_sr_ff ffsr_req(rf_rreq_l, mc_rack, do_req, ss_clock);
wire [5:0] req_count_dec;
S_sr_ff ffsr_req(rf_rreq_l, mc_rack, (do_req | ~(req_count_dec == 6'b000000) & ~mc_rack), ss_clock);
//remove hold
// GReg1 ffh_uflow_n(uflow_p, uflow, ss_clock, Gnd) ;
Mflipflop_noop_1 ffh_uflow_n(uflow_p, uflow, ss_clock) ;
wire uflow_req;
assign uflow_req = ~uflow_p & uflow;
// following is added for slow respond from afx.
//
// req_count counter specific.
wire [5:0] incr_w_req_count;
wire ld_ct_req_count, dec_ct_req_count, inc_ct_req_count;
assign dec_ct_req_count = mc_rack;
assign inc_ct_req_count = uflow_req;
assign ld_ct_req_count = rst;
//------------- incr function --------------------------------
// Is a 4 bit loadable-decrementor used for decrementing the
// column address in block type accesses (I$, D$, SBus).
//-------------------------------------------------------------
function [5:0] f_decr_req_count;
input [5:0] req_count_dec;
input ld_ct_req_count, inc_ct_req_count, dec_ct_req_count;
begin
f_decr_req_count = req_count_dec;
if ( ld_ct_req_count == 1'b1 ) begin /* load the input. */
f_decr_req_count = 6'b000000;
end
else if (( dec_ct_req_count == 1'b1 )&(~(inc_ct_req_count == 1'b1)) &
(req_count_dec > 6'b000000)) begin /* count up.*/
f_decr_req_count = req_count_dec - 6'b000001; // Modulo-2 counter.
end
else if ((~(dec_ct_req_count == 1'b1))&(inc_ct_req_count == 1'b1 ) &
(req_count_dec < 6'b111111))begin /* count up.*/
f_decr_req_count = req_count_dec + 6'b000001; // Modulo-2 counter.
end
end
endfunction
//remove hold
// GReg6 ffh_col_inc_req_count (req_count_dec[5:0], incr_w_req_count[5:0], ss_clock, Gnd );
Mflipflop_noop_6 ffh_col_inc_req_count (req_count_dec[5:0], incr_w_req_count[5:0], ss_clock );
//-------------------------------------------------------------
assign incr_w_req_count = f_decr_req_count(req_count_dec,ld_ct_req_count,inc_ct_req_count,dec_ct_req_count);
// end req_count counter
// These are for self-ref dram.
/*
wire first_uflow, second_uflow;
S_sr_ff first_uflow_reg(first_uflow, uflow, rst_count_rst, ss_clock);
assign second_uflow = first_uflow & uflow;
S_sr_ff second_uflow_reg(enough_count, second_uflow, rst_count_rst, ss_clock);
*/
//remove hold
// GReg3 ffh_countcbr (fnc_in[2:0], fnc_out[2:0], ss_clock, Gnd) ;
Mflipflop_noop_3 ffh_countcbr (fnc_in[2:0], fnc_out[2:0], ss_clock) ;
/*----------------- wait8 function -------------------------------
* This is the combo-logic for tracking the initial 8 CbR ref-cycles. It
* counts from 0 to 7 and stops on 7 till reset again when (rst==1).
*--------------------------------------------------------------------*/
function [2:0] wait8;
input [02:00] fnc_in;
input mc_rack;
input rst;
begin
if (rst==1'b1) begin
wait8 = 3'b000 ;
end
else begin
case (mc_rack)
1'b1: wait8 = fnc_in + 1'b1 ;
1'b0: wait8 = fnc_in ;
endcase
end
end
endfunction
/*-------------------------------------------------------------------*/
assign fnc_out = wait8(fnc_in, mc_rack,rst ) ;
endmodule
/************************************************************************
* The rfr block !
*/
module rl_rfr ( rf_cbr, rf_rreq_l,
ss_clock, ss_reset, mc_rack_l, mm_rf_cntl
);
output rf_cbr;
output rf_rreq_l;
input ss_clock;
input ss_reset;
input mc_rack_l;
input [2:0] mm_rf_cntl;
wire mc64_l;
wire [6:0] start_count;
wire uflow;
rl_div64 div64 (mc64_l, ss_clock, rf_cbr);
rl_refrate refrate (start_count, mm_rf_cntl
);
rl_reqtimer reqtimer (uflow, start_count, mc64_l, ss_clock, rf_cbr);
rl_reqgen reqgen (rf_cbr, rf_rreq_l, uflow,
mc_rack_l, ss_reset, ss_clock
);
endmodule
| This page: |
Created: | Thu Aug 19 12:00:29 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_rfr.v
|