output IT
; // incomming data to core
inout X;
// Verilog body for JBS13SN
wire MD1_ ;
wire MD2_ ;
wire OT_ ;
wire ENO_ ;
wire tmg1m1_out ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire tmg1m1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD1_, MD1) ;
not g2(MD2_, MD2) ;
not g3(OT_, OT) ;
not g4(ENO_, ENO) ;
UDP_MUX21 g5(tmg1m1_out, jtag_q, OT_, MD1_) ;
not g6(ENC, ENC_) ;
not g7(tmg1m1_out_, tmg1m1_out) ;
and g8(bscn_xd0, ENC, tmg1m1_out) ;
or g9(bscn_d0, ENC_, tmg1m1_out_) ;
or g10(bscn_xd1, ENC_, tmg1m1_out) ;
and g11(bscn_d1, ENC, tmg1m1_out_) ;
not g12(tmg2m3_b, X) ;
UDP_MUX21 g13(IT, jtag_q, tmg2m3_b, MD2_) ;
not g14(bck, XBCK) ;
not g15(xack, ACK) ;
not g16(xclk, CK) ;
not g17(clk, xclk) ;
not g18(xupd, UP) ;
not g19(upd, xupd) ;
and g20(jtag_x1, OT_, ENO) ;
and g21(jtag_x2, ENO_, tmg2m3_b) ;
nor g22(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g23(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g24(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g25(SO, jtag_latch2_out) ;
UDP_LATCH g26(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g27(jtag_q, jtag_latch3_out) ;
not g28(out_buf_a, bscn_xd0) ;
not g29(out_buf_b, bscn_xd1) ;
xor g30(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g31(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Bidirectional cell
module JBD11SN(ENC_, OT, ENO, SI, CK, UP, ACK, XBCK, MD1,
MD2, SO, IT, X);
input ENC_; // tri-state enable, 0-tristate, 1-bistate
input OT; // outgoing data from core
input ENO; // jtag_ff: 1-sel_OT_data, 0-sel_PAD_data
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD1; // 0-sel_pad_data, 1-sel_jtag_ff
input MD2; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // incomming data to core
inout X;
// Verilog body for JBD11SN
wire MD1_ ;
wire MD2_ ;
wire OT_ ;
wire ENO_ ;
wire tmg1m_d_out ;
wire jtag_q ;
wire tmg2m1_b ;
wire ENC ;
wire tmg1m_d_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_d_a ;
wire out_buf_d_b ;
wire out_buf_d_en ;
not g1(MD1_, MD1) ;
not g2(MD2_, MD2) ;
not g3(OT_, OT) ;
not g4(ENO_, ENO) ;
UDP_MUX21 g5(tmg1m_d_out, jtag_q, OT_, MD1_) ;
not g6(ENC, ENC_) ;
not g7(tmg1m_d_out_, tmg1m_d_out) ;
and g8(bscn_xd0, ENC, tmg1m_d_out) ;
or g9(bscn_d0, ENC_, tmg1m_d_out_) ;
or g10(bscn_xd1, ENC_, tmg1m_d_out) ;
and g11(bscn_d1, ENC, tmg1m_d_out_) ;
not g12(tmg2m1_b, X) ;
UDP_MUX21 g13(IT, jtag_q, tmg2m1_b, MD2_) ;
not g14(bck, XBCK) ;
not g15(xack, ACK) ;
not g16(xclk, CK) ;
not g17(clk, xclk) ;
not g18(xupd, UP) ;
not g19(upd, xupd) ;
and g20(jtag_x1, OT_, ENO) ;
and g21(jtag_x2, ENO_, tmg2m1_b) ;
nor g22(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g23(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g24(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g25(SO, jtag_latch2_out) ;
UDP_LATCH g26(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g27(jtag_q, jtag_latch3_out) ;
not g28(out_buf_d_a, bscn_xd0) ;
not g29(out_buf_d_b, bscn_xd1) ;
xor g30(out_buf_d_en, out_buf_d_a, out_buf_d_b) ;
notif0 g31(X, out_buf_d_a, out_buf_d_en) ;
endmodule
// JTAG Bidirectional Cell
module JBD12SN(ENC_, OT, ENO, SI, CK, UP, ACK, XBCK, MD1,
MD2, SO, IT, X);
input ENC_; // tri-state enable, 0-tristate, 1-bistate
input OT; // outgoing data from core
input ENO; // jtag_ff: 1-sel_OT_data, 0-sel_PAD_data
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD1; // 0-sel_pad_data, 1-sel_jtag_ff
input MD2; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // incomming data to core
inout X;
// Verilog body for JBD12SN
wire MD1_ ;
wire MD2_ ;
wire OT_ ;
wire ENO_ ;
wire tmg1m_d_out ;
wire jtag_q ;
wire tmg2m2_b ;
wire ENC ;
wire tmg1m_d_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_d_a ;
wire out_buf_d_b ;
wire out_buf_d_en ;
not g1(MD1_, MD1) ;
not g2(MD2_, MD2) ;
not g3(OT_, OT) ;
not g4(ENO_, ENO) ;
UDP_MUX21 g5(tmg1m_d_out, jtag_q, OT_, MD1_) ;
not g6(ENC, ENC_) ;
not g7(tmg1m_d_out_, tmg1m_d_out) ;
and g8(bscn_xd0, ENC, tmg1m_d_out) ;
or g9(bscn_d0, ENC_, tmg1m_d_out_) ;
or g10(bscn_xd1, ENC_, tmg1m_d_out) ;
and g11(bscn_d1, ENC, tmg1m_d_out_) ;
not g12(tmg2m2_b, X) ;
UDP_MUX21 g13(IT, jtag_q, tmg2m2_b, MD2_) ;
not g14(bck, XBCK) ;
not g15(xack, ACK) ;
not g16(xclk, CK) ;
not g17(clk, xclk) ;
not g18(xupd, UP) ;
not g19(upd, xupd) ;
and g20(jtag_x1, OT_, ENO) ;
and g21(jtag_x2, ENO_, tmg2m2_b) ;
nor g22(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g23(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g24(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g25(SO, jtag_latch2_out) ;
UDP_LATCH g26(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g27(jtag_q, jtag_latch3_out) ;
not g28(out_buf_d_a, bscn_xd0) ;
not g29(out_buf_d_b, bscn_xd1) ;
xor g30(out_buf_d_en, out_buf_d_a, out_buf_d_b) ;
notif0 g31(X, out_buf_d_a, out_buf_d_en) ;
endmodule
// Output Buffer Cell, no scan
module JOS13NN(OT, X);
input OT;
output X;
// Verilog body for JOS13NN
wire OT_ ;
wire tmg1m1n_out ;
wire tmg1m1n_out_ ;
wire ENC ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(OT_, OT) ;
not g2(tmg1m1n_out, OT_) ;
not g3(ENC, 1'b0) ;
not g4(tmg1m1n_out_, tmg1m1n_out) ;
and g5(bscn_xd0, ENC, tmg1m1n_out) ;
or g6(bscn_d0, 1'b0, tmg1m1n_out_) ;
or g7(bscn_xd1, 1'b0, tmg1m1n_out) ;
and g8(bscn_d1, ENC, tmg1m1n_out_) ;
not g9(out_buf_a, bscn_xd0) ;
not g10(out_buf_b, bscn_xd1) ;
xor g11(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g12(X, out_buf_a, out_buf_en) ;
endmodule
// Output Buffer Cell, no scan
module JOA13NN(OT, X);
input OT;
output X;
// Verilog body for JOA13NN
wire OT_ ;
wire tmg1m1n_out ;
wire tmg1m1n_out_ ;
wire ENC ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(OT_, OT) ;
not g2(tmg1m1n_out, OT_) ;
not g3(ENC, 1'b0) ;
not g4(tmg1m1n_out_, tmg1m1n_out) ;
and g5(bscn_xd0, ENC, tmg1m1n_out) ;
or g6(bscn_d0, 1'b0, tmg1m1n_out_) ;
or g7(bscn_xd1, 1'b0, tmg1m1n_out) ;
and g8(bscn_d1, ENC, tmg1m1n_out_) ;
not g9(out_buf_a, bscn_xd0) ;
not g10(out_buf_b, bscn_xd1) ;
xor g11(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g12(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Output with Tri-state Cell
module JTS13SN(OT, SI, CK, UP, ACK, XBCK, MD, SO, X);
input OT; // core data out
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output X;
// Verilog body for JTS13SN
wire MD_ ;
wire OT_ ;
wire tmg1m1_out ;
wire tmg1m1_out_ ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD_, MD) ;
not g2(OT_, OT) ;
UDP_MUX21 g3(tmg1m1_out, jtag_q, OT_, MD_) ;
not g4(ENC, 1'b0) ;
not g5(tmg1m1_out_, tmg1m1_out) ;
and g6(bscn_xd0, ENC, tmg1m1_out) ;
or g7(bscn_d0, 1'b0, tmg1m1_out_) ;
or g8(bscn_xd1, 1'b0, tmg1m1_out) ;
and g9(bscn_d1, ENC, tmg1m1_out_) ;
not g10(tmg2m3_b, X) ;
not g12(bck, XBCK) ;
not g13(xack, ACK) ;
not g14(xclk, CK) ;
not g15(clk, xclk) ;
not g16(xupd, UP) ;
not g17(upd, xupd) ;
and g18(jtag_x1, OT_, 1'b1) ;
and g19(jtag_x2, 1'b0, tmg2m3_b) ;
nor g20(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g21(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g22(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g23(SO, jtag_latch2_out) ;
UDP_LATCH g24(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g25(jtag_q, jtag_latch3_out) ;
not g26(out_buf_a, bscn_xd0) ;
not g27(out_buf_b, bscn_xd1) ;
xor g28(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g29(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Output with tri-state Cell
module JTA13SN(OT, SI, CK, UP, ACK, XBCK, MD, SO, X);
input OT; // core data out
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output X;
// Verilog body for JTA13SN
wire MD_ ;
wire OT_ ;
wire tmg1m_d_out ;
wire tmg1m_d_out_ ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire bscn_d_xd0 ;
wire bscn_d_d0 ;
wire bscn_d_xd1 ;
wire bscn_d_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a1_a ;
wire out_buf_a1_b ;
wire out_buf_a1_en ;
not g1(MD_, MD) ;
not g2(OT_, OT) ;
UDP_MUX21 g3(tmg1m_d_out, jtag_q, OT_, MD_) ;
not g4(ENC, 1'b0) ;
not g5(tmg1m_d_out_, tmg1m_d_out) ;
and g6(bscn_d_xd0, ENC, tmg1m_d_out) ;
or g7(bscn_d_d0, 1'b0, tmg1m_d_out_) ;
or g8(bscn_d_xd1, 1'b0, tmg1m_d_out) ;
and g9(bscn_d_d1, ENC, tmg1m_d_out_) ;
not g10(tmg2m3_b, X) ;
not g12(bck, XBCK) ;
not g13(xack, ACK) ;
not g14(xclk, CK) ;
not g15(clk, xclk) ;
not g16(xupd, UP) ;
not g17(upd, xupd) ;
and g18(jtag_x1, OT_, 1'b1) ;
and g19(jtag_x2, 1'b0, tmg2m3_b) ;
nor g20(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g21(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g22(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g23(SO, jtag_latch2_out) ;
UDP_LATCH g24(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g25(jtag_q, jtag_latch3_out) ;
not g26(out_buf_a1_a, bscn_d_xd0) ;
not g27(out_buf_a1_b, bscn_d_xd1) ;
xor g28(out_buf_a1_en, out_buf_a1_a, out_buf_a1_b) ;
notif0 g29(X, out_buf_a1_a, out_buf_a1_en) ;
endmodule
// JTAG Output with tri-state Cell
module JTA23SN(OT, SI, CK, UP, ACK, XBCK, MD, SO, X);
input OT; // core data out
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output X;
// Verilog body for JTA23SN
wire MD_ ;
wire OT_ ;
wire tmg1m_d_out ;
wire tmg1m_d_out_ ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire bscn_a2_xd0 ;
wire bscn_a2_d0 ;
wire bscn_a2_xd1 ;
wire bscn_a2_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a2_a ;
wire out_buf_a2_b ;
wire out_buf_a2_en ;
not g1(MD_, MD) ;
not g2(OT_, OT) ;
UDP_MUX21 g3(tmg1m_d_out, jtag_q, OT_, MD_) ;
not g4(ENC, 1'b0) ;
not g5(tmg1m_d_out_, tmg1m_d_out) ;
and g6(bscn_a2_xd0, ENC, tmg1m_d_out) ;
or g7(bscn_a2_d0, 1'b0, tmg1m_d_out_) ;
or g8(bscn_a2_xd1, 1'b0, tmg1m_d_out) ;
and g9(bscn_a2_d1, ENC, tmg1m_d_out_) ;
not g10(tmg2m3_b, X) ;
not g12(bck, XBCK) ;
not g13(xack, ACK) ;
not g14(xclk, CK) ;
not g15(clk, xclk) ;
not g16(xupd, UP) ;
not g17(upd, xupd) ;
and g18(jtag_x1, OT_, 1'b1) ;
and g19(jtag_x2, 1'b0, tmg2m3_b) ;
nor g20(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g21(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g22(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g23(SO, jtag_latch2_out) ;
UDP_LATCH g24(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g25(jtag_q, jtag_latch3_out) ;
not g26(out_buf_a2_a, bscn_a2_xd0) ;
not g27(out_buf_a2_b, bscn_a2_xd1) ;
xor g28(out_buf_a2_en, out_buf_a2_a, out_buf_a2_b) ;
notif0 g29(X, out_buf_a2_a, out_buf_a2_en) ;
endmodule
// Output with tri-state Cell
module JTA23NN(ENC_, OT, X);
input ENC_;
input OT;
output X;
// Verilog body for JTA23NN
wire OT_ ;
wire tmg1m1_out ;
wire tmg1m1_out_ ;
wire ENC ;
wire bscn_d_xd0 ;
wire bscn_d_d0 ;
wire bscn_d_xd1 ;
wire bscn_d_d1 ;
wire out_buf_o_a ;
wire out_buf_o_b ;
wire out_buf_o_en ;
not g1(OT_, OT) ;
not g2(tmg1m1_out, OT_) ;
not g3(ENC, ENC_) ;
not g4(tmg1m1_out_, tmg1m1_out) ;
and g5(bscn_d_xd0, ENC, tmg1m1_out) ;
or g6(bscn_d_d0, ENC_, tmg1m1_out_) ;
or g7(bscn_d_xd1, ENC_, tmg1m1_out) ;
and g8(bscn_d_d1, ENC, tmg1m1_out_) ;
not g9(out_buf_o_a, bscn_d_xd0) ;
not g10(out_buf_o_b, bscn_d_xd1) ;
xor g11(out_buf_o_en, out_buf_o_a, out_buf_o_b) ;
notif0 g12(X, out_buf_o_a, out_buf_o_en) ;
endmodule
// JTAG Output with tri-state Cell
module JTD03SN(OT, SI, CK, UP, ACK, XBCK, MD, SO, X);
input OT; // core data out
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output X;
// Verilog body for JTD03SN
wire MD_ ;
wire OT_ ;
wire tmg1m1_out ;
wire tmg1m1_out_ ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a2_a ;
wire out_buf_a2_b ;
wire out_buf_a2_en ;
not g1(MD_, MD) ;
not g2(OT_, OT) ;
UDP_MUX21 g3(tmg1m1_out, jtag_q, OT_, MD_) ;
not g4(ENC, 1'b0) ;
not g5(tmg1m1_out_, tmg1m1_out) ;
and g6(bscn_xd0, ENC, tmg1m1_out) ;
or g7(bscn_d0, 1'b0, tmg1m1_out_) ;
or g8(bscn_xd1, 1'b0, tmg1m1_out) ;
and g9(bscn_d1, ENC, tmg1m1_out_) ;
not g10(tmg2m3_b, X) ;
not g12(bck, XBCK) ;
not g13(xack, ACK) ;
not g14(xclk, CK) ;
not g15(clk, xclk) ;
not g16(xupd, UP) ;
not g17(upd, xupd) ;
and g18(jtag_x1, OT_, 1'b1) ;
and g19(jtag_x2, 1'b0, tmg2m3_b) ;
nor g20(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g21(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g22(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g23(SO, jtag_latch2_out) ;
UDP_LATCH g24(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g25(jtag_q, jtag_latch3_out) ;
not g26(out_buf_a2_a, bscn_xd0) ;
not g27(out_buf_a2_b, bscn_xd1) ;
xor g28(out_buf_a2_en, out_buf_a2_a, out_buf_a2_b) ;
notif0 g29(X, out_buf_a2_a, out_buf_a2_en) ;
endmodule
// JTAG Input Buffer Cell
module JIS13SN(X, SI, CK, UP, ACK, XBCK, MD, SO, IT);
input X;
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // core data in
// Verilog body for JIS13SN
wire MD_ ;
wire tmg1m1_out ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire tmg1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD_, MD) ;
UDP_MUX21 g2(tmg1m1_out, jtag_q, 1'b1, 1'b1) ;
not g3(ENC, 1'b1) ;
not g4(tmg1m1_out_, tmg1m1_out) ;
and g5(bscn_xd0, ENC, tmg1m1_out) ;
or g6(bscn_d0, 1'b1, tmg1m1_out_) ;
or g7(bscn_xd1, 1'b1, tmg1m1_out) ;
and g8(bscn_d1, ENC, tmg1m1_out_) ;
not g9(tmg2m3_b, X) ;
UDP_MUX21 g10(IT, jtag_q, tmg2m3_b, MD_) ;
not g11(bck, XBCK) ;
not g12(xack, ACK) ;
not g13(xclk, CK) ;
not g14(clk, xclk) ;
not g15(xupd, UP) ;
not g16(upd, xupd) ;
and g17(jtag_x1, 1'b1, 1'b0) ;
and g18(jtag_x2, 1'b1, tmg2m3_b) ;
nor g19(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g20(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g21(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g22(SO, jtag_latch2_out) ;
UDP_LATCH g23(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g24(jtag_q, jtag_latch3_out) ;
not g25(out_buf_a, bscn_xd0) ;
not g26(out_buf_b, bscn_xd1) ;
xor g27(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g28(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Input Buffer Cell
module JIS11SN(X, SI, CK, UP, ACK, XBCK, MD, SO, IT);
input X;
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // core data in
// Verilog body for JIS11SN
wire MD_ ;
wire tmg1m1_out ;
wire jtag_q ;
wire tmg2m1_b ;
wire ENC ;
wire tmg1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD_, MD) ;
UDP_MUX21 g2(tmg1m1_out, jtag_q, 1'b1, 1'b1) ;
not g3(ENC, 1'b1) ;
not g4(tmg1m1_out_, tmg1m1_out) ;
and g5(bscn_xd0, ENC, tmg1m1_out) ;
or g6(bscn_d0, 1'b1, tmg1m1_out_) ;
or g7(bscn_xd1, 1'b1, tmg1m1_out) ;
and g8(bscn_d1, ENC, tmg1m1_out_) ;
not g9(tmg2m1_b, X) ;
UDP_MUX21 g10(IT, jtag_q, tmg2m1_b, MD_) ;
not g11(bck, XBCK) ;
not g12(xack, ACK) ;
not g13(xclk, CK) ;
not g14(clk, xclk) ;
not g15(xupd, UP) ;
not g16(upd, xupd) ;
and g17(jtag_x1, 1'b1, 1'b0) ;
and g18(jtag_x2, 1'b1, tmg2m1_b) ;
nor g19(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g20(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g21(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g22(SO, jtag_latch2_out) ;
UDP_LATCH g23(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g24(jtag_q, jtag_latch3_out) ;
not g25(out_buf_a, bscn_xd0) ;
not g26(out_buf_b, bscn_xd1) ;
xor g27(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g28(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Input Buffer with Pull-up Cell
module JIS11SP(X, SI, CK, UP, ACK, XBCK, MD, SO, IT);
input X;
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // core data in
// Verilog body for JIS11SP
wire MD_ ;
wire tmg1m1_out ;
wire jtag_q ;
wire tmg2m1_b ;
wire ENC ;
wire tmg1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD_, MD) ;
UDP_MUX21 g2(tmg1m1_out, jtag_q, 1'b1, 1'b1) ;
not g3(ENC, 1'b1) ;
not g4(tmg1m1_out_, tmg1m1_out) ;
and g5(bscn_xd0, ENC, tmg1m1_out) ;
or g6(bscn_d0, 1'b1, tmg1m1_out_) ;
or g7(bscn_xd1, 1'b1, tmg1m1_out) ;
and g8(bscn_d1, ENC, tmg1m1_out_) ;
not g9(tmg2m1_b, X) ;
UDP_MUX21 g10(IT, jtag_q, tmg2m1_b, MD_) ;
not g11(bck, XBCK) ;
not g12(xack, ACK) ;
not g13(xclk, CK) ;
not g14(clk, xclk) ;
not g15(xupd, UP) ;
not g16(upd, xupd) ;
and g17(jtag_x1, 1'b1, 1'b0) ;
and g18(jtag_x2, 1'b1, tmg2m1_b) ;
nor g19(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g20(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g21(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g22(SO, jtag_latch2_out) ;
UDP_LATCH g23(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g24(jtag_q, jtag_latch3_out) ;
not g25(out_buf_a, bscn_xd0) ;
not g26(out_buf_b, bscn_xd1) ;
xor g27(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g28(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Input Buffer with pull-up Cell
module JIS13SP(X, SI, CK, UP, ACK, XBCK, MD, SO, IT);
input X;
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // core data in
// Verilog body for JIS13SP
wire MD_ ;
wire tmg1m1_out ;
wire jtag_q ;
wire tmg2m3_b ;
wire ENC ;
wire tmg1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD_, MD) ;
UDP_MUX21 g2(tmg1m1_out, jtag_q, 1'b1, 1'b1) ;
not g3(ENC, 1'b1) ;
not g4(tmg1m1_out_, tmg1m1_out) ;
and g5(bscn_xd0, ENC, tmg1m1_out) ;
or g6(bscn_d0, 1'b1, tmg1m1_out_) ;
or g7(bscn_xd1, 1'b1, tmg1m1_out) ;
and g8(bscn_d1, ENC, tmg1m1_out_) ;
not g9(tmg2m3_b, X) ;
UDP_MUX21 g10(IT, jtag_q, tmg2m3_b, MD_) ;
not g11(bck, XBCK) ;
not g12(xack, ACK) ;
not g13(xclk, CK) ;
not g14(clk, xclk) ;
not g15(xupd, UP) ;
not g16(upd, xupd) ;
and g17(jtag_x1, 1'b1, 1'b0) ;
and g18(jtag_x2, 1'b1, tmg2m3_b) ;
nor g19(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g20(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g21(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g22(SO, jtag_latch2_out) ;
UDP_LATCH g23(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g24(jtag_q, jtag_latch3_out) ;
not g25(out_buf_a, bscn_xd0) ;
not g26(out_buf_b, bscn_xd1) ;
xor g27(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g28(X, out_buf_a, out_buf_en) ;
endmodule
// Input Buffer Cell
module JIS13NN(X, IT);
input X;
output IT;
// Verilog body for JIS13NN
wire ENC ;
wire tmg1m1n_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire tmg2m3n_x ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(ENC, 1'b1) ;
not g2(tmg1m1n_out_, 1'b0) ;
and g3(bscn_xd0, ENC, 1'b0) ;
or g4(bscn_d0, 1'b1, tmg1m1n_out_) ;
or g5(bscn_xd1, 1'b1, 1'b0) ;
and g6(bscn_d1, ENC, tmg1m1n_out_) ;
not g7(tmg2m3n_x, X) ;
not g8(IT, tmg2m3n_x) ;
not g9(out_buf_a, bscn_xd0) ;
not g10(out_buf_b, bscn_xd1) ;
xor g11(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g12(X, out_buf_a, out_buf_en) ;
endmodule
// Input Buffer Cell
module JIS11NP(X, IT);
input X;
output IT;
// Verilog body for JIS13NN
wire ENC ;
wire tmg1m1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire tmg2m1_x ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(ENC, 1'b1) ;
not g2(tmg1m1_out_, 1'b0) ;
and g3(bscn_xd0, ENC, 1'b0) ;
or g4(bscn_d0, 1'b1, tmg1m1_out_) ;
or g5(bscn_xd1, 1'b1, 1'b0) ;
and g6(bscn_d1, ENC, tmg1m1_out_) ;
not g7(tmg2m1_x, X) ;
not g8(IT, tmg2m1_x) ;
not g9(out_buf_a, bscn_xd0) ;
not g10(out_buf_b, bscn_xd1) ;
xor g11(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g12(X, out_buf_a, out_buf_en) ;
endmodule
// Test Cell
module JTST1(X);
output X;
// Verilog body for JTST1
endmodule
// Test Cell
module JTST2(X);
output X;
// Verilog body for JTST2
endmodule
// Power 2-Input AND Gate
module MJAND2B(A1, A2, O);
input A1;
input A2;
output O;
and g0(O, A1, A2);
endmodule
// Power 3-Input AND Gate
module MJAND3B(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
and g0(O, A1, A2, A3);
endmodule
// Power 4-Input AND Gate
module MJAND4B(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
and g0(O, A1, A2, A3, A4);
endmodule
// Power 6-Input AND Gate
module MJAND6B(A1, A2, A3, A4, A5, A6, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
output O;
and g0(O, A1, A2, A3, A4, A5, A6);
endmodule
// Power 8-Input AND Gate
module MJAND8B(A1, A2, A3, A4, A5, A6, A7, A8, O);
input A1;
input A2;
| This page: |
Created: | Thu Aug 19 12:01:16 1999 |
| From: |
../../../sparc_v8/lib/rtl/sc.v
|