V1.5 CORE Generator & IP Modules -
Tips and Techniques
General
Solution 3883 - V1.5, V1.4 COREGEN : How to permanently set the default "output format" for the CORE Generator
Solution 3040 - V1.5, V1.4 COREGEN: sample COREGen .COE coefficient files for a FIR Filter, ROM, and RAM.
Solution 3633 - V1.5, V1.4 COREGEN: How to uninstall it.
Solution 3840 - V1.5, V1.4 COREGEN: How to obtain the latest COREs and software.
Solution 3697 - V1.5, V1.4 COREGEN: COREGen does not release CPU after generating a core module.
Solution 3668 - COREGen v1.4.0 and later: How to determine the build version of the CORE Generator v1.4.x GUI.
Foundation & FPGA Express
Solution 3863 - V1.5, V1.4 COREGEN, FOUNDATION EXPRESS: How to generate Foundation functional simulation files for a Foundation Express VHDL design
Solution 2738 - FPGA EXPRESS: How to integrate CoreGen module XNF files into Express Verilog or VHDL designs
IP Modules
Solution 3846 - COREGEN: Tips on simulating the SDA FIR filter.
Solution 4675 - COREGEN: How to simulate a SINGLE Cascade mode SDA FIR filter.
Solution 4610 - COREGEN: How to calculate the pipeline/clock latency for a PDA FIR Filter.
Solution 4427 - COREGEN: How the PDA FIR module calculates its full precision output width.
Solution 3791 - COREGEN: FIFO output is only valid when RE is enabled.
