V2.1i CORE Generator & IP Modules -
Tips and Techniques
General
Solution 3883 - V2.1i, V1.5, V1.4 COREGEN : How to permanently set the default "output format" for the CORE Generator
Solution 4913 - V2.1i COREGEN: sample COREGen .COE coefficient files for a FIR Filter, Distributed ROM, Distributed RAM, Dual Port Block RAM, and Single Port Block RAM.
Solution 3840 - V2.1i, V1.5, V1.4 COREGEN: How to obtain the latest COREs and software.
Foundation & FPGA Express
Solution 3863 - V2.1i, V1.5, V1.4 COREGEN, FOUNDATION EXPRESS: How to generate Foundation functional simulation files for a Foundation Express VHDL design
Solution 5008 - FPGA Express: modules for black boxes (LogiBLOX, CoreGen) must be declared in Verilog designs; clock pins missing
IP Modules
Solution 3846 - COREGEN: Tips on simulating the SDA FIR filter.
Solution 4675 - COREGEN: How to simulate a SINGLE Cascade mode SDA FIR filter.
Solution 4610 - COREGEN: How to calculate the pipeline/clock latency for a PDA FIR Filter.
Solution 4427 - COREGEN: How the PDA FIR module calculates its full precision output width.
Solution 3791 - COREGEN: FIFO output is only valid when RE is enabled.
