/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)psr.v
***
****************************************************************************
****************************************************************************/
// @(#)psr.v 1.4 6/2/92
// psr.v
//------------------------------------------------------------------------------
/*
This file models the various pieces of the PSR,
and instantiates the pieces as part of module psr.
*/
//------------------------------------------------------------------------------
// CC
module Mcc
(ccm, cc_next3, cc_next1,
alu_cc, result_cc,
hold_cc, load_cc, write_cc, restore_cc,
ss_clock, hold
);
// OUTPUTS
output [3:0] ccm
; // condition codes {N,Z,V,C}
output cc_next3
;
output cc_next1
;
// INPUTS
input [3:0] alu_cc
; // latest cc's from the ALU
input [23:20] result_cc
; // cc field from result register
// CONTROL
input hold_cc
; // hold current CC value
input load_cc
; // load CC's from ALU
input write_cc
; // write CC's with WRPSR
input restore_cc
; // reset the CC's from previous value
// MISC
input ss_clock
;
input hold
; // primary hold
//input scan_mode;
wire [3:0] ccm;
// INPUT MUX
wire [3:0] cc_prev
; // forward declaration
wire [3:0] cc_next
;
// Expanded macro begin.
// cmux4d(cc_mux, 4, cc_next, cc_prev, restore_cc, alu_cc, load_cc, result_cc, write_cc, ccm, hold_cc)
function [4:1] cc_mux ;
input [4:1] in0_fn ;
input s0_fn ;
input [4:1] in1_fn ;
input s1_fn ;
input [4:1] in2_fn ;
input s2_fn ;
input [4:1] in3_fn ;
input s3_fn ;
reg [4:1] out_fn ;
begin
case ({ hold_cc, write_cc, load_cc, restore_cc}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
cc_mux = out_fn ;
end
endfunction
assign cc_next = cc_mux( cc_prev, restore_cc, alu_cc, load_cc, result_cc, write_cc, ccm, hold_cc) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( hold_cc+ write_cc+ load_cc+ restore_cc !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( hold_cc+ write_cc+ load_cc^ restore_cc===1'bx)) begin
$display("### %m.cc_mux: CMUX4D select error!\n");
$display(" hold_cc, write_cc, load_cc, restore_cc=%0d%0d%0d%0d\n", hold_cc, write_cc, load_cc, restore_cc);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
wire cc_next3 = cc_next[3];
wire cc_next1 = cc_next[1];
// CC REGISTER
// master latch
wire [3:0] cc_master_mux_out
= cc_next;
Mflipflop_4 cc_master_4( ccm, cc_master_mux_out, ss_clock, hold) ;
// CC SHADOW REGISTER (needed to restore CC's on TRAP of setcc instrs.)
wire [3:0] cc_shadow_mux_out
= ccm;
Mflipflop_4 cc_shadow_4( cc_prev, cc_shadow_mux_out, ss_clock, hold) ;
endmodule
//------------------------------------------------------------------------------
// CWP
module Mcwp
(cwp, cwpm_, ncwpm_, ecwpm, ecwpm_,
result_cwp, wcwpm1, cwpp1, cwpm1, wcwp,
w_wrpsr_sm, w_wrpsr_l, TRAP_sm, cwp_inc_sm,
cwp_dec_sm, cwp_hold_sm, ecwp_next_sm, cwp_recirc,
ss_clock, hold
);
// OUTPUTS
output [2:0] cwp
; // Current Window Pointer
output [2:0] cwpm_
; // Current Window Pointer master (active low)
output [2:0] ncwpm_
;
output [2:0] ecwpm
; // Previous cwp master (used for rd xlate)
output [2:0] ecwpm_
; // Previous cwp master (used for rd xlate)
// active low
//output [2:0] ecwpp1m_; // Previous cwp master + 1 (used for rd xlate)
// active low
// INPUTS
input [2:0] result_cwp
; // 3 lsb's of the result latch (for WRPSR)
input [2:0] wcwpm1
; // w - stage cwp - 1 (for WRPSR)
input [2:0] cwpp1
; // cwp + 1 (for WRPSR)
input [2:0] cwpm1
; // cwp - 1 (for WRPSR)
output [2:0] wcwp
; //
// CONTROLS
input w_wrpsr_sm
; // write PSR
input w_wrpsr_l
; // not write PSR - see hld_pilefec
input TRAP_sm
; // restore CWP on a trap
input cwp_inc_sm
; // increment cwp
input cwp_dec_sm
; // decrement cwp
input cwp_hold_sm
; // hold cwp
input ecwp_next_sm
; // normal cwp pipe advance
input cwp_recirc
;
// MISC
input ss_clock
;
input hold
;
// input scan_mode;
// FORWARD DECLARATIONS
wire [2:0] cwp; // cwp // used to be reg
wire [2:0] cwpp1; // cwp plus 1
wire [2:0] cwpm1; // cwp minus 1
wire [2:0] wcwpm1; // wcwp minus 1
wire [2:0] cwp_shadow
;
// INPUT MUX
wire [2:0] ncwp_lev1
; // mux output
// Expanded macro begin.
// cmux5d(cwp_mux, 3, ncwp_lev1, wcwpm1, TRAP_sm, result_cwp, w_wrpsr_sm, cwpp1, cwp_inc_sm, cwpm1, cwp_dec_sm, cwp, cwp_hold_sm)
function [3:1] cwp_mux ;
input [3:1] in0_fn ;
input s0_fn ;
input [3:1] in1_fn ;
input s1_fn ;
input [3:1] in2_fn ;
input s2_fn ;
input [3:1] in3_fn ;
input s3_fn ;
input [3:1] in4_fn ;
input s4_fn ;
reg [3:1] out_fn ;
begin
case ({ cwp_hold_sm, cwp_dec_sm, cwp_inc_sm, w_wrpsr_sm, TRAP_sm}) /* synopsys parallel_case */
5'b00001: out_fn = in0_fn ;
5'b00010: out_fn = in1_fn ;
5'b00100: out_fn = in2_fn ;
5'b01000: out_fn = in3_fn ;
5'b10000: out_fn = in4_fn ;
default: out_fn = 65'hx;
endcase
cwp_mux = out_fn ;
end
endfunction
assign ncwp_lev1 = cwp_mux( wcwpm1, TRAP_sm, result_cwp, w_wrpsr_sm, cwpp1, cwp_inc_sm, cwpm1, cwp_dec_sm, cwp, cwp_hold_sm) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( cwp_hold_sm+ cwp_dec_sm+ cwp_inc_sm+ w_wrpsr_sm+ TRAP_sm !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( cwp_hold_sm+ cwp_dec_sm+ cwp_inc_sm+ w_wrpsr_sm^ TRAP_sm===1'bx)) begin
$display("### %m.cwp_mux: CMUX5D select error!\n");
$display(" cwp_hold_sm, cwp_dec_sm, cwp_inc_sm, w_wrpsr_sm, TRAP_sm=%0d%0d%0d%0d%0d\n", cwp_hold_sm, cwp_dec_sm, cwp_inc_sm, w_wrpsr_sm, TRAP_sm);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// this mux added
wire [2:0] ncwp
;
// Expanded macro begin.
// cmux2(cwp_lev2_mux, 3, ncwp, ncwp_lev1, cwp_shadow, cwp_recirc)
function [3:1] cwp_lev2_mux ;
input [3:1] in0_fn ;
input [3:1] in1_fn ;
input select_fn ;
reg [3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
cwp_lev2_mux = out_fn ;
end
endfunction
assign ncwp = cwp_lev2_mux(ncwp_lev1, cwp_shadow, cwp_recirc) ;
// Expanded macro end.
// CWP MASTeR
wire [2:0] cwpm_;
wire [2:0] ncwpm_ = ~ncwp;
Mflipflop_3 cwp_master_3( cwpm_, ncwpm_, ss_clock, hold) ;
// CWP shadow register - recirculate in case you have an annuled
// SAVE/RESTORE in delay slot of a folded branch -
wire [2:0] ncwp_shadow
= ~cwpm_;
Mflipflop_3 cwp_shadow_reg_3(cwp_shadow,ncwp_shadow,ss_clock,hold) ;
// Note: In the next few lines, some of the IF constructs contain
// references to invalid cwp values. These were added because the
// values are possible during scan mode, although they will not show
// up during normal operation of the IU.
// wire [2:0] cwpp1m_ = (cwpm_==1 || cwpm_==0) ? 7 : cwpm_ - 1;
// CWP SLAVe
assign cwp = ~cwpm_;
// assign cwpp1 = (cwp==6 || cwp==7) ? 0 : cwp + 1;
// assign cwpm1 = cwp == 0 ? 6 : cwp - 1;
// E_CWP MUX
wire [2:0] necwp
;
// Expanded macro begin.
// cmux3d(ecwp_mux, 3, necwp, cwp, ecwp_next_sm, result_cwp, w_wrpsr_sm, wcwpm1, TRAP_sm)
function [3:1] ecwp_mux ;
input [3:1] in0_fn ;
input s0_fn ;
input [3:1] in1_fn ;
input s1_fn ;
input [3:1] in2_fn ;
input s2_fn ;
reg [3:1] out_fn ;
begin
case ({ TRAP_sm, w_wrpsr_sm, ecwp_next_sm}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
ecwp_mux = out_fn ;
end
endfunction
assign necwp = ecwp_mux( cwp, ecwp_next_sm, result_cwp, w_wrpsr_sm, wcwpm1, TRAP_sm) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( TRAP_sm+ w_wrpsr_sm+ ecwp_next_sm !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( TRAP_sm+ w_wrpsr_sm^ ecwp_next_sm===1'bx)) begin
$display("### %m.ecwp_mux: CMUX3D select error!\n");
$display(" TRAP_sm, w_wrpsr_sm, ecwp_next_sm=%0d%0d%0d\n", TRAP_sm, w_wrpsr_sm, ecwp_next_sm);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// E_CWP MASTeR
wire [2:0] ecwpm_;
wire [2:0] ecwp_master_mux_out
= ~necwp;
Mflipflop_3 ecwp_master_3( ecwpm_, ecwp_master_mux_out, ss_clock, hold) ;
wire [2:0] ecwpm = ~ecwpm_;
// wire [2:0] ecwpp1m_ = ecwpm_ == 1 ? 7 : ecwpm_ - 1;
// E_CWP SLAVe
wire [2:0] ecwp
; // used to be reg
assign ecwp = ~ecwpm_;
// W_CWP MUX
wire [2:0] nwcwp
;
// Expanded macro begin.
// cmux2d(wcwp_mux, 3, nwcwp, ecwp, w_wrpsr_l, result_cwp, w_wrpsr_sm)
function [3:1] wcwp_mux ;
input [3:1] in0_fn ;
input s0_fn ;
input [3:1] in1_fn ;
input s1_fn ;
reg [3:1] out_fn ;
begin
case ({ w_wrpsr_sm, w_wrpsr_l}) /* synopsys parallel_case */
2'b01: out_fn = in0_fn;
2'b10: out_fn = in1_fn;
default: out_fn = 65'hx;
endcase
wcwp_mux = out_fn ;
end
endfunction
assign nwcwp = wcwp_mux( ecwp, w_wrpsr_l, result_cwp, w_wrpsr_sm) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( w_wrpsr_sm+ w_wrpsr_l !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( w_wrpsr_sm^ w_wrpsr_l===1'bx)) begin
$display("### %m.wcwp_mux: CMUX2D select error!\n");
$display(" w_wrpsr_sm, w_wrpsr_l=%0d%0d\n", w_wrpsr_sm, w_wrpsr_l);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// W_CWP REGISTER
wire [2:0] wcwp;
wire [2:0] wcwp_reg_mux_out
= nwcwp;
Mflipflop_3 wcwp_reg_3( wcwp, wcwp_reg_mux_out, ss_clock, hold) ;
// assign wcwpm1 = wcwp == 0 ? 6 : wcwp - 1;
endmodule
//------------------------------------------------------------------------------
// ET
module Met
(et, etm,
result_et,
clret_sets_sm, setet_ps2s_sm, write_etps_sm, hold_ets_sm,
ss_clock, hold
);
// OUTPUTS
output et
; // Enable Traps bit of PSR
output etm
; // master version
// INPUTS
input result_et
; // for writing the ET bit with WRPSR
// CONTROL
input clret_sets_sm
; // clear the ET bit
input setet_ps2s_sm
; // set the ET bit
input write_etps_sm
; // write ET (wrpsr)
input hold_ets_sm
; // keep ET bit
// MISC
input ss_clock
;
input hold
;
//input scan_mode;
// INPUT MUX
wire net
; // next et
wire et; // used to be reg
wire zero
= 1'b0; // simplify mux argument
wire one
= 1'b1; // simplify mux argument
// Expanded macro begin.
// cmux4d(et_mux, 1, net, zero, clret_sets_sm, one, setet_ps2s_sm, result_et, write_etps_sm, et, hold_ets_sm)
function [1:1] et_mux ;
input [1:1] in0_fn ;
input s0_fn ;
input [1:1] in1_fn ;
input s1_fn ;
input [1:1] in2_fn ;
input s2_fn ;
input [1:1] in3_fn ;
input s3_fn ;
reg [1:1] out_fn ;
begin
case ({ hold_ets_sm, write_etps_sm, setet_ps2s_sm, clret_sets_sm}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
et_mux = out_fn ;
end
endfunction
assign net = et_mux( zero, clret_sets_sm, one, setet_ps2s_sm, result_et, write_etps_sm, et, hold_ets_sm) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( hold_ets_sm+ write_etps_sm+ setet_ps2s_sm+ clret_sets_sm !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( hold_ets_sm+ write_etps_sm+ setet_ps2s_sm^ clret_sets_sm===1'bx)) begin
$display("### %m.et_mux: CMUX4D select error!\n");
$display(" hold_ets_sm, write_etps_sm, setet_ps2s_sm, clret_sets_sm=%0d%0d%0d%0d\n", hold_ets_sm, write_etps_sm, setet_ps2s_sm, clret_sets_sm);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// MASTeR LATCH
wire etm;
Mflipflop_1 et_master_1( etm, net, ss_clock, hold) ;
// SLAVe
assign et = etm;
endmodule
//------------------------------------------------------------------------------
// PS
module Mps
(ps, psm,
result_ps, s,
s_into_ps_sm, hold_ps_sm, write_etps_sm,
ss_clock, hold
);
// OUTPUTS
output ps
; // Previous State bit in PSR
output psm
; // master version
// INPUTS
input result_ps
; // for writing PS with WRPSR
input s
; // supervisor bit (ps <- s on traps)
// CONTROL
input s_into_ps_sm
; // load S into PS (TRAP)
input hold_ps_sm
; // hold PS
input write_etps_sm
; // write PS
//input reset_sm;
// MISC
input ss_clock
;
input hold
;
//input scan_mode;
// INPUT MUX
wire ps; // used to be reg
wire nps
; // next PS
// wire one = 1'b1; // simplify mux argument
// Expanded macro begin.
// cmux3d(ps_mux, 1, nps, s, s_into_ps_sm, result_ps, write_etps_sm, ps, hold_ps_sm)
function [1:1] ps_mux ;
input [1:1] in0_fn ;
input s0_fn ;
input [1:1] in1_fn ;
input s1_fn ;
input [1:1] in2_fn ;
input s2_fn ;
reg [1:1] out_fn ;
begin
case ({ hold_ps_sm, write_etps_sm, s_into_ps_sm}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
ps_mux = out_fn ;
end
endfunction
assign nps = ps_mux( s, s_into_ps_sm, result_ps, write_etps_sm, ps, hold_ps_sm) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( hold_ps_sm+ write_etps_sm+ s_into_ps_sm !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( hold_ps_sm+ write_etps_sm^ s_into_ps_sm===1'bx)) begin
$display("### %m.ps_mux: CMUX3D select error!\n");
$display(" hold_ps_sm, write_etps_sm, s_into_ps_sm=%0d%0d%0d\n", hold_ps_sm, write_etps_sm, s_into_ps_sm);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// one, reset_sm
// MASTeR LATCH
wire psm;
Mflipflop_1 ps_master_1( psm, nps, ss_clock, hold) ;
// SLAVe LATCH
assign ps = psm;
endmodule
//------------------------------------------------------------------------------
// S
module Ms
(s, sm,
result_s, ps,
clret_sets_sm, write_etps_sm, setet_ps2s_sm, hold_ets_sm,
ss_clock, hold
);
// OUTPUTS
output s
; // Supervisor bit in PSR
output sm
; // master version
// INPUTS
input result_s
; // for writing S with WRPSR
input ps
; // supervisor bit (s <- ps on rett)
// CONTROL
input clret_sets_sm
; // set the S bit
input write_etps_sm
; // write the S bit
input setet_ps2s_sm
; // copy PS into S
input hold_ets_sm
; // hold S
// MISC
input ss_clock
;
input hold
;
//input scan_mode;
// INPUT MUX
wire s; // used to be reg
wire ns
; // next S
wire one
= 1'b1; // simplify mux argument
// Expanded macro begin.
// cmux4d(s_mux, 1, ns, one, clret_sets_sm, result_s, write_etps_sm, ps, setet_ps2s_sm, s, hold_ets_sm)
function [1:1] s_mux ;
input [1:1] in0_fn ;
input s0_fn ;
input [1:1] in1_fn ;
input s1_fn ;
input [1:1] in2_fn ;
input s2_fn ;
input [1:1] in3_fn ;
input s3_fn ;
reg [1:1] out_fn ;
begin
case ({ hold_ets_sm, setet_ps2s_sm, write_etps_sm, clret_sets_sm}) /* synopsys parallel_case */
4'b0001: out_fn = in0_fn;
4'b0010: out_fn = in1_fn;
4'b0100: out_fn = in2_fn;
4'b1000: out_fn = in3_fn;
default: out_fn = 65'hx;
endcase
s_mux = out_fn ;
end
endfunction
assign ns = s_mux( one, clret_sets_sm, result_s, write_etps_sm, ps, setet_ps2s_sm, s, hold_ets_sm) ;
// synopsys translate_off
always @ (posedge(~Mclocks.clock))
#1 if (( hold_ets_sm+ setet_ps2s_sm+ write_etps_sm+ clret_sets_sm !== 1) & `SS_SCOPE.input_reset_l &
~Mtask.trace.ppr & ~( hold_ets_sm+ setet_ps2s_sm+ write_etps_sm^ clret_sets_sm===1'bx)) begin
$display("### %m.s_mux: CMUX4D select error!\n");
$display(" hold_ets_sm, setet_ps2s_sm, write_etps_sm, clret_sets_sm=%0d%0d%0d%0d\n", hold_ets_sm, setet_ps2s_sm, write_etps_sm, clret_sets_sm);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// synopsys translate_on
// Expanded macro end.
// MASTeR LATCH
wire sm;
Mflipflop_1 s_master_1( sm, ns, ss_clock, hold) ;
// SLAVe LATCH
assign s = sm;
endmodule
//------------------------------------------------------------------------------
// PSR
/*
This module instantiates the previous pieces of the PSR
and creates master latches for the remaining fields.
*/
module Mpsr
(psrm, cwp, cwpm_, ncwpm_, ecwpm_, wcwpm1, cwpp1, cwpm1, wcwp, ccm,
cc_next3, cc_next1,
sm, little_endian, s, psm, ps, et, ef, pil,
result,
alu_cc, hold_cc, load_cc, write_cc, restore_cc,
clret_sets_sm, setet_ps2s_sm, write_etps_sm, hold_ets_sm,
s_into_ps_sm, hold_ps_sm,
hld_pilefec,
w_wrpsr_sm, TRAP_sm,
cwp_inc_sm, cwp_dec_sm, cwp_hold_sm, ecwp_next_sm,
cwp_recirc,
ss_clock, hold
);
// OUTPUTS
output [31:0] psrm
; // master latched PSR - for RDPSR
output [2:0] cwp
; // Current Window Pointer
output [2:0] cwpm_
; // Current Window Pointer master (active low)
output [2:0] ncwpm_
;
output [2:0] ecwpm_
; // Previous cwp master (used for rd xlate) (active low)
// output [2:0] ecwpp1m_; // Prev. cwp master + 1 (used for rd xlate) (act. low)
input [2:0] wcwpm1
; // w cwp master -1
input [2:0] cwpp1
; // cwp master + 1
input [2:0] cwpm1
; // cwp master - 1
output [2:0] wcwp
; //
output [3:0] ccm
; // Condition Codes Master latched
output cc_next3
;
output cc_next1
;
output sm
; // supervisor bit master version
output little_endian
; // little endian control
output s
; // supervisor bit
output psm
; // previous supervisor bit master version
output ps
; // previous supervisor bit
output et
; // trap enable bit
output ef
; // enable FPU
//output ec; // enable co-processor
output [3:0] pil
; // Processor Interrupt Level
//output iu_sup_inst_f; // supervisor state for fetch?
// INPUTS
//input use_ps; // use pS bit for i-fetches
input [31:0] result
; // result latch from ALU
input [3:0] alu_cc
; // condition code results from ALU
// CONTROL
input hold_cc
; // hold CC's
input load_cc
; // load CC's from ALU
input write_cc
; // write CC's from result (wrpsr)
input restore_cc
; // restore CC's due to trap on setcc instr.
input clret_sets_sm
; // clear ET and set S
input setet_ps2s_sm
; // set ET
input write_etps_sm
; // load ET (wrpsr)
input hold_ets_sm
; // hold ET
input s_into_ps_sm
; // PS controls
input hold_ps_sm
;
input hld_pilefec
; // hold control for PIL, EF, and EC
input w_wrpsr_sm
; // W cycle of WRPSR
// input w_wrpsr_l; // W cycle of not WRPSR
input TRAP_sm
; // TRAP detected
//input reset_sm; // IU reset
input cwp_inc_sm
; // increment cwp
input cwp_dec_sm
; // decrement cwp
input cwp_hold_sm
; // hold cwp
input ecwp_next_sm
; // normal cwp pipe advance
input cwp_recirc
;
// MISC
input ss_clock
;
input hold
;
//input scan_mode;
// CWP
wire [2:0] cwp; // Current Window Pointer
// active low CWP's are used for RF Xlate
wire [2:0] cwpm_; // Current Window Pointer master
wire [2:0] ncwpm_;
wire [2:0] ecwpm_; // Previous cwp master (used for rd xlate)
// wire [2:0] ecwpp1m; // Previous cwp master + 1 (used for rd xlate)
wire [2:0] ecwpm
; // Previous cwp master (used for RDPSR)
Mcwp cwp_mod (cwp, cwpm_, ncwpm_, ecwpm, ecwpm_,
result[2:0], wcwpm1, cwpp1, cwpm1, wcwp,
w_wrpsr_sm, hld_pilefec, // was w_wrpsr_l
TRAP_sm, cwp_inc_sm, cwp_dec_sm, cwp_hold_sm, ecwp_next_sm,
cwp_recirc,
ss_clock, hold
);
// ET
wire et; // Enable Traps
wire etm
;
Met et_mod (et, etm,
result[5],
clret_sets_sm, setet_ps2s_sm, write_etps_sm, hold_ets_sm,
ss_clock, hold
);
// PS
wire ps; // Previous State
wire psm;
wire s; // Supervisor
Mps ps_mod (ps, psm,
result[6], s,
s_into_ps_sm, hold_ps_sm, write_etps_sm,
ss_clock, hold
);
// S
wire sm;
Ms s_mod (s, sm,
result[7], ps,
clret_sets_sm, write_etps_sm, setet_ps2s_sm, hold_ets_sm,
ss_clock, hold
);
// evaluate supervisor fetch status
// wire iu_sup_inst_f = use_ps ? ps : s;
// PIL
wire [3:0] pilm
;
wire [3:0] pil_master_mux_out
= result[11:8];
Mflipflop_4 pil_master_4( pilm, pil_master_mux_out, ss_clock, (hold | hld_pilefec)) ;
wire [3:0] pil; // used to be reg
assign pil = pilm;
// EF
wire efm
;
wire ef; // used to be reg
Mflipflop_1 ef_master_1( efm, result[12], ss_clock, (hold | hld_pilefec)) ;
assign ef = efm;
// EC
wire ecm
;
wire ec
; // used to be reg
Mflipflop_1 ec_master_1( ecm, result[13], ss_clock, (hold | hld_pilefec)) ;
assign ec = ecm;
// DE
wire dem
;
wire de
; // used to be reg
Mflipflop_1 de_master_1( dem, result[15], ss_clock, (hold | hld_pilefec)) ;
assign de = dem;
// DE_SUP
wire de_supm
;
wire de_sup
; // used to be reg
Mflipflop_1 de_sup_master_1( de_supm, result[16], ss_clock, (hold | hld_pilefec)) ;
assign de_sup = de_supm;
// little endian control
assign little_endian = sm & de_sup | ~sm & de;
// CC's
wire [3:0] ccm;
wire cc_next3;
wire cc_next1;
Mcc cc_mod (ccm, cc_next3, cc_next1,
alu_cc, result[23:20],
hold_cc, load_cc, write_cc, restore_cc,
ss_clock, hold
);
// PSR
// NOTE:
// This value is used ONLY by the RDPSR instruction
// ecwpm is used instead of cwpm because save and restore
// instructions change the cwpm in their decode cycle,
// thus affecting the PRECEDING RDPSR which reads the psr
// in it's E cycle.
// WRPSR and TRAP both update cwp and ecwp immediately,
wire [31:0] psrm = {
4'h0, // IMPLEMENTATION
4'h4, // VERSION
ccm, // Condition Codes
3'b0,
de_sup, // default endian supervisor
de, // default endian user
1'b0, // RESERVED
ecm, // Enable Co-processor
efm, // Enable FPU
pilm, // Processor Interrupt Level
sm, // Supervisor bit
psm, // Previous state bit
etm, // Enable traps bit
2'b0, // Unused bits of the CWP
ecwpm // Current Window Pointer
};
endmodule
This page: |
Created: | Thu Aug 19 12:02:29 1999 |
| From: |
../../../sparc_v8/ssparc/iu/Mexec/rtl/psr.v
|