/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
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/******************************************************************************/
// @(#)fp_ctl.v 1.1 4/7/92
//
// FPU core control top-level interconnect module.
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand to remove hierarchy from signal names and make
// things more readable.
module fp_ctl
( ss_clock, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
Conditionals_3, Conditionals_10, Conditionals_12,
FpLd, FpOp, FracAgtB, FracBregSign, FracZero,
notAInfNAN, notAM31_3, notAM2_0, notAregMasterFPMSBP1, notAZeroDenorm,
notBInfNAN, notBZeroDenorm, notExpUnderflow, notExpOverflow,
notExpException, notPossibleOv, notFracZero, notSticky1, ResetIn,
RS2_63, RS1_63, StickyForSR1, SubResultNorm, AregMaster_57_40,
AregMaster_7_0, CarryInLSBs, CregInSL2SQRT, CregSNBits, ExpIn,
FpInst, notExpShiftResult, notMultip, notSticky4, RoundingMode,
SALSBs, SBLSBs, SCLSBs, StepRemBits, Sticky2, StickyExtra, SumInLSBs,
TregLSBs, U_RomOutputs,
CarryIn, CarryOut0, CarryOut3, Constantb, Constantc, Constantd,
Constante, Constantf, Constantg, Constanth, ExpAregLC0, ExpAregLC1,
ExpAregLoadEn, ExpBregLC0, ExpBregLC1, ExpBregLoadEn, FracAregLoadEn,
FracBregLoadEn, FracCregLC, FracCregLoadEn, FracTregLoadEn, FpBusy,
InitialCarryBit, InitialMulStep, notFracYFromD1A, notFracYFromD2A,
notFracYFromD3A, notNO_1, notStickyInForSR, OprSNnotDB, RomOutputs_18,
RomOutputs_20, RomOutputs_27, RomOutputs_55, SignResult, SNnotDB,
SROneMore, SRToSticky, SumCarryLoadEn, SumOut0, ConditionCodes, Excep,
FracAregLC, FracBregLC, FracRound, FracYbusLSBs, InForCreg,
InForCregDB, InFromCregOr0, LIB, MulLenSel, notsh, Pos,
RomOutputs_32_29, RomOutputs_46_44, SelectedMIptr, Shift, SRControl,
TopBitsIn, Zero,
ss_scan_mode, fp_ctl_scan_in, fp_ctl_scan_out);
input ss_clock
, AregMaster_32
, BregFPMSBM1
, CALSB
, CBLSB
, CCLSB
,
Conditionals_3
, Conditionals_10
, Conditionals_12
,
FpLd
, FpOp
, FracAgtB
, FracBregSign
, FracZero
,
notAInfNAN
, notAM31_3
, notAM2_0
, notAregMasterFPMSBP1
, notAZeroDenorm
,
notBInfNAN
, notBZeroDenorm
, notExpUnderflow
, notExpOverflow
,
notExpException
, notPossibleOv
, notFracZero
, notSticky1
, ResetIn
,
RS2_63
, RS1_63
, StickyForSR1
, SubResultNorm
,
ss_scan_mode
, fp_ctl_scan_in
;
input [57:40] AregMaster_57_40
;
input [7:0] AregMaster_7_0
;
input [2:0] CarryInLSBs
;
input [1:0] CregInSL2SQRT
;
input [1:0] CregSNBits
;
input [7:0] ExpIn
;
input [9:0] FpInst
;
input [12:0] notExpShiftResult
;
input [8:0] notMultip
;
input [3:0] notSticky4
;
input [1:0] RoundingMode
;
input [1:0] SALSBs
;
input [1:0] SBLSBs
;
input [1:0] SCLSBs
;
input [3:0] StepRemBits
;
input [1:0] Sticky2
;
input [1:0] StickyExtra
;
input [2:0] SumInLSBs
;
input [1:0] TregLSBs
;
input [63:0] U_RomOutputs
; // unbuffered ROM data output
output CarryIn
, CarryOut0
, CarryOut3
, Constantb
, Constantc
, Constantd
,
Constante
, Constantf
, Constantg
, Constanth
, ExpAregLC0
, ExpAregLC1
,
ExpAregLoadEn
, ExpBregLC0
, ExpBregLC1
, ExpBregLoadEn
, FracAregLoadEn
,
FracBregLoadEn
, FracCregLC
, FracCregLoadEn
, FracTregLoadEn
, FpBusy
,
InitialCarryBit
, InitialMulStep
, notFracYFromD1A
, notFracYFromD2A
,
notFracYFromD3A
, notNO_1
, notStickyInForSR
, OprSNnotDB
, RomOutputs_18
,
RomOutputs_20
, RomOutputs_27
, RomOutputs_55
, SignResult
, SNnotDB
,
SROneMore
, SRToSticky
, SumCarryLoadEn
, SumOut0
,
fp_ctl_scan_out
;
output [1:0] ConditionCodes
;
output [5:0] Excep
;
output [2:0] FracAregLC
;
output [2:0] FracBregLC
;
output [4:0] FracRound
;
output [1:0] FracYbusLSBs
;
output [1:0] InForCreg
;
output [1:0] InForCregDB
;
output [1:0] InFromCregOr0
;
output [2:0] LIB
;
output [4:0] MulLenSel
;
output [3:1] notsh
;
output [3:0] Pos
;
output [32:29] RomOutputs_32_29
;
output [46:44] RomOutputs_46_44
;
output [7:0] SelectedMIptr
; // unregistered ROM address
output [3:0] Shift
;
output [3:0] SRControl
;
output [8:0] TopBitsIn
;
output [3:0] Zero
;
wire notWaitForShifter
, SignAreg
, PreventSwap
, PreventSwapExp
, XDest
,
CMPDecoded
, CMPEDecoded
, notAbortWB
, NegateOprSign
, Unimplemented
,
Status_6
, notSignAFromB
, notSignBFromA
, DBnotSN
,
Conditionals_2
, Conditionals_6
, Conditionals_7
, Conditionals_15
;
wire [6:0] YDest
;
wire [1:0] notNO
;
wire [63:0] RomOutputs
;
assign notNO_1 = notNO[1] ;
assign RomOutputs_18 = RomOutputs[18] ;
assign RomOutputs_20 = RomOutputs[20] ;
assign RomOutputs_27 = RomOutputs[27] ;
assign RomOutputs_55 = RomOutputs[55] ;
assign RomOutputs_32_29 = RomOutputs[32:29] ;
assign RomOutputs_46_44 = RomOutputs[46:44] ;
ME_TIEOFF toff (vdd
, gnd
);
Control cl ( .Phi (ss_clock ), .ResetIn (ResetIn ),
.notExpAgtB (notExpShiftResult[12] ),
.notAInfNan (notAInfNAN ), .notAZeroDenorm (notAZeroDenorm ),
.notBInfNan (notBInfNAN ), .notBZeroDenorm (notBZeroDenorm ),
.notExpUnderflow (notExpUnderflow ), .notExpOverflow (notExpOverflow ),
.notExpException (notExpException ),
.notWaitForShifter (notWaitForShifter ), .notNO (notNO ),
.SubResultNorm (SubResultNorm ), .notPossibleOv (notPossibleOv ),
.Conditionals_14_8 ({vdd, AregMaster_57_40[54], Conditionals_12,
FracAgtB, Conditionals_10, FracZero, notFracZero }),
.Conditionals_6_0 ( {Conditionals_6, SignAreg, ExpIn[0],
Conditionals_3, Conditionals_2 , SNnotDB, gnd} ),
.FpInst (FpInst ), .FpOp (FpOp ), .FpLd (FpLd ),
.PreventSwap (PreventSwap ), .PreventSwapExp (PreventSwapExp ),
.RCondition (Conditionals_15 ),
.SelectedMIptr (SelectedMIptr ),
.U_RomOutputs (U_RomOutputs ),
.RomOutputs (RomOutputs[63:0] ),
.YDest (YDest[6:0] ), .XDest (XDest ), .CMPDecoded (CMPDecoded ),
.CMPEDecoded (CMPEDecoded ), .AregOprExc (Conditionals_7 ),
.notAbortWB (notAbortWB ),
.Reset (Reset
), .Busy (FpBusy ), .NegateOprSign (NegateOprSign ),
.UnimpOut (Unimplemented ) );
frac_ctl fracctl ( .Phi(ss_clock), .AregMaster_32 (AregMaster_32 ),
.BregFPMSBM1 (BregFPMSBM1 ), .CALSB (CALSB), .CBLSB (CBLSB ),
.CCLSB (CCLSB ), .FracBregSign (FracBregSign ), .FracSign (FracAgtB ),
.LoadForInt (RomOutputs[19] ), .LoadOprs (FpLd ),
.notAbortWB (notAbortWB ), .notAM31_3 (notAM31_3 ),
.notAM2_0 (notAM2_0), .notAregMasterFPMSBP1 (notAregMasterFPMSBP1 ),
.notSticky1 (notSticky1), .PreventSwap (PreventSwap ),
.Rom_Inexact (Status_6 ), .RomShForAlign (RomOutputs[21] ),
.SNnotDB(SNnotDB), .SROneMore (SROneMore), .SRToSticky (SRToSticky ),
.StickyForSR1 (StickyForSR1),
.AregMaster_57_40 ( AregMaster_57_40[57:40] ),
.AregMaster_7_0 (AregMaster_7_0[7:0] ),
.CarryInLSBs (CarryInLSBs ), .CregInSL2SQRT ( CregInSL2SQRT ),
.CregSNBits (CregSNBits ), .ExpIn ({SignAreg, ExpIn}),
.notMultip (notMultip ), .notSticky4 (notSticky4 ),
.Rom_63_48 (RomOutputs[63:48] ), .SALSBs (SALSBs ), .SBLSBs (SBLSBs ),
.SCLSBs (SCLSBs ), .SRControl (SRControl ), .StepRemBits (StepRemBits),
.Sticky2 (Sticky2 ), .StickyExtra (StickyExtra ),
.SumInLSBs (SumInLSBs ), .TregLSBs (TregLSBs ), .YDest (YDest[6:0] ),
.CarryOut0 (CarryOut0 ), .CarryOut3 (CarryOut3 ),
.FracAregLoadEn (FracAregLoadEn ), .FracBregLoadEn (FracBregLoadEn ),
.FracCregLoadEn (FracCregLoadEn ), .FracCregLC (FracCregLC ),
.FracTregLoadEn (FracTregLoadEn ), .Inexact (Excep[0] ),
.InitialCarryBit (InitialCarryBit ), .InitialMulStep (InitialMulStep ),
.notFracYFromD1A (notFracYFromD1A ),
.notFracYFromD2A (notFracYFromD2A ),
.notFracYFromD3A (notFracYFromD3A ),
.notStickyInForSR (notStickyInForSR ),
.SumCarryLoadEn (SumCarryLoadEn ), .SumOut0 (SumOut0 ),
.FracAregLC (FracAregLC ), .FracBregLC (FracBregLC ),
.FracYbusLSBs (FracYbusLSBs ), .InForCreg (InForCreg ),
.InForCregDB (InForCregDB ), .InFromCregOr0 (InFromCregOr0 ),
.LIB ( LIB ), .notNO (notNO ), .notsh (notsh ), .Pos (Pos ),
.Shift (Shift ), .TopBitsIn (TopBitsIn ), .Zero (Zero ) );
SignDp sdp ( .Phi (ss_clock ), .Reset (Reset ),
.RomSignLength ( RomOutputs[43:39] ),
.RomStatus ( RomOutputs[26:22] ), .FracXFromRound (RomOutputs[47] ),
.XDest (XDest ), .CMPDecoded (CMPDecoded ),
.CMPEDecoded (CMPEDecoded ), .SignOpA (RS2_63 ), .SignOpB (RS1_63 ),
.notAbortWB (notAbortWB ), .PreventSwap (PreventSwap ), .FpLd (FpLd ),
.FpOp (FpOp ), .NegateOprSign (NegateOprSign ),
.notSignAFromB (notSignAFromB ), .notSignBFromA (notSignBFromA ),
.OprRoundMode (RoundingMode ), .FpInst1 ( FpInst[1] ),
.Unimplemented (Unimplemented ), .SignResult (SignResult ),
.AregSign (SignAreg ), .AregXORBreg (Conditionals_2 ),
.FpExc_Unimp (Excep[5] ), .Status_6_2 ({Status_6 , Excep[4:1] }),
.ConditionCodes (ConditionCodes ), .OprSNnotDB (OprSNnotDB ),
.SNnotDB (SNnotDB ), .DBnotSN (DBnotSN ), .MulLenSel (MulLenSel ),
.RModeMinus (Conditionals_6 ), .FracRoundOut (FracRound ) );
exp_ctl expctl ( .Phi (ss_clock), .DBnotSN (DBnotSN),
.FracAregMSB1 (AregMaster_57_40[56] ), .LoadOprs (FpLd),
.notAbortWB (notAbortWB ), .PreventSwap (PreventSwapExp ),
.ShiftBy8 (RomOutputs[20] ), .ShiftForAl (RomOutputs[21] ),
.SNnotDB (SNnotDB ), .notExpShiftResult (notExpShiftResult ),
.Rom_28_27 (RomOutputs[28:27] ), .Rom_38_33 (RomOutputs[38:33] ),
.CarryIn (CarryIn ), .Constantb (Constantb ), .Constantc (Constantc ),
.Constantd (Constantd ), .Constante (Constante ),
.Constantf (Constantf ), .Constantg (Constantg ),
.Constanth (Constanth ), .ExpAregLoadEn (ExpAregLoadEn ),
.ExpAregLC0 (ExpAregLC0 ), .ExpAregLC1 (ExpAregLC1 ),
.ExpBregLC0 (ExpBregLC0 ), .ExpBregLC1 (ExpBregLC1 ),
.ExpBregLoadEn (ExpBregLoadEn ), .notSignAFromB (notSignAFromB ),
.notSignBFromA (notSignBFromA ),
.notWaitForShifter (notWaitForShifter ), .SROneMore (SROneMore ),
.SRToSticky (SRToSticky ), .SRControl (SRControl) );
endmodule
This page: |
Created: | Thu Aug 19 12:02:39 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/fp_ctl.v
|