5'b11010: decode4to16w1e = 15'h0200;
  5'b11011: decode4to16w1e = 15'h0400;
  5'b11100: decode4to16w1e = 15'h0800;
  5'b11101: decode4to16w1e = 15'h1000;
  5'b11110: decode4to16w1e = 15'h2000;
  5'b11111: decode4to16w1e = 15'h4000;
  default:  decode4to16w1e = 15'h0000;
endcase
end
endfunction

function [3:0] code2to4;
input [1:0] code;
begin
case(code)
  2'b00: code2to4 = 4'b0001;
  2'b01: code2to4 = 4'b0010;
  2'b10: code2to4 = 4'b0100;
  2'b11: code2to4 = 4'b1000;
  default: code2to4 = 4'b0000;
endcase
end
endfunction

function [1:0] quiet_sm_func;
input	[1:0]	req_ack_sm;
input		req_quiet;
input		ack_quiet; 	

reg [1:0] ns;               // next state

begin
  case (req_ack_sm)
// NREQ_NACK is used when there is no request to go quiescent
// and there is no acknowledge from that request
	`NREQ_NACK:		// no request, no acknowledge
	   begin		// wait for a request
	     if (req_quiet)
		ns = `REQ_NACK;
             else ns = `NREQ_NACK;
	   end
	`REQ_NACK:		// request but no acknowledge yet 
	   begin		// waiting for ack to go on
	     if (ack_quiet)
		ns = `REQ_ACK;
	     else ns = `REQ_NACK;
	   end
	`REQ_ACK:		// had request and acknowledge
	   begin		// waiting for request to go off
	     if (~req_quiet)
		ns = `NREQ_ACK;
	     else ns = `REQ_ACK;
	   end
	`NREQ_ACK:		// no request, wait for ack to go off
	   begin		// 
	     if (~ack_quiet)
		ns = `NREQ_NACK;
	     else ns = `NREQ_ACK;
	   end
  endcase
quiet_sm_func[1:0] = ns;
end
endfunction

// add timer module
timers	timers(
	.reset			(reset),
	.clock			(clock),
	.tmr_clk		(tmr_clk),

	.pci_config_wdata	(pci_config_wdata),
	.pci_config_wbe		(pci_config_wbe),
	.pci_config_wadd	(pci_config_wadd),
	.pci_config_radd	(pci_config_radd),
	.pci_config_we		(pci_config_we),
	.afx_rd_wrt		(afx_rd_wrt),

	.rd_sys_cntr		(rd_sys_cntr),
	.rd_sys_lmt		(rd_sys_lmt),
	.rd_prc_cntr		(rd_prc_cntr),
	.rd_prc_lmt		(rd_prc_lmt),
	.tmr_conf_reg		(tmr_conf_reg),

	.sys_intr		(sys_intr),
	.sys_intr_lvl		(sys_intr_lvl),
	.prc_intr		(prc_intr),
	.prc_intr_lvl		(prc_intr_lvl)
	);

// add system reset control and status register.
sys_rst_cntl sys_rst_cntl(
	.input_reset_l		(input_reset_l),
	.reset			(reset),
	.pci_clk		(pci_clk),
	.gclk			(clock),
	.iu_error		(iu_error),
	.pci_slave_mode		(pci_slave_mode),
	.pci_syncg_rst		(pci_syncg_rst),

	.pci_config_wdata	(pci_config_wdata),
	.pci_config_wbe		(pci_config_wbe),
	.pci_config_wadd	(pci_config_wadd),
	.pci_config_radd	(pci_config_radd),
	.pci_config_we		(pci_config_we),

	.sw_rst			(sw_rst),
	.en_sw_rst_nonwd	(en_sw_rst_nonwd),

	.en_pci_sw_rst		(en_pci_sw_rst),
	.sys_rst_reg		(sys_rst_reg)
	);

endmodule

// This module generates the two timer interrupts. It attempts to 
// duplicate the funcionality of the timers from the slavio. One
// timer, the system counter, only functions as a 31 bit counter.
// The other timer, the processor counter or user timer, can function
// as either another timer when set as the processor counter, or
// as a 63 bit processor counter, which does not generate an interrupt
// when used as a user timer.


module timers 
	(
	reset,
	clock,			// gclk domain (stopped in standby)
	tmr_clk,		// free running at sys_clk divide by 4

	pci_config_wdata,
	pci_config_wbe,
	pci_config_wadd,
	pci_config_radd,
	pci_config_we,
	afx_rd_wrt,		// pulse for read Or write

	rd_sys_cntr,		// system counter syncd to gclk
	rd_sys_lmt,		// system limit 
	rd_prc_cntr,		// processor counter syncd to gclk
	rd_prc_lmt,		// processor limit
	tmr_conf_reg,		// timer configuration register

	sys_intr,		// system counter interrupt
	sys_intr_lvl,		// system timer interrupt programmable levels
	prc_intr,		// processor counter interrupt
	prc_intr_lvl		// processor timer interrupt programmable levels
	);

input		reset;
input		clock;
input		tmr_clk;

input	[31:0]	pci_config_wdata;
input	[3:0]	pci_config_wbe;
input	[7:0]	pci_config_wadd;
input	[7:0]	pci_config_radd;
input		pci_config_we;
input		afx_rd_wrt;

output [31:0]	rd_sys_cntr;
output [31:0]	rd_sys_lmt;
output [31:0]	rd_prc_cntr;
output [31:0]	rd_prc_lmt;
output [23:0]	tmr_conf_reg;

output 		sys_intr;
output [3:0]	sys_intr_lvl;
output 		prc_intr;
output [3:0]	prc_intr_lvl;

reg		wrt_prc_lmt_g;
reg		wrt_prc_cntr_g;
reg		wrt_prc_lmt_no_reset_g;
reg		wrt_sys_lmt_g;
reg		wrt_sys_cntr_g;
reg		wrt_sys_lmt_no_reset_g;
reg		rd_prc_lmt_g;
reg		rd_prc_cntr_g;
reg		rd_sys_lmt_g;
reg		rd_sys_cntr_g;

reg		wrt_prc_lmt_t;
reg		wrt_prc_cntr_t;
reg		wrt_prc_lmt_no_reset_t;
reg		wrt_sys_lmt_t;
reg		wrt_sys_cntr_t;
reg		wrt_sys_lmt_no_reset_t;
reg		rd_prc_lmt_t;
reg		rd_prc_cntr_t;
reg		rd_sys_lmt_t;
reg		rd_sys_cntr_t;
reg		tmr_run_enbl_t;
reg		tmr_user_mode_t;
reg		hld_usr_msw_rf;

reg	[31:0]	tmr_wrt_hld_reg;
reg	[7:0]	tmr_int_lvls;
reg		tmr_run_enbl;
reg		tmr_user_mode;
reg		tmr_prc_wenbl;
reg		tmr_sys_wenbl;
reg	[30:0]	usr_tmr_wrt_msw_shdo ;
reg	[31:0]	usr_tmr_rd_msw_shdo ;
reg	[31:0]	usr_tmr_msw ;
reg	[31:0]	prc_cntr ;
reg	[31:0]	prc_cntr_sync ;
reg	[30:0]	prc_cntr_lmt ;
reg	[30:0]	sys_cntr ;
reg	[30:0]	sys_cntr_sync ;
reg	[30:0]	sys_cntr_lmt ;
reg	sys_cntr_lmt_rchd;
reg	prc_cntr_lmt_rchd;
reg	sys_cntr_lmt_rchd_g;
reg	prc_cntr_lmt_rchd_g;

// this part will do the decodes to load up the registers.
// Since the decodes are generated on a gclk (30ns base speed),
// the outputs will be ff's that will go to the next level, that are
// clocked on the timer clock (40 ns base speed).

wire 	wrt_prc_lmt = (pci_config_wadd[7:0] == 8'hac) & pci_config_we;
// wrt_prc_lmt also is to write user timer msw shadow register
wire	wrt_prc_cntr = (pci_config_wadd[7:0] == 8'hb0) & pci_config_we;
wire	wrt_prc_lmt_no_reset = (pci_config_wadd[7:0] == 8'hb4) & pci_config_we;
wire	wrt_sys_lmt = (pci_config_wadd[7:0] == 8'hb8) & pci_config_we;
wire	wrt_sys_cntr = (pci_config_wadd[7:0] == 8'hbc) & pci_config_we;
wire	wrt_sys_lmt_no_reset = (pci_config_wadd[7:0] == 8'hc0) & pci_config_we;
wire	wrt_tmr_conf = (pci_config_wadd[7:0] == 8'hc4) & pci_config_we;

wire	afx_read_pulse = ~pci_config_we & afx_rd_wrt;
wire	rd_prc_lmt_dcd = (pci_config_wadd[7:0] == 8'hac) & afx_read_pulse;
// rd_prc_lmt is also used to read the user timer msw shadow register
wire	rd_prc_cntr_dcd = (pci_config_wadd[7:0] == 8'hb0) & afx_read_pulse;
wire	rd_sys_lmt_dcd = (pci_config_wadd[7:0] == 8'hb8) & afx_read_pulse;
wire	rd_sys_cntr_dcd = (pci_config_wadd[7:0] == 8'hbc) & afx_read_pulse;
wire	wrt_any_tmr_reg = (wrt_prc_lmt | wrt_prc_cntr | wrt_prc_lmt_no_reset |
			wrt_sys_lmt | wrt_sys_lmt_no_reset | wrt_sys_cntr );

wire	hold_usr_msw_shdor = rd_prc_cntr_dcd | hld_usr_msw_rf ;
wire	prc_cntr_eql_lmt = (prc_cntr[30:0] == prc_cntr_lmt);
wire	sys_cntr_eql_lmt = (sys_cntr == sys_cntr_lmt);
wire	prc_cntr_eql_ff = (prc_cntr == 32'hffffffff);

wire	[3:0]	sys_intr_lvl = tmr_int_lvls[7:4];
wire	[3:0]	prc_intr_lvl = tmr_int_lvls[3:0];

wire	[31:0]	rd_sys_cntr = ({sys_cntr_lmt_rchd_g, sys_cntr_sync[30:0]});
wire	[31:0]	rd_sys_lmt = ({sys_cntr_lmt_rchd_g, sys_cntr_lmt[30:0]}); 
wire	[31:0]	rd_prc_cntr = (tmr_user_mode ? prc_cntr_sync : {prc_cntr_lmt_rchd_g,prc_cntr_sync[30:0]});
wire	[31:0]	rd_prc_lmt = (tmr_user_mode ? usr_tmr_rd_msw_shdo : {prc_cntr_lmt_rchd_g,prc_cntr_lmt[30:0]});
wire	[23:0]	tmr_conf_reg = ({tmr_int_lvls, tmr_sys_wenbl, tmr_prc_wenbl, 5'b0,
				 tmr_user_mode, 7'b0, tmr_run_enbl});

wire [31:0] usr_tmr_rd_msw_shdoin = (hold_usr_msw_shdor ? usr_tmr_rd_msw_shdo : usr_tmr_msw);
wire [31:0] tmr_wrt_hld_regin = (wrt_any_tmr_reg ? pci_config_wdata : tmr_wrt_hld_reg);

wire [7:0]   tmr_int_lvlsin;
assign tmr_int_lvlsin = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : tmr_int_lvls[7:0]);
wire  tmr_sys_wenblin = (~pci_config_wbe[1] ? pci_config_wdata[15] : tmr_sys_wenbl);
wire  tmr_prc_wenblin = (~pci_config_wbe[1] ? pci_config_wdata[14] : tmr_prc_wenbl);
wire  tmr_user_modein = (~pci_config_wbe[1] ? pci_config_wdata[8] : tmr_user_mode);
wire  tmr_run_enblin = (~pci_config_wbe[0] ? pci_config_wdata[0] : tmr_run_enbl);

// these are the registers that change on gclk edge
// 
always @(posedge clock)
begin
  if (reset)
    begin
    wrt_prc_lmt_g <= #1 1'b0;
    wrt_prc_cntr_g <= #1 1'b0;
    wrt_sys_cntr_g <= #1 1'b0;
    wrt_prc_lmt_no_reset_g <= #1 1'b0;
    wrt_sys_lmt_g <= #1 1'b0;
    wrt_sys_lmt_no_reset_g <= #1 1'b0;
    rd_prc_lmt_g <= #1 1'b0;
    rd_prc_cntr_g <= #1 1'b0;
    rd_sys_lmt_g <= #1 1'b0;
    rd_sys_cntr_g <= #1 1'b0;
    tmr_int_lvls[7:0] <= #1 8'h00;
    tmr_user_mode <= #1 1'b0;
    tmr_prc_wenbl <= #1 1'b0;
    tmr_sys_wenbl <= #1 1'b0;
    tmr_run_enbl <= #1 1'b0;
    tmr_wrt_hld_reg <= #1 32'h00000000;
    prc_cntr_sync <= #1 32'h00000000;
    sys_cntr_sync[30:0] <= #1 31'h00000000;
    sys_cntr_lmt_rchd_g <= #1 1'b0;
    prc_cntr_lmt_rchd_g <= #1 1'b0;
    usr_tmr_rd_msw_shdo <= #1 32'h00000000;
    hld_usr_msw_rf <= #1 1'b0;
    end
  else 
    begin
    wrt_prc_lmt_g <= #1 (wrt_prc_lmt | wrt_prc_lmt_g & ~wrt_prc_lmt_t);
    wrt_prc_cntr_g <= #1 (wrt_prc_cntr | wrt_prc_cntr_g & ~wrt_prc_cntr_t);
    wrt_prc_lmt_no_reset_g <= #1 (wrt_prc_lmt_no_reset |
			wrt_prc_lmt_no_reset_g & ~wrt_prc_lmt_no_reset_t);
    wrt_sys_lmt_g <= #1 (wrt_sys_lmt | wrt_sys_lmt_g & ~wrt_sys_lmt_t);
    wrt_sys_cntr_g <= #1 (wrt_sys_cntr | wrt_sys_cntr_g & ~wrt_sys_cntr_t);
    wrt_sys_lmt_no_reset_g <= #1 (wrt_sys_lmt_no_reset |
			 wrt_sys_lmt_no_reset_g & ~wrt_sys_lmt_no_reset_t);
    rd_prc_lmt_g <= #1 (rd_prc_lmt_dcd | rd_prc_lmt_g & ~rd_prc_lmt_t);
    rd_prc_cntr_g <= #1 (rd_prc_cntr_dcd | rd_prc_cntr_g & ~rd_prc_cntr_t);
    rd_sys_lmt_g <= #1 (rd_sys_lmt_dcd | rd_sys_lmt_g & ~rd_sys_lmt_t) ;
    rd_sys_cntr_g <= #1 (rd_sys_cntr_dcd | rd_sys_cntr_g & ~rd_sys_cntr_t) ;
    hld_usr_msw_rf <= #1 (rd_prc_cntr_dcd | hld_usr_msw_rf & ~rd_prc_lmt_dcd ) ;
    prc_cntr_sync <= #1 prc_cntr;
    sys_cntr_sync[30:0] <= #1 sys_cntr[30:0];
    sys_cntr_lmt_rchd_g <= #1 sys_cntr_lmt_rchd; 
    prc_cntr_lmt_rchd_g <= #1 prc_cntr_lmt_rchd; 
    usr_tmr_rd_msw_shdo <= #1 usr_tmr_rd_msw_shdoin;
    tmr_wrt_hld_reg <= #1 tmr_wrt_hld_regin;
    if (wrt_tmr_conf)
      begin
      tmr_int_lvls[7:0] <= #1 tmr_int_lvlsin; 
      tmr_sys_wenbl <= #1 tmr_sys_wenblin;
      tmr_prc_wenbl <= #1 tmr_prc_wenblin;
      tmr_user_mode <= #1 tmr_user_modein;
      tmr_run_enbl <= #1 tmr_run_enblin;
      end
    end
end

wire	[30:0]	prc_cntr_lmtin = (wrt_prc_lmt_t | wrt_prc_lmt_no_reset_t) ?
			tmr_wrt_hld_reg[30:0] : prc_cntr_lmt;
wire	[30:0]	usr_tmr_wrt_msw_shdoin = (wrt_prc_lmt_t & tmr_user_mode_t) ?
			 tmr_wrt_hld_reg[30:0] : usr_tmr_wrt_msw_shdo;
wire	[31:0]	prc_cntrin = ((wrt_prc_cntr_t & ~tmr_user_mode_t & tmr_prc_wenbl) |
			(tmr_user_mode_t & wrt_prc_cntr_t)) ?	// load prc_cntr
			tmr_wrt_hld_reg : 
			((wrt_prc_lmt_t & ~tmr_user_mode_t) |
			 (prc_cntr_eql_lmt & ~tmr_user_mode_t)) ? // set to 0x01
			32'h00000001 :
			(~tmr_user_mode_t | tmr_run_enbl_t) ?	// inc prc_cntr
			(prc_cntr + 1'b1) : 
			prc_cntr ;                             // or hold    
wire	[31:0]	usr_tmr_mswin = (wrt_prc_cntr_t & tmr_user_mode_t) ?	// load from shadow
			usr_tmr_wrt_msw_shdo :
			(prc_cntr_eql_ff & tmr_user_mode_t &
			 tmr_run_enbl_t) ?			// inc if lsw is 0xff
			(usr_tmr_msw + 1'b1) :			
			usr_tmr_msw ;				// or hold
wire	[30:0]	sys_cntr_lmtin = (wrt_sys_lmt_t | wrt_sys_lmt_no_reset_t) ?
			tmr_wrt_hld_reg[30:0] : sys_cntr_lmt;
    

wire	[30:0]	sys_cntrin = (wrt_sys_cntr_t & tmr_sys_wenbl) ?		// load sys_cntr
			tmr_wrt_hld_reg :
			(wrt_sys_lmt_t | sys_cntr_eql_lmt) ?	// set to 0x01
                         32'h00000001 :
			(sys_cntr + 1'b1);			// or inc

// these are the registers that are clocked on the timer clock (tmr_clk)
// which is at one-fourth the processor rate, free running (like refresh)
always @(posedge tmr_clk)
begin
  if (reset)
    begin
    usr_tmr_wrt_msw_shdo <= #1 31'h00000000;
    usr_tmr_msw <= #1 32'h00000000;
    prc_cntr_lmt <= #1 31'h00000000;
    prc_cntr <= #1 32'h00000001;
    sys_cntr_lmt <= #1 31'h00000000;
    sys_cntr <= #1 32'h00000001;
    wrt_prc_lmt_t <= #1 1'b0;
    wrt_prc_cntr_t <= #1 1'b0;
    wrt_prc_lmt_no_reset_t <= #1 1'b0;
    wrt_sys_lmt_t <= #1 1'b0;
    wrt_sys_lmt_no_reset_t <= #1 1'b0;
    wrt_sys_cntr_t <= #1 1'b0;
    rd_prc_lmt_t <= #1 1'b0;
    rd_prc_cntr_t <= #1 1'b0;
    rd_sys_lmt_t <= #1 1'b0;
    rd_sys_cntr_t <= #1 1'b0;
    tmr_run_enbl_t <= #1 1'b0;
    tmr_user_mode_t <= #1 1'b0;
    end
  else 
    begin					// transfered each clock
    wrt_prc_lmt_t <= #1 wrt_prc_lmt_g;
    wrt_prc_cntr_t <= #1 wrt_prc_cntr_g;
    wrt_prc_lmt_no_reset_t <= #1 wrt_prc_lmt_no_reset_g;
    wrt_sys_lmt_t <= #1 wrt_sys_lmt_g;
    wrt_sys_lmt_no_reset_t <= #1 wrt_sys_lmt_no_reset_g;
    wrt_sys_cntr_t <= #1 wrt_sys_cntr_g;
    rd_prc_lmt_t <= #1 rd_prc_lmt_g;
    rd_prc_cntr_t <= #1 rd_prc_cntr_g;
    rd_sys_lmt_t <= #1 rd_sys_lmt_g;
    rd_sys_cntr_t <= #1 rd_sys_cntr_g;
    tmr_run_enbl_t <= #1 tmr_run_enbl;
    tmr_user_mode_t <= #1 tmr_user_mode;

// processor counter registers
    prc_cntr_lmt <= #1 prc_cntr_lmtin;
    usr_tmr_wrt_msw_shdo <= #1 usr_tmr_wrt_msw_shdoin;
    prc_cntr <=  #1 prc_cntrin;
    usr_tmr_msw <=  #1 usr_tmr_mswin;

// system counter regsiters
    sys_cntr_lmt <= #1 sys_cntr_lmtin;
    sys_cntr <= #1 sys_cntrin;
    end
end

// now the interrupt generation stuff.

always @(posedge tmr_clk)
begin
  if (reset)
    begin
    sys_cntr_lmt_rchd <= #1 1'b0;
    prc_cntr_lmt_rchd <= #1 1'b0;
    end
  else
    begin
    sys_cntr_lmt_rchd <= #1 (sys_cntr_eql_lmt | sys_cntr_lmt_rchd & ~rd_sys_lmt_t);
    prc_cntr_lmt_rchd <= #1 (prc_cntr_eql_lmt | prc_cntr_lmt_rchd & ~rd_prc_lmt_t);
    end
end

assign sys_intr = sys_cntr_lmt_rchd;
assign prc_intr = prc_cntr_lmt_rchd & ~tmr_user_mode_t;

// Added spare cells 
 
        spares  intr_spares ();
 
endmodule


module sys_rst_cntl
	(
	input_reset_l,		// the big reset, from the pin
	reset,			// pcic reset, which is non_wd
	iu_error,		// watchdog reset source
	pci_clk,		// pci free running clock
	gclk,			// afx gclock
	pci_slave_mode,		// pin setting for slave mode on powerup
	pci_syncg_rst,		// pci reset input through a gclk

	pci_config_wdata,	// write data for registers
	pci_config_wbe,		// write byte enables
	pci_config_wadd,	// write address (lsb's are xx)
	pci_config_radd,	// read address
	pci_config_we,		// actural write enable

	sw_rst,			// reset out, resets iu (like reset_any)
	en_sw_rst_nonwd,	// reset out, resets all (like reset_nonwd)

	en_pci_sw_rst,		// enable pci reset to act like a sw_rst
	sys_rst_reg		// system reset control status register out
	);

input		input_reset_l;
input		reset;
input		iu_error;
input		pci_clk;
input		gclk;
input		pci_slave_mode;
input		pci_syncg_rst;

input	[31:0]	pci_config_wdata;
input	[3:0]	pci_config_wbe;
input	[7:0]	pci_config_wadd;
input	[7:0]	pci_config_radd;
input		pci_config_we;

output 		sw_rst;
output 		en_sw_rst_nonwd;
output 		en_pci_sw_rst;
output	[7:0]	sys_rst_reg;

reg		sw_reset_reg;
reg		sw_reset_ind;
reg		wd_reset_ind;
reg		in_reset_ind;
reg		pci_reset_ind;
reg		en_pci_sw_rst;
reg		input_reset_l_g;
reg		sw_reset_reg_p;
reg	[14:0]	sw_rst_tmr;

wire	[7:0]	sys_rst_reg;
assign sys_rst_reg = {pci_slave_mode,en_pci_sw_rst,pci_reset_ind,
			wd_reset_ind,in_reset_ind,1'b0,sw_reset_ind,1'b0};
wire 	wrt_sys_rst_reg = (pci_config_wadd[7:0] == 8'hd0) & pci_config_we
				& ~pci_config_wbe[0];
wire set_sw_ind = (sw_reset_reg | (wrt_sys_rst_reg & pci_config_wdata[00])); 
wire rst_sw_ind = (~input_reset_l_g | (pci_syncg_rst & en_pci_sw_rst)
                        | (wrt_sys_rst_reg & ~pci_config_wdata[01]));
wire sw_reset_ind_in = (set_sw_ind ? 1'b1 : rst_sw_ind ? 1'b0 : sw_reset_ind);

wire set_wd_ind = iu_error;
wire rst_wd_ind = (reset | (wrt_sys_rst_reg & ~pci_config_wdata[04]));
wire wd_reset_ind_in = (set_wd_ind ? 1'b1 : rst_wd_ind ? 1'b0 : wd_reset_ind);

wire rst_in_ind = (wrt_sys_rst_reg & ~pci_config_wdata[03]);
wire in_reset_ind_in = (~input_reset_l_g ? 1'b1 : rst_in_ind ? 1'b0 : in_reset_ind);

wire set_pci_ind = (pci_syncg_rst & en_pci_sw_rst);
wire rst_pci_ind = (~input_reset_l_g | (wrt_sys_rst_reg & ~pci_config_wdata[05]));
wire pci_reset_ind_in = (set_pci_ind ? 1'b1 : rst_pci_ind ? 1'b0 : pci_reset_ind);

wire	[14:0]	sw_rst_tmr_in;
assign sw_rst_tmr_in = (~input_reset_l 	? 15'h0000 : 	// clear on powerup
	(sw_reset_reg_p & ~|sw_rst_tmr) ? 15'h0001 :	// load with 0x01 on sw reset

// next two lines are for debug only
//	(sw_rst_tmr == 15'h00ff)	? 15'h7bf0 :	// jump to near transition
//	(sw_rst_tmr == 15'h7c0f)	? 15'h7f00 :	// jump to near end

		   |sw_rst_tmr		? (sw_rst_tmr + 1'b1): // increment if not zero
			    15'h0000 );			// keep at zero

wire rst_tmr_msb_all_ones = &sw_rst_tmr[14:10];	// these bits reach ones in 1.047 ms
wire rst_tmr_any_ones = |sw_rst_tmr[14:0];	// these bits reach zero in 1.081 ms

wire sw_rst = rst_tmr_any_ones;
wire en_sw_rst_nonwd = rst_tmr_msb_all_ones;

always @(posedge gclk)
begin
  if (reset)
    begin
    en_pci_sw_rst <= #1 pci_slave_mode;
    sw_reset_reg <= #1 1'b0;
    end
  else if (wrt_sys_rst_reg)
    begin
    en_pci_sw_rst <= #1 pci_config_wdata[06] & pci_slave_mode;
    sw_reset_reg <= #1 pci_config_wdata[00] ; 
  end
end

always @(posedge gclk)
begin
  input_reset_l_g <= #1 input_reset_l;
  sw_reset_ind <= #1 sw_reset_ind_in;
  wd_reset_ind <= #1 wd_reset_ind_in;
  in_reset_ind <= #1 in_reset_ind_in;
  pci_reset_ind <= #1 pci_reset_ind_in;
end

always @(posedge pci_clk)
begin
  sw_reset_reg_p <= #1 sw_reset_reg;
  sw_rst_tmr <= #1 sw_rst_tmr_in;
end
 
endmodule