/******************************************************************************/
/* */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)interrupts.v
***
***
*** Description:
*** This is the interrupt module. It duplicates much of the interrrupt
*** control logic of that slavio, but for pci purposes only. In such
*** it receives 4 asynchronous interrupts from pci slots, and generates
*** four coded interrupts on the irl lines to the processor. It can
*** also receive an error interrupt from the falcon itself.
***
*** Revision 1.0 Include an interrupt for PCI Serr singnaling. SERR is
*** signalled (asynchronously) to indicate a fatal error has
*** occured on the pci bus. This generates a level 15 interrupt to IIe.
*** (Note: idsel's and lock logic removed also, even though module connections
*** remain.)
*** Rev: 1.1. Added special clocks for synchronizers to work in scan mode.
*** Rev: 1.2 Added Quiescence request to pci slave and acknolwedge responce
*** Rev: 1.3 Added task to make interrupt inputs programmable as to which
*** priority each goes to, also added a disable to allow the pci_int
*** int lines to bypass all the interrupt control login and drive the
*** irl lines directly, also changed the decodes of all the necessary
*** registers to match the rev1.2 IIep spec.
*** Rev: 1.4 Added input pin mm_lvl15_int_l, which was missing. Also removed
*** all ff's from the interrupt paths in generating the irl's to
*** processor, since the processor double clocks these to resync.
*** Rev 1.6 Changed all ff inputs to wires, just for good rtl coding style.
*** Added 4 additional interrupt pins, and made all 8 outputs.
*** Removed inversion (by adding inverters) when interrupts in bypass.
*** Rev 1.7 Adding System Reset control and status register, like was in slavio.
***
*** 3/11/98: fixed pci_sync_serr_ which was defined twice.
***
***
****************************************************************************
****************************************************************************/
![[Up: pcic interrupts]](v2html-up.gif)
module interrupts
(
input_reset_l, // raw power up reset pin
iu_error, // watchdog reset source
pci_slave_mode, // input from pin jumper settings
raw_pci_rst_l, // input from raw pin
sw_rst, // output to rst_cntl, causing reset (any_reset)
en_sw_rst_nonwd, // output to rst_cntl, causing reset (reset_nonwd)
en_pci_sw_rst, // output enableing pci reset as an input, allowing it
// to be treated like a sw reset (with a unique indicator)
reset, // any nonwatchdog reset
clock, // afx g clock
tmr_clk, // timer clock, refresh clock divided by 4.
pci_clk, // pci clock
pci_int_, // pci interrupt (int_l[7:0] -> INTH/G/F/E/D/C/B/A#)
pci_int_oe, // pci interrupt output enables
afx_mast_error_address, // master detected error, reference address
afx_mast_error_cmd, // master detected error, reference command
afx_mast_error, // master detected error, (level 15 interrupt)
afx_slave_error, // slave detected error, (level 15 interrupt)
pci_serr_, // pci detected "fatal" error, (level 15 interrupt)
iotlb_cd_in_reg, // iotlb cam input data register
iotlb_rd_in_reg, // iotlb ram input data register
iotlb_cd_out_reg, // iotlb cam output data register
iotlb_rd_out_reg, // iotlb ram output data register
iotlb_cntl_reg, // iotlb control input register
iotlb_cntl_wrt, // iotlb control write pulse
iotlb_err, // iotlb miss error,
iotlb_err_address, // iotlb miss error address
iotlb_enable, // iotlb bypass or enable
mm_lvl15_int_l, // cpu is signaling level 15 interrupt
any_intrnl_int_l, // OR of any internally generated interrupts
any_xint, // any external interrupts set
irl, // host processor interrupt level
prefetch_enable, // afx_slave prefetch enable
burst_enable, // afx_slave data burst enable
idsel, // configuration idsel's to 4 pci slots
arb_lock_en, // arbiter enable responce to lock on pci bus
arb_lvl_en, // arbiter enable for 3 levels of priority rotation
arb_disable, // arbiter disable totally
cfg_fast_decode, // configure pci to respond to fast decodes.
afx_master_cfg, // afx_master configuration enables (to be added)
req_quiescence, // request to have quiescence in the pci slave input
ack_quiescence, // acknowledge of quiescence in the pci slave input
smbar0, // afx to pci address translation/mapping
msize0, // afx to pci address translation/mapping
pmbar0, // afx to pci address translation/mapping
smbar1, // afx to pci address translation/mapping
msize1, // afx to pci address translation/mapping
pmbar1, // afx to pci address translation/mapping
sibar, // afx to pci address translation/mapping
isize, // afx to pci address translation/mapping
pibar, // afx to pci address translation/mapping
isabar, // pci to afx address translation/mapping
pci_config_wdata, // falcon reg data in
pci_config_wbe, // falcon reg byte marks
pci_config_wadd, // falcon reg write address
pci_config_radd, // falcon reg read address
pci_config_we, // falcon reg write enable
pci_config_rdata, // falcon reg read data
afx_rd_wrt, // pulse for read OR writing from falcon.
cfg_config_out, // config data from pci core
scan_en, // scan enabled (test mode)
pci_clk_sync, // rising edge pci_clk for synchronizers
pci_clk_sync_, // falling edge pci_clk for synchronizers
gclk_sync, // rising edge gclk for synchronizers
gclk_sync_, // falling edge gclk for synchronizers
pcim_big_endian, // pci master (afx slave) big endian
pcis_big_endian, // pci slave (afx master) big endian
discard_timer, // pci slave discard timer (discard saved data)
arb_asgn_reg // arbitration assignment (priority) register
);
// The interrupt controller attempts to duplicate the functionality of the
// interrupt controller that is in the slavio component. (NCR89C105) This
// interface tries to duplicate much of that logic, since the falcon chip
// is intended to replace the slavio in a migratory process. The falcon is
// intended to co-exist with the slavio at first. In this environment, the
// slavio supports the interrupts, most of which are due to i/o through the
// sbus or slavio itself. The four pci interrupts are synchronized with the
// pci clock (which they probably are synchronous to already). Then they
// are resynced to the afx clock. After this they are treated like the first
// four sbus interrupt requests. (When the falcon is not supplying the
// irl lines to the IIe, the slavio can receive the pci interrupt on one of
// the sbus interrupt inputs.) After this point most of the masking and clearing
// of the interrupts is the same as on the slavio.
`define NREQ_NACK 2'b00
`define NREQ_ACK 2'b01
`define REQ_ACK 2'b11
`define REQ_NACK 2'b10
input input_reset_l;
input iu_error;
input pci_slave_mode;
input raw_pci_rst_l;
output sw_rst;
output en_sw_rst_nonwd;
output en_pci_sw_rst;
input reset;
input clock;
input tmr_clk;
input pci_clk;
input pci_clk_sync;
input pci_clk_sync_;
input gclk_sync;
input gclk_sync_;
output any_intrnl_int_l;
input mm_lvl15_int_l;
input [7:0] pci_int_;
input [31:0] afx_mast_error_address;
input [3:0] afx_mast_error_cmd;
input afx_mast_error;
input afx_slave_error;
input pci_serr_;
input ack_quiescence;
input [31:0] iotlb_cd_out_reg;
input [31:0] iotlb_rd_out_reg;
input iotlb_err;
input [31:0] iotlb_err_address;
output [31:0] iotlb_cd_in_reg;
output [31:0] iotlb_rd_in_reg;
output [7:0] iotlb_cntl_reg;
output iotlb_cntl_wrt;
output iotlb_enable;
output any_xint;
output req_quiescence;
output [3:0] irl;
output prefetch_enable;
output burst_enable;
output [4:1] idsel;
output arb_lock_en;
output arb_lvl_en;
output arb_disable;
output cfg_fast_decode;
output [3:0] afx_master_cfg;
output [3:0] smbar0;
output [3:0] msize0;
output [7:0] pmbar0;
output [3:0] smbar1;
output [3:0] msize1;
output [7:0] pmbar1;
output [3:0] sibar;
output [3:0] isize;
output [7:0] pibar;
output [3:0] isabar;
input [31:0] pci_config_wdata;
input [3:0] pci_config_wbe;
input [7:0] pci_config_wadd;
input [7:0] pci_config_radd;
input pci_config_we;
input afx_rd_wrt;
output [31:0] pci_config_rdata;
output [7:0] pci_int_oe;
input [31:0] cfg_config_out;
input scan_en;
output pcim_big_endian; // pci master big endian (for config)
output pcis_big_endian; // pci slave big endian
output [14:0] arb_asgn_reg; // arbitration assignment (priority) register
output [15:0] discard_timer; // pci slave discard timer value.
// add some wire interconnect for the sys_rst_cntl
wire sw_rst;
wire en_sw_rst_nonwd;
wire en_pci_sw_rst;
wire [7:0] sys_rst_reg;
// removed it. defined twice.
// wire pci_sync_serr_; // resync outputs, synced to pci_clk
wire pci_sync_serr_; // resync outputs, synced to pci_clk
wire afx_sync_serr; // resync output, synced to afx_clock
wire pci_syncg_rst; // resync output, synced to afx_clock
wire pci_syncp_rst; // resync output, synced to pci_clock
wire pci_sync_int0_; // resync outputs, synced to pci_clk
wire pci_sync_int1_; // resync outputs, synced to pci_clk
wire pci_sync_int2_; // resync outputs, synced to pci_clk
wire pci_sync_int3_; // resync outputs, synced to pci_clk
wire pci_sync_int4_; // resync outputs, synced to pci_clk
wire pci_sync_int5_; // resync outputs, synced to pci_clk
wire pci_sync_int6_; // resync outputs, synced to pci_clk
wire pci_sync_int7_; // resync outputs, synced to pci_clk
reg [7:6] afx_slave_cfg;
reg [2:0] pci_idsel_cfg;
reg [3:0] afx_master_cfg;
reg [4:0] pci_arb_cfg;
reg pcim_big_endian;
wire iotlb_enable = afx_master_cfg[1];
wire prefetch_enable = afx_slave_cfg[7];
wire burst_enable = afx_slave_cfg[6];
wire pcis_big_endian = afx_master_cfg[2];
wire [4:1] idsel = 4'b0000;
wire arb_lock_en = 1'b0;
wire arb_lvl_en = pci_arb_cfg[0];
wire arb_disable = pci_arb_cfg[2];
wire cfg_fast_decode = pci_arb_cfg[3];
wire int_ctlr_disable = pci_arb_cfg[4];
wire any_xint;
wire any_intrnl_int_l;
wire [15:1] s_tmr_int;
wire [15:1] p_tmr_int;
wire [15:1] a_pci_int;
wire [15:1] b_pci_int;
wire [15:1] c_pci_int;
wire [15:1] d_pci_int;
wire [15:1] e_pci_int;
wire [15:1] f_pci_int;
wire [15:1] g_pci_int;
wire [15:1] h_pci_int;
wire [15:1] hw_int;
wire [15:1] tmr_ints;
wire unmasked_tmr_int;
wire [15:1] unmasked_hw_int;
wire [31:0] rd_sys_cntr;
wire [31:0] rd_sys_lmt;
wire [31:0] rd_prc_cntr;
wire [31:0] rd_prc_lmt;
wire [23:0] tmr_conf_reg;
wire sys_intr;
wire [3:0] sys_intr_lvl;
wire prc_intr;
wire [3:0] prc_intr_lvl;
reg [3:0] smbar0;
reg [3:0] msize0;
reg [7:0] pmbar0;
reg [3:0] smbar1;
reg [3:0] msize1;
reg [7:0] pmbar1;
reg [3:0] sibar;
reg [3:0] isize;
reg [7:0] pibar;
reg [3:0] isabar;
reg [31:0] iotlb_cd_in_reg;
reg [31:0] iotlb_rd_in_reg;
reg [7:0] iotlb_cntl_reg;
reg [31:0] iotlb_err_address_reg;
wire ack_quiet_rd;
// afx configuration register made up of slave, idsel, master, and arbiter control.
wire [31:0] afx_config = {3'h0, pci_arb_cfg, 3'h0, ack_quiet_rd,
afx_master_cfg, 5'h00, pci_idsel_cfg, afx_slave_cfg, 3'h0,pcim_big_endian,2'h0};
reg [15:1] soft_int;
reg mask_all;
reg mask_mast_err;
reg mask_slave_err;
reg mask_serr;
reg mask_mm_lvl15;
reg mask_pci_rst;
reg [15:1] mask_hw;
reg afxm_error_reg;
reg afxs_error_reg;
reg pci_rst_reg;
reg pci_serr_reg;
reg pci_serr_ff1_;
reg pci_serr_ff2_;
reg pci_serr_ff3;
reg [1:0] req_ack_sm;
reg req_quiet1;
reg req_quiescence;
reg ack_quiet;
wire [1:0] req_ack_sm_in;
wire req_quiet2;
wire req_quiet = afx_master_cfg[0];
wire ack_quiet1;
wire req_quiet1_in;
reg [15:0] int_asgn_reg;
reg [15:0] int_asgn_reg2;
reg [7:0] int_output_reg;
reg [14:0] arb_asgn_reg;
reg [15:0] discard_timer;
wire [7:0] pci_int = ~pci_int_;
wire [7:0] pci_int_oe = int_output_reg;
// implement quienscence state machine stuff
assign req_quiet1_in = ~reset &
(((req_ack_sm == `NREQ_NACK) & afx_master_cfg[0]) |
(req_ack_sm == `REQ_NACK) |
((req_ack_sm == `REQ_ACK) & afx_master_cfg[0]));
assign req_ack_sm_in = reset ? 2'b00 : quiet_sm_func(req_ack_sm[1:0],req_quiet,ack_quiet);
assign ack_quiet_rd = ack_quiet & afx_master_cfg[0];
always @(posedge clock)
begin
req_quiet1 <= #1 (req_quiet1_in);
ack_quiet <= #1 (ack_quiet1);
req_ack_sm <= #1 (req_ack_sm_in);
end
always @(posedge pci_clk)
begin
req_quiescence <= #1 (req_quiet2);
end
sync sync_pci10(req_quiet2, pci_clk_sync, pci_clk_sync_, req_quiet1);
sync sync_afx6(ack_quiet1, gclk_sync, gclk_sync_, ack_quiescence);
// convert to use 36 bit macro REG36
wire [35:0] afx_mast_error_macroreg;
wire [25:0] wrt_decodes = wrt_decoder(pci_config_wadd,pci_config_we);
wire [3:0] hw_irl;
wire [3:0] sw_irl;
wire hw_lvl_15_int;
assign hw_lvl_15_int =((afxm_error_reg & ~mask_mast_err) |
(afxs_error_reg & ~mask_slave_err) |
(~mm_lvl15_int_l & ~mask_mm_lvl15) |
(pci_syncg_rst & ~mask_pci_rst) |
(pci_serr_reg & ~mask_serr));
assign any_intrnl_int_l = ~((afxm_error_reg & ~mask_mast_err) |
(afxs_error_reg & ~mask_slave_err) |
(~mm_lvl15_int_l & ~mask_mm_lvl15) |
(pci_syncg_rst & ~mask_pci_rst) |
(pci_serr_reg & ~mask_serr) |
unmasked_tmr_int );
wire any_lvl_15_pci ;
wire tmr_int_syncp ;
sync sync_pci11( .out (any_lvl_15_pci), .in_clk (pci_clk_sync_),
.out_clk(pci_clk_sync), .in (hw_lvl_15_int) );
sync sync_pci12( .out (tmr_int_syncp), .in_clk (pci_clk_sync_),
.out_clk(pci_clk_sync), .in (unmasked_tmr_int) );
// Note: any_xint may be better if changed to unmasked interrupts!
// Also for rev 2.0 silicon cause any_xint to go true to release standby if in slave mode!
assign any_xint = ( ~pci_sync_int0_ |~pci_sync_int1_ | ~pci_sync_int2_ | ~pci_sync_int3_
| ~pci_sync_int4_ | ~pci_sync_int5_ | ~pci_sync_int6_ | ~pci_sync_int7_
| any_lvl_15_pci | tmr_int_syncp | (pci_syncp_rst & pci_slave_mode) );
// position the bits within their assigned registers
wire [31:0] p_int_pnd;
wire [31:0] s_int_pnd;
wire [31:0] int_trg_msk;
assign s_tmr_int = decode4to16w1e(sys_intr,sys_intr_lvl);
assign p_tmr_int = decode4to16w1e(prc_intr,prc_intr_lvl);
assign a_pci_int = decode4to16w1e(pci_int[0],int_asgn_reg[3:0]);
assign b_pci_int = decode4to16w1e(pci_int[1],int_asgn_reg[7:4]);
assign c_pci_int = decode4to16w1e(pci_int[2],int_asgn_reg[11:8]);
assign d_pci_int = decode4to16w1e(pci_int[3],int_asgn_reg[15:12]);
assign e_pci_int = decode4to16w1e(pci_int[4],int_asgn_reg2[3:0]);
assign f_pci_int = decode4to16w1e(pci_int[5],int_asgn_reg2[7:4]);
assign g_pci_int = decode4to16w1e(pci_int[6],int_asgn_reg2[11:8]);
assign h_pci_int = decode4to16w1e(pci_int[7],int_asgn_reg2[15:12]);
assign tmr_ints = (s_tmr_int | p_tmr_int);
assign unmasked_tmr_int = |(~mask_hw[15:1] & tmr_ints[15:1]);
assign hw_int = (s_tmr_int | p_tmr_int | a_pci_int | b_pci_int | c_pci_int | d_pci_int
| e_pci_int | f_pci_int | g_pci_int | h_pci_int);
assign unmasked_hw_int = (~mask_hw[15:1] & hw_int[15:1]);
assign p_int_pnd = {soft_int, 1'b0, (hw_lvl_15_int | unmasked_hw_int[15]),
unmasked_hw_int[14:1], 1'b0};
assign s_int_pnd = {1'b0, afxm_error_reg, afxs_error_reg, pci_serr_reg, ~mm_lvl15_int_l,
pci_rst_reg, 10'h000, hw_int, 1'b0};
assign int_trg_msk = {mask_all, mask_mast_err, mask_slave_err, mask_serr, mask_mm_lvl15,
mask_pci_rst, 10'h000, mask_hw, 1'b0};
wire [31:0] pci_config_rdata = rd_config_mux_func(pci_config_radd, cfg_config_out, afx_config,
p_int_pnd, s_int_pnd, int_trg_msk, smbar0, msize0, pmbar0,
smbar1, msize1, pmbar1, sibar, isize, pibar,
afx_mast_error_macroreg,iotlb_cd_in_reg,iotlb_rd_in_reg,
iotlb_cd_out_reg,iotlb_rd_out_reg,iotlb_cntl_reg,
iotlb_err_address_reg,int_asgn_reg,arb_asgn_reg,
rd_sys_cntr,rd_sys_lmt,rd_prc_cntr,rd_prc_lmt,
tmr_conf_reg,discard_timer,int_output_reg,int_asgn_reg2,
sys_rst_reg);
// the following decodes are word decodes, and treat the byte pointer
// within the word as a don't care (bits 1:0 are not decoded)
wire wr_asgn_reg = wrt_decodes[21]; // decode 88
// wire wr_pci_size5 = wrt_decodes[20]; // decode 58
// wire wr_pci_size4 = wrt_decodes[19]; // decode 54
// wire wr_pci_size3 = wrt_decodes[18]; // decode 50
// wire wr_pci_size2 = wrt_decodes[17]; // decode 4c
// wire wr_pci_size1 = wrt_decodes[16]; // decode 48
// wire wr_pci_size0 = wrt_decodes[15]; // decode 44
// wire wr_pci_bar5 = wrt_decodes[8]; // decode 24
// wire wr_pci_bar4 = wrt_decodes[6]; // decode 20
// wire wr_pci_bar3 = wrt_decodes[14]; // decode 1c
// wire wr_pci_bar2 = wrt_decodes[13]; // decode 18
// wire wr_pci_bar1 = wrt_decodes[5]; // decode 14
// wire wr_pci_bar0 = wrt_decodes[4]; // decode 10
wire wr_tlb_cd_in = wrt_decodes[12]; // decode 94
wire wr_tlb_rd_in = wrt_decodes[11]; // decode 90
wire wr_tlb_cntl = wrt_decodes[10]; // decode 84
wire wr_clr_s_int = wrt_decodes[9]; // decode 80
wire wr_asgn_reg2 = wrt_decodes[8]; // decode 8c
wire wr_falcon_cfg = wrt_decodes[7]; // decode 60
wire wr_ibar = wrt_decodes[25]; // decode a8
wire wr_mbar1 = wrt_decodes[24]; // decode a4
wire wr_mbar0 = wrt_decodes[23]; // decode a0
wire wr_set_sw_int = wrt_decodes[3]; // decode 6c
wire wr_clr_sw_int = wrt_decodes[2]; // decode 68
wire wr_set_int_msk = wrt_decodes[1]; // decode 7c
wire wr_clr_int_msk = wrt_decodes[0]; // decode 78
sync sync_pci1(pci_sync_int0_, pci_clk_sync, pci_clk_sync_, pci_int_[0]);
sync sync_pci2(pci_sync_int1_, pci_clk_sync, pci_clk_sync_, pci_int_[1]);
sync sync_pci3(pci_sync_int2_, pci_clk_sync, pci_clk_sync_, pci_int_[2]);
sync sync_pci4(pci_sync_int3_, pci_clk_sync, pci_clk_sync_, pci_int_[3]);
sync sync_pci5(pci_sync_int4_, pci_clk_sync, pci_clk_sync_, pci_int_[4]);
sync sync_pci6(pci_sync_int5_, pci_clk_sync, pci_clk_sync_, pci_int_[5]);
sync sync_pci7(pci_sync_int6_, pci_clk_sync, pci_clk_sync_, pci_int_[6]);
sync sync_pci8(pci_sync_int7_, pci_clk_sync, pci_clk_sync_, pci_int_[7]);
sync sync_pci13(pci_syncp_rst, pci_clk_sync, pci_clk_sync_, ~raw_pci_rst_l);
sync sync_pci9(pci_sync_serr_, pci_clk_sync, pci_clk_sync_, pci_serr_);
sync sync_afx5(afx_sync_serr, gclk_sync, gclk_sync_, pci_serr_ff3);
sync sync_afx7(pci_syncg_rst, gclk_sync, gclk_sync_, ~raw_pci_rst_l);
wire pci_serr_ff1_in = (reset ? 1'b0 : pci_sync_serr_);
wire pci_serr_ff2_in = (reset ? 1'b0 : pci_serr_ff1_);
// qualify with being off two pci cycles before going on
wire pci_serr_ff3in = ((reset || pci_serr_reg) ? 1'b0 : (pci_serr_ff3 |
~pci_sync_serr_ & pci_serr_ff1_ & pci_serr_ff2_));
// pci serr_ holding reg
always @(posedge pci_clk)
begin
pci_serr_ff1_ <= #1 pci_serr_ff1_in ;
pci_serr_ff2_ <= #1 pci_serr_ff2_in ;
pci_serr_ff3 <= #1 pci_serr_ff3in ;
end
wire clr_lvl_15_int = wr_clr_s_int & ~pci_config_wbe[3] & pci_config_wdata[31];
wire clr_afxm_error = wr_clr_s_int & ~pci_config_wbe[3] & pci_config_wdata[30];
wire clr_afxs_error = wr_clr_s_int & ~pci_config_wbe[3] & pci_config_wdata[29];
wire clr_pci_serr = wr_clr_s_int & ~pci_config_wbe[3] & pci_config_wdata[28];
wire clr_pci_rst = wr_clr_s_int & ~pci_config_wbe[3] & pci_config_wdata[26];
wire [3:0] irl = mx_irl_func(sw_irl, hw_irl, mask_all, int_ctlr_disable, pci_int_[3:0]);
// convert to macro register REG36
// always @(posedge clock)
// begin
// if (reset)
// begin
// afx_mast_error_address_reg <= #1 32'h00000000;
// afx_mast_error_cmd_reg <= #1 4'h0;
// end
// else if (afx_mast_error && ~afxm_error_reg)
// begin
// afx_mast_error_address_reg <= #1 afx_mast_error_address;
// afx_mast_error_cmd_reg <= #1 afx_mast_error_cmd;
// end
// end
REG36 HLDREG(
.data_out (afx_mast_error_macroreg),
.clock (clock ),
.load_en (afx_mast_error ),
.data_in ({afx_mast_error_cmd,afx_mast_error_address}));
wire [31:0] iotlb_cd_in_regin;
assign iotlb_cd_in_regin[31:24] = (~pci_config_wbe[3] ? pci_config_wdata[31:24] : iotlb_cd_in_reg[31:24]);
assign iotlb_cd_in_regin[23:16] = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : iotlb_cd_in_reg[23:16]);
assign iotlb_cd_in_regin[15:8] = (~pci_config_wbe[1] ? pci_config_wdata[15:8] : iotlb_cd_in_reg[15:8]);
assign iotlb_cd_in_regin[7:0] = (~pci_config_wbe[0] ? pci_config_wdata[7:0] : iotlb_cd_in_reg[7:0]);
wire [31:0] iotlb_rd_in_regin;
assign iotlb_rd_in_regin[31:24] = (~pci_config_wbe[3] ? pci_config_wdata[31:24] : iotlb_rd_in_reg[31:24]);
assign iotlb_rd_in_regin[23:16] = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : iotlb_rd_in_reg[23:16]);
assign iotlb_rd_in_regin[15:8] = (~pci_config_wbe[1] ? pci_config_wdata[15:8] : iotlb_rd_in_reg[15:8]);
assign iotlb_rd_in_regin[7:0] = (~pci_config_wbe[0] ? pci_config_wdata[7:0] : iotlb_rd_in_reg[7:0]);
wire [7:0] iotlb_cntl_regin;
assign iotlb_cntl_regin[7:0] = (~pci_config_wbe[0] ? pci_config_wdata[7:0] : iotlb_cntl_reg[7:0]);
wire [14:0] arb_asgn_regin;
wire [15:0] int_asgn_regin;
assign arb_asgn_regin[14:8] = (~pci_config_wbe[3] ? pci_config_wdata[30:24] : arb_asgn_reg[14:8]);
assign arb_asgn_regin[7:0] = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : arb_asgn_reg[7:0]);
assign int_asgn_regin[15:8] = (~pci_config_wbe[1] ? pci_config_wdata[15:8] : int_asgn_reg[15:8]);
assign int_asgn_regin[7:0] = (~pci_config_wbe[0] ? pci_config_wdata[7:0] : int_asgn_reg[7:0]);
wire [7:0] int_output_regin;
assign int_output_regin[7:0] = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : int_output_reg[7:0]);
wire [15:0] int_asgn_reg2in;
assign int_asgn_reg2in[15:8] = (~pci_config_wbe[1] ? pci_config_wdata[15:8] : int_asgn_reg2[15:8]);
assign int_asgn_reg2in[7:0] = (~pci_config_wbe[0] ? pci_config_wdata[7:0] : int_asgn_reg2[7:0]);
// IOTLB registers and translation miss error register
always @(posedge clock)
begin
if (reset)
begin
iotlb_cd_in_reg <= #1 32'h00000000;
iotlb_rd_in_reg <= #1 32'h00000000;
iotlb_cntl_reg <= #1 8'h00;
int_asgn_reg <= #1 16'h7532;
arb_asgn_reg <= #1 15'h4688; // 100 011 010 001 000
// 0100 0110 1000 1000 h'4688
int_output_reg <= #1 8'h00;
int_asgn_reg2 <= #1 16'h0000;
end
else if (wr_tlb_cd_in)
begin
iotlb_cd_in_reg[31:24] <= #1 iotlb_cd_in_regin[31:24];
iotlb_cd_in_reg[23:16] <= #1 iotlb_cd_in_regin[23:16];
iotlb_cd_in_reg[15:8] <= #1 iotlb_cd_in_regin[15:8];
iotlb_cd_in_reg[7:0] <= #1 iotlb_cd_in_regin[7:0];
end
else if (wr_tlb_rd_in)
begin
iotlb_rd_in_reg[31:24] <= #1 iotlb_rd_in_regin[31:24];
iotlb_rd_in_reg[23:16] <= #1 iotlb_rd_in_regin[23:16];
iotlb_rd_in_reg[15:8] <= #1 iotlb_rd_in_regin[15:8];
iotlb_rd_in_reg[7:0] <= #1 iotlb_rd_in_regin[7:0];
end
else if (wr_tlb_cntl)
begin
iotlb_cntl_reg[7:0] <= #1 iotlb_cntl_regin[7:0];
end
else if (wr_asgn_reg)
begin
arb_asgn_reg[14:8] <= #1 arb_asgn_regin[14:8];
arb_asgn_reg[7:0] <= #1 arb_asgn_regin[7:0];
int_asgn_reg[15:8] <= #1 int_asgn_regin[15:8];
int_asgn_reg[7:0] <= #1 int_asgn_regin[7:0];
end
else if (wr_asgn_reg2)
begin
int_output_reg[7:0] <= #1 int_output_regin[7:0];
int_asgn_reg2[15:8] <= #1 int_asgn_reg2in[15:8];
int_asgn_reg2[7:0] <= #1 int_asgn_reg2in[7:0];
end
end
always @(posedge clock)
begin
if (reset)
iotlb_err_address_reg <= #1 32'h00000000;
else if (iotlb_err && ~afxs_error_reg)
iotlb_err_address_reg <= #1 iotlb_err_address;
end
wire iotlb_cntl_wrt = wr_tlb_cntl;
wire afxm_error_regin = (reset || clr_lvl_15_int || clr_afxm_error) ? 1'b0
: (afxm_error_reg | afx_mast_error);
wire afxs_error_regin = (reset || clr_lvl_15_int || clr_afxs_error) ? 1'b0
: (afxs_error_reg | afx_slave_error | iotlb_err);
wire pci_serr_regin = (reset || clr_lvl_15_int || clr_pci_serr) ? 1'b0
: (pci_serr_reg | afx_sync_serr);
wire pci_rst_regin = (reset || clr_lvl_15_int ||
(clr_pci_rst & ~pci_syncg_rst & pci_slave_mode)) ? 1'b0
: (pci_rst_reg | pci_syncg_rst);
wire [7:6] afx_slave_cfgin = (~pci_config_wbe[0] ? pci_config_wdata[7:6] : afx_slave_cfg);
wire pcim_big_endianin = (~pci_config_wbe[0] ? pci_config_wdata[2] : pcim_big_endian);
wire [2:0] pci_idsel_cfgin = (~pci_config_wbe[1] ? pci_config_wdata[10:8] : pci_idsel_cfg);
wire [3:0] afx_master_cfgin = (~pci_config_wbe[2] ? pci_config_wdata[19:16] : afx_master_cfg);
wire [4:0] pci_arb_cfgin = (~pci_config_wbe[3] ? pci_config_wdata[28:24] : pci_arb_cfg);
wire [3:0] smbar0in = (~pci_config_wbe[0] ? pci_config_wdata[3:0] : smbar0) ;
wire [3:0] msize0in = (~pci_config_wbe[1] ? pci_config_wdata[11:8] : msize0) ;
wire [7:0] pmbar0in = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : pmbar0) ;
wire [3:0] smbar1in = (~pci_config_wbe[0] ? pci_config_wdata[3:0] : smbar1) ;
wire [3:0] msize1in = (~pci_config_wbe[1] ? pci_config_wdata[11:8] : msize1) ;
wire [7:0] pmbar1in = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : pmbar1);
wire [3:0] sibarin = (~pci_config_wbe[0] ? pci_config_wdata[3:0] : sibar) ;
wire [3:0] isizein = (~pci_config_wbe[1] ? pci_config_wdata[11:8] : isize) ;
wire [7:0] pibarin = (~pci_config_wbe[2] ? pci_config_wdata[23:16] : pibar) ;
wire [15:1] soft_intin1;
wire [15:1] soft_intin2;
wire [15:0] discard_timerin;
assign soft_intin1[15:8] = (~pci_config_wbe[3] ? (soft_int[15:8] | pci_config_wdata[31:24]) : soft_int[15:8]);
assign soft_intin1[7:1] = (~pci_config_wbe[2] ? (soft_int[7:1] | pci_config_wdata[23:17]) : soft_int[7:1]);
assign soft_intin2[15:8] = (~pci_config_wbe[3] ? (soft_int[15:8] & ~pci_config_wdata[31:24]) : soft_int[15:8]);
assign soft_intin2[7:1] = (~pci_config_wbe[2] ? (soft_int[7:1] & ~pci_config_wdata[23:17]) : soft_int[7:1]);
assign discard_timerin[15:8] = (~pci_config_wbe[1] ? pci_config_wdata[15:8] : discard_timer[15:8]);
assign discard_timerin[7:0] = (~pci_config_wbe[0] ? pci_config_wdata[7:0] : discard_timer[7:0]);
wire mask_allin1 = (~pci_config_wbe[3] ? (mask_all | pci_config_wdata[31]) : mask_all);
wire mask_mast_errin1 = (~pci_config_wbe[3] ? (mask_mast_err | pci_config_wdata[30]) : mask_mast_err);
wire mask_slave_errin1 = (~pci_config_wbe[3] ? (mask_slave_err | pci_config_wdata[29]) : mask_slave_err);
wire mask_serrin1 = (~pci_config_wbe[3] ? (mask_serr | pci_config_wdata[28]) : mask_serr);
wire mask_mm_lvl15in1 = (~pci_config_wbe[3] ? (mask_mm_lvl15 | pci_config_wdata[27]) : mask_mm_lvl15);
wire mask_pci_rstin1 = (~pci_config_wbe[3] ? (mask_pci_rst | pci_config_wdata[26]) : mask_pci_rst);
wire [15:1] mask_hwin1;
assign mask_hwin1[15:8] = (~pci_config_wbe[1] ? (mask_hw[15:8] | pci_config_wdata[15:8]) : mask_hw[15:8]);
assign mask_hwin1[7:1] = (~pci_config_wbe[0] ? (mask_hw[7:1] | pci_config_wdata[7:1]) : mask_hw[7:1]);
wire mask_allin2 = (~pci_config_wbe[3] ? (mask_all & ~pci_config_wdata[31]) : mask_all);
wire mask_mast_errin2 = (~pci_config_wbe[3] ? (mask_mast_err & ~pci_config_wdata[30]) : mask_mast_err);
wire mask_slave_errin2 = (~pci_config_wbe[3] ? (mask_slave_err & ~pci_config_wdata[29]) : mask_slave_err);
wire mask_serrin2 = (~pci_config_wbe[3] ? (mask_serr & ~pci_config_wdata[28]) : mask_serr);
wire mask_mm_lvl15in2 = (~pci_config_wbe[3] ? (mask_mm_lvl15 & ~pci_config_wdata[27]) : mask_mm_lvl15);
wire mask_pci_rstin2 = (~pci_config_wbe[3] ? (mask_pci_rst & ~pci_config_wdata[26]) : mask_pci_rst);
wire [15:1] mask_hwin2;
assign mask_hwin2[15:8] = (~pci_config_wbe[1] ? (mask_hw[15:8] & ~pci_config_wdata[15:8]) : mask_hw[15:8]);
assign mask_hwin2[7:1] = (~pci_config_wbe[0] ? (mask_hw[7:1] & ~pci_config_wdata[7:1]) : mask_hw[7:1]);
// Software Interrupts and System Mask
always @(posedge clock)
begin
afxm_error_reg <= #1 afxm_error_regin;
afxs_error_reg <= #1 afxs_error_regin;
pci_serr_reg <= #1 pci_serr_regin;
pci_rst_reg <= #1 pci_rst_regin;
if (reset)
begin
soft_int <= #1 15'h0000;
mask_all <= #1 1'b1;
mask_mast_err <= #1 1'b1;
mask_slave_err <= #1 1'b1;
mask_serr <= #1 1'b1;
mask_mm_lvl15 <= #1 1'b1;
mask_pci_rst <= #1 1'b1;
mask_hw <= #1 15'h7fff;
afx_slave_cfg <= #1 2'b00;
pcim_big_endian <= #1 1'b0;
pci_idsel_cfg <= #1 3'b000;
afx_master_cfg <= #1 4'h0;
pci_arb_cfg <= #1 {2'b00,pci_slave_mode,2'b00};
smbar0 <= #1 4'b0000;
msize0 <= #1 4'b0000;
pmbar0 <= #1 8'h00;
smbar1 <= #1 4'b0000;
msize1 <= #1 4'b0000;
pmbar1 <= #1 8'h00;
sibar <= #1 4'b0000;
isize <= #1 4'b0000;
pibar <= #1 8'h00;
isabar <= #1 4'b0000;
discard_timer <= #1 16'h7fff;
end
else if (wr_falcon_cfg)
begin
afx_slave_cfg <= #1 afx_slave_cfgin;
pcim_big_endian <= #1 pcim_big_endianin;
pci_idsel_cfg <= #1 pci_idsel_cfgin;
afx_master_cfg <= #1 afx_master_cfgin;
pci_arb_cfg <= #1 pci_arb_cfgin;
end
else if (wr_ibar)
begin
sibar <= #1 sibarin;
isize <= #1 isizein;
pibar <= #1 pibarin;
end
else if (wr_mbar0)
begin
smbar0 <= #1 smbar0in;
msize0 <= #1 msize0in;
pmbar0 <= #1 pmbar0in;
end
else if (wr_mbar1)
begin
smbar1 <= #1 smbar1in;
msize1 <= #1 msize1in;
pmbar1 <= #1 pmbar1in;
end
else if (wr_set_sw_int)
begin
soft_int[15:8] <= #1 soft_intin1[15:8];
soft_int[7:1] <= #1 soft_intin1[7:1];
end
else if (wr_clr_sw_int)
begin
soft_int[15:8] <= #1 soft_intin2[15:8];
soft_int[7:1] <= #1 soft_intin2[7:1];
discard_timer[15:8] <= #1 discard_timerin[15:8];
discard_timer[7:0] <= #1 discard_timerin[7:0];
end
else if (wr_set_int_msk)
begin
mask_all <= #1 mask_allin1;
mask_mast_err <= #1 mask_mast_errin1;
mask_slave_err <= #1 mask_slave_errin1;
mask_serr <= #1 mask_serrin1;
mask_mm_lvl15 <= #1 mask_mm_lvl15in1;
mask_pci_rst <= #1 mask_pci_rstin1;
mask_hw[15:8] <= #1 mask_hwin1[15:8];
mask_hw[7:1] <= #1 mask_hwin1[7:1];
end
else if (wr_clr_int_msk)
begin
mask_all <= #1 mask_allin2;
mask_mast_err <= #1 mask_mast_errin2;
mask_slave_err <= #1 mask_slave_errin2;
mask_serr <= #1 mask_serrin2;
mask_mm_lvl15 <= #1 mask_mm_lvl15in2;
mask_pci_rst <= #1 mask_pci_rstin2;
mask_hw[15:8] <= #1 mask_hwin2[15:8];
mask_hw[7:1] <= #1 mask_hwin2[7:1];
end
end
assign sw_irl[3:0] = sw_irl_func(soft_int);
assign hw_irl[3:0] = hw_irl_func(hw_int, mask_hw, hw_lvl_15_int);
// function for mx_irl_func
// includes a bypass all the interrupt controller logic and allows
// the resynced pci signals to be routed to the irl_in inputs to the V8 sparc.
function [3:0] mx_irl_func;
input [3:0] sw_irl;
input [3:0] hw_irl;
input mask_all;
input int_ctlr_disable;
input [3:0] pci_int_;
begin
if (int_ctlr_disable == 1'b1)
mx_irl_func = ~pci_int_[3:0] ;
else if (mask_all == 1'b1)
mx_irl_func = 4'h0;
else if (sw_irl >= hw_irl)
mx_irl_func = sw_irl;
else mx_irl_func = hw_irl;
end
endfunction
// function for sw_irl
function [3:0] sw_irl_func;
input [15:1] soft_int;
begin
if (soft_int[15] == 1'b1) sw_irl_func = 4'hf;
else if (soft_int[14] == 1'b1) sw_irl_func = 4'he;
else if (soft_int[13] == 1'b1) sw_irl_func = 4'hd;
else if (soft_int[12] == 1'b1) sw_irl_func = 4'hc;
else if (soft_int[11] == 1'b1) sw_irl_func = 4'hb;
else if (soft_int[10] == 1'b1) sw_irl_func = 4'ha;
else if (soft_int[9] == 1'b1) sw_irl_func = 4'h9;
else if (soft_int[8] == 1'b1) sw_irl_func = 4'h8;
else if (soft_int[7] == 1'b1) sw_irl_func = 4'h7;
else if (soft_int[6] == 1'b1) sw_irl_func = 4'h6;
else if (soft_int[5] == 1'b1) sw_irl_func = 4'h5;
else if (soft_int[4] == 1'b1) sw_irl_func = 4'h4;
else if (soft_int[3] == 1'b1) sw_irl_func = 4'h3;
else if (soft_int[2] == 1'b1) sw_irl_func = 4'h2;
else if (soft_int[1] == 1'b1) sw_irl_func = 4'h1;
else sw_irl_func = 4'h0;
end
endfunction
// function for hw_irl
function [3:0] hw_irl_func;
input [15:1] hw_int;
input [15:1] mask_hw;
input hw_lvl_15_int;
begin
if (hw_lvl_15_int == 1'b1) hw_irl_func = 4'hf;
else if ((hw_int[15] == 1'b1) && (mask_hw[15] == 1'b0)) hw_irl_func = 4'hf;
else if ((hw_int[14] == 1'b1) && (mask_hw[14] == 1'b0)) hw_irl_func = 4'he;
else if ((hw_int[13] == 1'b1) && (mask_hw[13] == 1'b0)) hw_irl_func = 4'hd;
else if ((hw_int[12] == 1'b1) && (mask_hw[12] == 1'b0)) hw_irl_func = 4'hc;
else if ((hw_int[11] == 1'b1) && (mask_hw[11] == 1'b0)) hw_irl_func = 4'hb;
else if ((hw_int[10] == 1'b1) && (mask_hw[10] == 1'b0)) hw_irl_func = 4'ha;
else if ((hw_int[9] == 1'b1) && (mask_hw[9] == 1'b0)) hw_irl_func = 4'h9;
else if ((hw_int[8] == 1'b1) && (mask_hw[8] == 1'b0)) hw_irl_func = 4'h8;
else if ((hw_int[7] == 1'b1) && (mask_hw[7] == 1'b0)) hw_irl_func = 4'h7;
else if ((hw_int[6] == 1'b1) && (mask_hw[6] == 1'b0)) hw_irl_func = 4'h6;
else if ((hw_int[5] == 1'b1) && (mask_hw[5] == 1'b0)) hw_irl_func = 4'h5;
else if ((hw_int[4] == 1'b1) && (mask_hw[4] == 1'b0)) hw_irl_func = 4'h4;
else if ((hw_int[3] == 1'b1) && (mask_hw[3] == 1'b0)) hw_irl_func = 4'h3;
else if ((hw_int[2] == 1'b1) && (mask_hw[2] == 1'b0)) hw_irl_func = 4'h2;
else if ((hw_int[1] == 1'b1) && (mask_hw[1] == 1'b0)) hw_irl_func = 4'h1;
else hw_irl_func = 4'h0;
end
endfunction
// read multiplexer for config registers (function)
function [31:0] rd_config_mux_func;
input [7:0] pci_config_radd;
input [31:0] cfg_config_out;
input [31:0] afx_config;
input [31:0] p_int_pnd;
input [31:0] s_int_pnd;
input [31:0] int_trg_msk;
input [3:0] smbar0;
input [3:0] msize0;
input [7:0] pmbar0;
input [3:0] smbar1;
input [3:0] msize1;
input [7:0] pmbar1;
input [3:0] sibar;
input [3:0] isize;
input [7:0] pibar;
// input [3:0] isabar;
input [35:0] afx_mast_error_macroreg;
input [31:0] iotlb_cd_in_reg;
input [31:0] iotlb_rd_in_reg;
input [31:0] iotlb_cd_out_reg;
input [31:0] iotlb_rd_out_reg;
input [7:0] iotlb_cntl_reg;
input [31:0] iotlb_err_address_reg;
input [15:0] int_asgn_reg;
input [24:0] arb_asgn_reg;
input [31:0] rd_sys_cntr;
input [31:0] rd_sys_lmt;
input [31:0] rd_prc_cntr;
input [31:0] rd_prc_lmt;
input [23:0] tmr_conf_reg;
input [15:0] discard_timer;
input [7:0] int_output_reg;
input [15:0] int_asgn_reg2;
input [7:0] sys_rst_reg;
begin
casex(pci_config_radd)
8'b101000xx: rd_config_mux_func = { 8'h00,pmbar0,4'h0,msize0,4'h0,smbar0}; // decode a0
8'b101001xx: rd_config_mux_func = { 8'h00,pmbar1,4'h0,msize1,4'h0,smbar1}; // decode a4
8'b101010xx: rd_config_mux_func = { 8'h00,pibar,4'h0,isize,4'h0,sibar}; // decode a8
8'b100011xx: rd_config_mux_func = { 8'h00,int_output_reg,int_asgn_reg2}; // decode 8c
8'b011000xx: rd_config_mux_func = {afx_config}; // decode 60
8'b011001xx: rd_config_mux_func = {p_int_pnd}; // decode 64
8'b011100xx: rd_config_mux_func = {s_int_pnd}; // decode 70
8'b011101xx: rd_config_mux_func = {int_trg_msk}; // decode 74
8'b110010xx: rd_config_mux_func =
{afx_mast_error_macroreg[7:0], afx_mast_error_macroreg[15:8],
afx_mast_error_macroreg[23:16],afx_mast_error_macroreg[31:24]}; // decode c8
8'b100001xx: rd_config_mux_func = { 24'h000000,iotlb_cntl_reg }; // decode 84
8'b100100xx: rd_config_mux_func = iotlb_rd_in_reg; // decode 90
8'b100101xx: rd_config_mux_func = iotlb_cd_in_reg; // decode 94
8'b100110xx: rd_config_mux_func = iotlb_rd_out_reg; // decode 98
8'b100111xx: rd_config_mux_func = iotlb_cd_out_reg; // decode 9c
8'b110011xx: rd_config_mux_func = iotlb_err_address_reg; // decode cc
8'b100010xx: rd_config_mux_func = { 1'b0,arb_asgn_reg,int_asgn_reg}; // decode 88
8'b101011xx: rd_config_mux_func = rd_prc_lmt; // decode ac
8'b101100xx: rd_config_mux_func = rd_prc_cntr; // decode b0
8'b101110xx: rd_config_mux_func = rd_sys_lmt; // decode b8
8'b101111xx: rd_config_mux_func = rd_sys_cntr; // decode bc
8'b011010xx: rd_config_mux_func = {16'h0000,discard_timer}; // decode 68
8'b110001xx: rd_config_mux_func =
{4'h0,afx_mast_error_macroreg[35:32],tmr_conf_reg}; // decode c4
8'b110100xx: rd_config_mux_func = { 24'h000000,sys_rst_reg }; // decode d0
default: rd_config_mux_func = {cfg_config_out}; // all other decodes to core.
endcase
end
endfunction
// write falcon interrupt register decoder
function [25:0] wrt_decoder;
input [7:0] pci_config_wadd;
input pci_config_we;
begin
casex({pci_config_wadd, pci_config_we})
9'b011110xx1: wrt_decoder = 26'h0000001; // decode 78, 79, 7a, or 7b
9'b011111xx1: wrt_decoder = 26'h0000002; // decode 7c, 7d, 7e, or 7f
9'b011010xx1: wrt_decoder = 26'h0000004; // decode 68, 69, 6a, or 6b
9'b011011xx1: wrt_decoder = 26'h0000008; // decode 6c, 6d, 6e, or 6f
9'b000100xx1: wrt_decoder = 26'h0000010; // decode 10, 11, 12, or 13
9'b000101xx1: wrt_decoder = 26'h0000020; // decode 14, 15, 16, or 17
9'b001000xx1: wrt_decoder = 26'h0000040; // decode 20, 21, 22, or 23
9'b011000xx1: wrt_decoder = 26'h0000080; // decode 60, 61, 62, or 63
9'b100011xx1: wrt_decoder = 26'h0000100; // decode 8c, 8d, 8e, or 8f
9'b100000xx1: wrt_decoder = 26'h0000200; // decode 80, 81, 82, or 83
9'b100001xx1: wrt_decoder = 26'h0000400; // decode 84, 85, 86, or 87
9'b100100xx1: wrt_decoder = 26'h0000800; // decode 90, 91, 92, or 93
9'b100101xx1: wrt_decoder = 26'h0001000; // decode 94, 95, 96, or 97
9'b000110xx1: wrt_decoder = 26'h0002000; // decode 18, 19, 1a, or 1b
9'b000111xx1: wrt_decoder = 26'h0004000; // decode 1c, 1d, 1e, or 1f
9'b010001xx1: wrt_decoder = 26'h0008000; // decode 44, 45, 46, or 47
9'b010010xx1: wrt_decoder = 26'h0010000; // decode 48, 49, 4a, or 4b
9'b010011xx1: wrt_decoder = 26'h0020000; // decode 4c, 4d, 4e, or 4f
9'b010100xx1: wrt_decoder = 26'h0040000; // decode 50, 51, 52, or 53
9'b010101xx1: wrt_decoder = 26'h0080000; // decode 54, 55, 56, or 57
9'b010110xx1: wrt_decoder = 26'h0100000; // decode 58, 59, 5a, or 5b
9'b100010xx1: wrt_decoder = 26'h0200000; // decode 88, 89, 8a, or 8b
9'b100011xx1: wrt_decoder = 26'h0400000; // decode 8c, 8d, 8e, or 8f
9'b101000xx1: wrt_decoder = 26'h0800000; // decode a0, a1, a2, or a3
9'b101001xx1: wrt_decoder = 26'h1000000; // decode a4, aa, a6, or a7
9'b101010xx1: wrt_decoder = 26'h2000000; // decode a8, a9, aa, or ab
default: wrt_decoder = 26'h0000000;
endcase
end
endfunction
function [15:0] decode4to16w1e;
input enable;
input [3:0] code;
begin
casex({enable,code})
5'b0xxxx: decode4to16w1e = 15'h0000;
5'b10000: decode4to16w1e = 15'h0000;
5'b10001: decode4to16w1e = 15'h0001;
5'b10010: decode4to16w1e = 15'h0002;
5'b10011: decode4to16w1e = 15'h0004;
5'b10100: decode4to16w1e = 15'h0008;
5'b10101: decode4to16w1e = 15'h0010;
5'b10110: decode4to16w1e = 15'h0020;
5'b10111: decode4to16w1e = 15'h0040;
5'b11000: decode4to16w1e = 15'h0080;
5'b11001: decode4to16w1e = 15'h0100;
| This page: |
Created: | Thu Aug 19 12:00:23 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/interrupts/rtl/interrupts.v
|