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/******************************************************************************/
// @(#)rl_clk_stop.v 1.30 9/14/93
// Clock stop/start logic
![[Up: misc clk_stop]](v2html-up.gif)
module rl_clk_stop
(
gclk_phase_bit1,
reset_out,
mm_hold_rst,
standby_dsbl_sysclk_a1,
standby_dsbl_tlb,
standby_req,
standby,
pcic_idle,
memif_idle,
ic_standby_f,
dc_standby_w,
terminal_count_l,
ext_event_l,
int_event_l,
mm_event,
iu_event,
rcc_clk,
gclk_phase_late_a1,
gclk_1st_phase,
free_phase_late_a1,
rcc_rst_l,
rs_stop_even,
rs_dsbl_clocks,
start,
stop,
stop_after_0,
stop_after_1,
stop_after_2,
stop_after_3,
stop_after_4,
div_ctl,
first_phi,
last_phi,
next2last_phi,
reset_nonwd,
hold_count,
rcc_rst_even_l,
ss_scan_mode,
ss_scan_in,
ss_scan_out,
logic_0,
logic_1
) ;
// Reset state machine decode - asserts reset and/or reset_iu
output gclk_phase_bit1; // gclk_phase[1]. export for 595 bug fix
input reset_out ;
input mm_hold_rst ;
output hold_count ;
output rcc_rst_even_l ;
input standby ;
output standby_req ;
input pcic_idle ;
input memif_idle ;
input ic_standby_f ;
input dc_standby_w ;
output standby_dsbl_sysclk_a1 ;
output standby_dsbl_tlb ;
input terminal_count_l ;
input ext_event_l ;
output int_event_l ;
input mm_event ;
input iu_event ;
input rcc_clk ; // 40 MHz, with scan, not inhibited by reset
input [2:0] free_phase_late_a1 ;
input [1:0] gclk_phase_late_a1 ;
output gclk_1st_phase ;
// rcc_clk-clocked phase decodes
output first_phi ;
output last_phi ;
output next2last_phi ;
// 20-MHz-synchronized input_reset, ANDed with ~tcen_sync
input rcc_rst_l ;
input rs_stop_even ; // Clock stop signal from reset state machine
input rs_dsbl_clocks ; // Clock inhibit signal from reset state machine
input reset_nonwd ;
output stop ; // Stop at the end of this phase (if possible)
// These signals must change only on sbclk posedge if
// clocks are running; i.e. they are controlled either by
// scan-in or by sbclk-clocked FFs.
output start ;
output stop_after_0 ; // Stop at the end of phase 0
output stop_after_1 ; // Stop at the end of phase 1
output stop_after_2 ; // Stop at the end of phase 2
output stop_after_3 ; // Stop at the end of phase 3
output stop_after_4 ; // Stop at the end of phase 4
input [1:0] div_ctl ;
input ss_scan_mode ;
input ss_scan_in ;
output ss_scan_out ;
output logic_0, logic_1 ; // Constants, brought up to ssparc level.
// Note: all FF scan-in inputs will be left unconnected. These nets
// will be automatically scan-stitched by back-end tools, and
// explicitly scan-stitched (by pseudo-continuous assigns)
// for stand-alone clk/misc simulation.
// wire div_by_2 = (div_ctl[1:0] == 2'b00) ;
wire div_by_6 = (div_ctl[1:0] == 2'b00) ;
wire div_by_3 = (div_ctl[1:0] == 2'b01) ;
wire div_by_4 = (div_ctl[1:0] == 2'b10) ;
wire div_by_5 = (div_ctl[1:0] == 2'b11) ;
wire [2:0] phi ;
Mflipflop_s_3 phi_reg(phi[2:0], free_phase_late_a1[2:0],
ss_scan_mode, /*scan-in*/, rcc_clk) ;
// Add the following two enables which can only be turned on with
// scan in the misc block. These two flops used to be in the processor core,
// but // we cannot scan them with jtag in the core. The enables in mdecode.v
// and rl_mmu_regs.v are hardwired to a 1, so that these flops can take
// their place.
wire enable_event;
wire nenable_event = enable_event & ~reset_out;
Mflipflop_1 event_reg_1(enable_event,nenable_event,rcc_clk,1'b0) ;
wire enbl_scan_bp;
wire nenbl_scan_bp = enbl_scan_bp & ~reset_out;
Mflipflop_1 event_reg_2(enbl_scan_bp,nenbl_scan_bp,rcc_clk,1'b0) ;
// mm_event_gate replaces all internal useages of mm_event
// iu_event_gate replaces all internal useages of iu_event
wire mm_event_gate = enbl_scan_bp & mm_event;
wire iu_event_gate = enable_event & iu_event;
// Modified this correctly for no sbus clock present - 6/25/96
// Further modification since now free_phase_late_a1 is PCI controlled 7/12/96
wire first_phi = (phi[2:0]==3'h0) ;
// wire last_phi_a2 = (
// (div_by_2 & (phi[0]==1'h1))
// //| (div_by_3 & (phi[1:0]==2'h0))
// //| (div_by_4 & (phi[1:0]==2'h1))
// //| (div_by_5 & (phi[1:0]==2'h2))
// | (div_by_3 & (phi[1:0]==2'h1))
// | (div_by_4 & (phi[1:0]==2'h2))
// | (div_by_5 & (phi[1:0]==2'h3))
// ) ;
wire last_phi_a2 = (
// (div_by_2 & (phi[0]==1'h0))
| (div_by_3 & (phi[1:0]==2'h0))
| (div_by_4 & (phi[1:0]==2'h1))
| (div_by_5 & (phi[1:0]==2'h2))
| (div_by_6 & (phi[1:0]==2'h3))
) ;
Mflipflop_s lp_reg(last_phi, next2last_phi,
ss_scan_mode, /*scan-in*/, rcc_clk) ;
Mflipflop_s n2lp_reg(next2last_phi, last_phi_a2,
ss_scan_mode, /*scan-in*/, rcc_clk) ;
// This is used to enable flipflops which are logically part
// of the External Clock Counter. These are clocked only
// at the end of an SBus cycle, are held while int_event
// is not asserted in stop_int_to_ext mode, and are inhibited
// during reset transitions.
wire count_int_events, int_event ; // (forward)
wire hold_count_cycle = (~int_event & count_int_events) | rs_dsbl_clocks ;
wire hold_count = ~last_phi | hold_count_cycle ;
// Use this to reset FFs which must transition only on sbclk edges.
wire rcc_rst_even_l = ~(~rcc_rst_l & last_phi) ;
// Latch the external event input (to simplify setup spec of this pin)
// ext_event_sb1 will be asserted when the XCC count is 0.
wire ext_event = ~ext_event_l | ~terminal_count_l ;
Mflipflop_srh ext_ev1_ff(ext_event_sb1, ext_event,
ss_scan_mode, /*scan-in*/, hold_count,
rcc_rst_even_l, rcc_clk) ;
// Stage it one more sbus cycle for use in stop_int_to_ext
// ext_event_sb2 will be asserted when the XCC count is 1.
Mflipflop_srh ext_ev2_ff(ext_event_sb2, ext_event_sb1,
ss_scan_mode, /*scan-in*/, hold_count,
rcc_rst_even_l, rcc_clk) ;
//--------------------------------------------------------------------
// Scan-only FFs. These are all reset by rcc_rst_l, thus forcing clocks
// on; if a service processor is installed, clocks will be stopped
// when reset_sync is deasserted, so that scantool can set them to
// whatever it wants.
// Stop on external event.
Mflipflop_sr sxe_ff (stop_on_ext_event, stop_on_ext_event,
ss_scan_mode, /*scan-in*/, rcc_rst_even_l, rcc_clk) ;
// Wait this many additional rcc_clk cycles after reaching ref_phi
// when stopping on external event. This must be less than the
// divide ratio.
wire [2:0] extra_cycles ;
Mflipflop_sr_3 xc_ff (extra_cycles[2:0], extra_cycles[2:0],
ss_scan_mode, /*scan-in*/, rcc_rst_even_l, rcc_clk) ;
// In this mode, clocks are counted after an internal event that
// would normally have stopped clocks.
Mflipflop_sr six_ff (stop_int_to_ext, stop_int_to_ext,
ss_scan_mode, /*scan-in*/, rcc_rst_even_l, rcc_clk) ;
// Stop on internal event.
Mflipflop_sr sie_ff (stop_on_int_event, stop_on_int_event,
ss_scan_mode, /*scan-in*/, rcc_rst_even_l, rcc_clk) ;
// Stop on Nth internal event
Mflipflop_sr sne_ff (stop_nth_event, stop_nth_event,
ss_scan_mode, /*scan-in*/, rcc_rst_even_l, rcc_clk) ;
// This is a copy of an External Clock Counter control bit
assign count_int_events = stop_int_to_ext | stop_nth_event ;
//--------------------------------------------------------------------
// This one clears on every rcc_clk pulse. Scanning a 1 into both
// start and stop_clocks (while clocks are stopped) will
// cause a single-step.
Mflipflop_s start_ff(start, logic_0,
ss_scan_mode, /*scan-in*/, rcc_clk) ;
// Compute the phi in which to stop clocks in response to an ext_event
// input. It is equal to (ext_stop_sum MOD divide_ratio).
// Take advantage of the fact that neither phi nor extra_cycles is
// greater than or equal to the divide ratio.
wire [3:0] ext_stop_sum =
{(phi[2]&extra_cycles[2]), (phi[2:0]+extra_cycles[2:0])} ;
wire [3:0] radix = {
1'b0,
(div_by_4 | div_by_5 | div_by_6),
(div_by_6 | div_by_3),
(div_by_3 | div_by_5)
} ;
// Test to see if we've wrapped around to the next SBus cycle
wire extra_sbus_cycle_a1 = (ext_stop_sum[3:0] >= radix[3:0]) ;
wire [2:0] ext_stop_phi, ext_stop_phi_a1 ;
assign ext_stop_phi_a1[2:0] =
extra_sbus_cycle_a1 ? (ext_stop_sum[2:0]-radix[2:0])
: ext_stop_sum[2:0] ;
// Latch ext_stop_sum and extra_sbus_cycle on the first internal event in
// stop_int_to_ext mode; also, latch them on the first sbclk in
// stop_on_ext_event mode (software must scan the special value '111'
// into ext_stop_phi to indicate that it is uninitialized).
wire int_event_detected, int_event_midcycle ; // (forward)
// This is asserted by the internal event which triggers
// the counting in stop_int_to_ext mode.
wire int_to_ext_event =
(stop_int_to_ext & int_event_detected
& ~int_event_midcycle & ~int_event) ;
// Clock enable for ext_stop_phi/extra_sbus_cycle
wire enbl_ext_stop_phi =
int_to_ext_event
// Initialize ext_stop_phi/extra_sbus_cycle on first clock
// after a scan-in. Scan software uses '111' as a special
// code for 'uninitialized'.
| (stop_on_ext_event & (ext_stop_phi[2:0] == 3'b111))
;
Mflipflop_srh_3 xsp_ff (ext_stop_phi[2:0], ext_stop_phi_a1[2:0],
ss_scan_mode, /*scan-in*/,
~enbl_ext_stop_phi, rcc_rst_even_l, rcc_clk) ;
Mflipflop_srh xsc_ff (extra_sbus_cycle, extra_sbus_cycle_a1,
ss_scan_mode, /*scan-in*/,
~enbl_ext_stop_phi, rcc_rst_even_l, rcc_clk) ;
wire int_event_a1 ; // (forward)
// Active in the sbclk cycle before one of the stop_after_* outputs is
// asserted.
wire ext_event_stop_a1 =
(stop_on_ext_event
// rs_dsbl_clocks is here because int_event_a1 won't move into
// int_event if rs_dsbl_clocks is asserted - see hold_int_event
| (stop_int_to_ext & (int_event | (int_event_a1&~rs_dsbl_clocks))))
// Dependency on hold_count_cycle, similiar to rs_dsbl_clocks
// dependency above.
& (hold_count_cycle
? (extra_sbus_cycle ? ext_event_sb2 : ext_event_sb1)
: (extra_sbus_cycle ? ext_event_sb1 : ext_event)
)
;
// Register the stop_after signals to avoid long paths into clk_cntl.
// Set them all to stop clocks unconditionally.
// Note: these signals are ignored (in clk_cntl) when jtag_trst_l is
// asserted.
//
// Note: the stop_after_* signals are meaningless until the cycle *after*
// enbl_ext_stop_phi has been asserted, since they are based on
// uninitialized values in ext_stop_phi and extra_sbus_cycle. To
// prevent problems, we must not allow ext_event_stop_a1 to be
// asserted in the same cycle as enbl_ext_stop_phi if this cycle is
// a last_phi cycle. These rules will assure it:
//
// * For the 'Issue N Clocks' algorithm (stop_ext_event), N must
// be greater than (radix+1). This prevents the situation
// where we try to issue (radix+1) clocks when stopped in
// last_phi: stop_after_(last_phi) bit should be set on the
// first clock in order for this to work, but ext_stop_phi is
// not yet valid in that cycle (it's 7, and enbl_ext_stop_phi
// is asserted in that cycle); clocks never stop.
//
// * For 'Stop Clocks N Cycles after Internal Event',
// (stop_int_to_ext), N must be greater than or equal to
// (2*radix). This assures that ext_event_sb1 and
// ext_event_sb2 are both 0 when enbl_ext_stop_phi is asserted;
// this prevents ext_event_stop_a1 from being asserted in
// that cycle.
//
// These conclusions were drawn by laboriously simplifying the
// expression (last_phi & enbl_ext_stop_phi & ext_event_stop_a1).
//
wire stop_after_0_a1 = (ext_event_stop_a1 & (ext_stop_phi[2:0]==3'h0)) ;
wire stop_after_1_a1 = (ext_event_stop_a1 & (ext_stop_phi[2:0]==3'h1)) ;
wire stop_after_2_a1 = (ext_event_stop_a1 & (ext_stop_phi[2:0]==3'h2)) ;
wire stop_after_3_a1 = (ext_event_stop_a1 & (ext_stop_phi[2:0]==3'h3)) ;
wire stop_after_4_a1 = (ext_event_stop_a1 & (ext_stop_phi[2:0]==3'h4)) ;
Mflipflop_srh sa0_ff(stop_after_0, stop_after_0_a1,
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
Mflipflop_srh sa1_ff(stop_after_1, stop_after_1_a1,
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
Mflipflop_srh sa2_ff(stop_after_2, stop_after_2_a1,
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
Mflipflop_srh sa3_ff(stop_after_3, stop_after_3_a1,
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
Mflipflop_srh sa4_ff(stop_after_4, stop_after_4_a1,
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
// The internal event stops will stop clocks one cycle after the event
// occurs.
// Note: unlike the stop_after_* signals, this one can transition in
// the middle of a free SBus cycle, since it is a function of
// int_event_detected.
// Note: this signal is ignored (in clk_cntl) when jtag_trst_l is
// asserted.
// CAUTION: the internal event stops will result in an extra sbclk edge
// if they are asserted while clocks are running and we stop in
// a nonzero phase. In general, the system must be reset
// afterwards.
wire stop_a1 =
stop_on_int_event & int_event_detected
// In stop_nth_event mode, we stop the cycle after the internal event
// which increments the XCC to a value of 00000002. XCC==0 when
// ext_event_sb1 is active, XCC==1 when ext_event_sb2 is active,
// and int_event and int_event_detected will each increment XCC
// by one.
| stop_nth_event & int_event_detected
& (int_event ? ext_event_sb1 : ext_event_sb2)
// Used by reset state machine to stop clocks on de-assertion of
// reset.
| rs_stop_even & next2last_phi
;
Mflipflop_sr stop_ff (stop, stop_a1,
ss_scan_mode, /*scan-in*/, rcc_rst_l, rcc_clk) ;
// This is set on internal event, and reset at the beginning of each
// sbclk cycle. It is used to hold internal events until we can
// latch them in the int_event FF.
Mflipflop_sr int_ev_mc_ff (int_event_midcycle, (~last_phi & int_event_a1),
ss_scan_mode, /*scan-in*/, rcc_rst_even_l, rcc_clk) ;
wire standby_error ; // (forward)
// assign int_event_detected = iu_event | mm_event | standby_error ;
assign int_event_detected = iu_event_gate | mm_event_gate | standby_error ;
assign int_event_a1 = int_event_detected | int_event_midcycle ;
// This effectively clocks at the sbclk rate. In int-to-ext mode,
// hold it once it gets set.
Mflipflop_srh int_ev_ff (int_event, int_event_a1,
ss_scan_mode, /*scan-in*/,
~(last_phi & ~hold_int_event), rcc_rst_even_l, rcc_clk) ;
assign hold_int_event = (stop_int_to_ext & int_event) | rs_dsbl_clocks ;
wire int_event_l = ~int_event ;
// Sysclk is disabled when this is active.
Mflipflop_srh sds_ff (standby_dsbl_sysclk, standby_dsbl_sysclk_a1,
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
// Graphics clock phase reference
wire [1:0] gclk_phase, gclk_phase_late_a1 ;
assign gclk_phase_bit1 = gclk_phase[1]; //export for 595 bug fix
Mflipflop_s_2 gcp_reg(gclk_phase[1:0], gclk_phase_late_a1[1:0],
ss_scan_mode, /*scan-in*/, rcc_clk) ;
wire gclk_1st_phase = (gclk_phase[1:0]==2'b00) ;
// The TLB megacell needs a signal that rises when standby_dsbl_sysclk
// rises, but drops one sbclk cycle earlier.
wire standby_dsbl_tlb = standby_dsbl_sysclk & standby_dsbl_sysclk_a1 ;
// This will delay the start of the standby clock disable period
wire standby_busy =
~ic_standby_f | ~dc_standby_w | mm_hold_rst | ~memif_idle | ~pcic_idle ;
// Standby state machine
wire [1:0] standby_state, standby_state_a1 ;
parameter
IDLE = 2'b00,
WAIT = 2'b01,
DSBL = 2'b11 ;
wire standby_req = standby_state[0] ;
// standby_dsbl_sysclk_a1 must meet setup to a flipflop clocked by the
// next-to-last input_clock edge of the sbclk cycle; standby_state is
// clocked on sbclk edge.
wire standby_dsbl_sysclk_a1 = standby_state[1] ;
function [1:0] standby_next_state ;
input [1:0] standby_state ;
input do_standby ;
input standby_busy ;
begin
case (standby_state) // synopsys parallel_case
IDLE : standby_next_state = do_standby ? WAIT : IDLE ;
// Assert standby_req, wait for units to be idle.
WAIT : standby_next_state =
// Abort if standby pin is de-asserted
~do_standby ? IDLE : (
standby_busy ? WAIT : (
DSBL )) ;
// Assert standby_dsbl_sysclk_a1 to turn off clocks in next
// sbclk cycle; wait for standby to be de-asserted.
// Keep asserting standby_req
DSBL : standby_next_state = do_standby ? DSBL : IDLE ;
// synposys_translate_off
default: standby_next_state = 2'bx ;
// synposys_translate_off
endcase
end
endfunction
// Bug 562 fix - abort the standby if a reset (e.g. watchdog) happens.
wire do_standby = standby & ~reset_out ;
assign standby_state_a1 = standby_next_state(
standby_state[1:0],
do_standby,
standby_busy
) ;
// State register
Mflipflop_srh_2 srq_reg(standby_state[1:0], standby_state_a1[1:0],
ss_scan_mode, /*scan-in*/, ~last_phi, rcc_rst_even_l, rcc_clk) ;
// It's an error for any of the standby wait conditions to be active
// during a standby clock disable. This is ORed into int_event,
// so we can stop rcc_clock when it happens.
wire standby_error_detected = standby_dsbl_sysclk & standby_busy ;
// Bug 578 fix: This FF is set on the first standby_error_detected, and
// stays set until rcc_rst.
Mflipflop_srh sbe_ff(standby_error, standby_error_detected,
ss_scan_mode, /*scan-in*/, standby_error, rcc_rst_l, rcc_clk) ;
// Monitors
// synopsys translate_off
Mflipflop_noop sbm1_ff(standby_req_d1, standby_req, rcc_clk) ;
Mflipflop_noop sbm2_ff(dc_standby_w_d1, dc_standby_w, rcc_clk) ;
Mflipflop_noop sbm3_ff(ic_standby_f_d1, ic_standby_f, rcc_clk) ;
Mflipflop_noop sbm4_ff(pcic_idle_d1, pcic_idle, rcc_clk) ;
Mflipflop_noop sbm5_ff(mm_hold_rst_d1, mm_hold_rst, rcc_clk) ;
Mflipflop_noop sbm6_ff(memif_idle_d1, memif_idle, rcc_clk) ;
// Monitors
always @(posedge rcc_clk)
if (~ss_scan_mode & rcc_rst_l) #2 begin
if (last_phi && (^standby_state_a1 === 1'bx))
Mclocks.print_error("clk_stop: unknown standby next state") ;
if (standby_error_detected!==1'b0)
Mclocks.print_error("clk_stop: machine busy during standby") ;
// Complain if anyone changes his mind about being idle during
// standby_req (see Bug 524). Give them one cycle to respond
// to standby_req->1 .
if (standby_req & standby_req_d1) begin
// Once dc_cntl goes idle it should stay idle
if (~dc_standby_w & dc_standby_w_d1)
Mclocks.print_error(
"clk_stop: dc_standby_w->0 during standby_req") ;
// Check ic_cntl after dc_cntl has gone idle (so we don't have to
// worry about force_dva).
if (~ic_standby_f & ic_standby_f_d1 & dc_standby_w_d1)
Mclocks.print_error(
"clk_stop: ic_standby_f->0 during standby_req") ;
// // Don't check SBC unless both caches are idle
// if (~sbc_idle & sbc_idle_d1 & ic_standby_f & dc_standby_w)
// Mclocks.print_error(
// "clk_stop: sbc_idle->0 during standby_req") ;
// Don't check MMU busy unless both caches are idle
if (mm_hold_rst & ~mm_hold_rst_d1
// & ic_standby_f & dc_standby_w & sbc_idle)
& ic_standby_f & dc_standby_w)
Mclocks.print_error(
"clk_stop: mm_hold_rst->1 during standby_req") ;
// Don't check PCI unless both caches and MMU and memory are idle
if (~pcic_idle & pcic_idle & ic_standby_f & dc_standby_w
& memif_idle & ~mm_hold_rst)
Mclocks.print_error(
"clk_stop: pcic_idle_->0 during standby_req") ;
// Don't check memif unless both caches, PCI, and mmu are idle
if (~memif_idle & memif_idle_d1
& ic_standby_f & dc_standby_w & pcic_idle & ~mm_hold_rst)
Mclocks.print_error(
"clk_stop: memif_idle->0 during standby_req") ;
end
end
// synopsys translate_on
assign logic_0 = 1'b0 ;
assign logic_1 = 1'b1 ;
endmodule
| This page: |
Created: | Thu Aug 19 12:00:52 1999 |
| From: |
../../../sparc_v8/ssparc/clk_misc/misc/rtl/rl_clk_stop.v
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