(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(r_dc_par & wb_valid_x & ~std_x & ~sb_data_avail & r_dcdaten &
(r_mem_space | (r_fb_space & ~afx_qbusy)) & ~r_misc_bsy ) |
(r_ic_par & ~r_misc_bsy & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))))) |
(m_state[MRD] & tw_write_req) |
(m_state[DWR] & std_x & (r_mem_space | (r_fb_space & ~afx_qbusy))) |
(m_state[SB_WR1] & r_memfb_space ) |
(m_state[D_ATOMIC] &
(r_dcdaten & wb_valid_x & ~r_misc_bsy &
(r_mem_space | (r_fb_space & ~afx_qbusy)))) ;
assign mem_issue_req2 = mem_issue_req ; // copy for MEMIF timing
/*** Write buffer strobe *****************************************************/
/*** D_ATOMIC -> DWR (IDLE) - stobe on write request (or trap) ***/
assign mm_wbstb_marb =
(m_state[IDLE] &
((r_dc_par & wb_valid_x & r_dcdaten & ~sb_data_avail & ~std_x &
(r_mem_space | (r_fb_space & ~afx_qbusy)) & ~r_misc_bsy) |
(r_dc_par & wb_valid_x & r_io_space & r_dcdaten &
~std_x & ~r_sbsy ))) |
(m_state[D_ATOMIC] &
((wb_valid_x & r_dcdaten & ~r_misc_bsy &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(wb_valid_x & r_dcdaten & r_io_space & (~r_sbsy | r_trap_w)))) |
(m_state[DWR] & ((~r_cntl_space & std_x) |
(r_io_space & r_trap_w))) |
(m_state[DWR_CS]) ;
/*** IO space issue request **************************************************/
/*** IDLE -> DRD_IO - D-cache I/O space read ***/
/*** -> DWR - D-cache write (~std) to I/O space ***/
/*** -> IRD_IO - I-cache I/O space read ***/
/*** DWR -> DWR_DONE - D-cache write (std) to I/O space ***/
/*** D_ATOMIC-> DWR - D-cache write to I/O space ***/
assign io_issue_req =
(m_state[IDLE] &
((r_dc_par & ~wb_valid_x & read_w & r_io_space &
~fp_ld_mask & ~r_sbsy) |
(r_dc_par & wb_valid_x & r_io_space & r_dcdaten &
~std_x & ~r_sbsy) |
(r_ic_par & r_io_space & ~r_sbsy))) |
(m_state[DWR] & r_io_space & std_x) |
(m_state[D_ATOMIC] & r_io_space & r_dcdaten & ~r_sbsy & ~r_trap_w) ;
/*** PIO strobe mm_cpcyc_stb_l **********************************************/
assign mm_cpcyc_stb_l = ~io_issue_req ;
/*** PIO ifetch mm_ifetch ***************************************************/
/* This signal is used to tell the SBC that the current PIO read is for an */
/* I fetch. This signal is only valid for the cycle of mm_cpcyc_stb_l */
assign mm_ifetch = m_state[IDLE] & r_ic_par & r_io_space & ~r_sbsy ;
/*** Read/Write signal for mm_cpcyc_stb_l ***********************************/
/*** ONLY VALID during cycle of mm_cpcyc_stb_l ***/
assign mm_cpsb_wrt = (m_state[IDLE] & r_dc_par & write_x) |
(m_state[D_ATOMIC] & r_io_space & ldst_st) |
(m_state[DWR] & r_io_space & std_x);
/*** ic_issue_req ************************************************************/
/*** This signal indicates when a request was made for an I-cache miss. ***/
/*** It is used to invalidate the IPAR register (ipar_valid). ***/
/*** IDLE -> IRD_C1 - I-cache read ***/
/*** -> IRD_IO - I-cache I/O space read ***/
assign ic_issue_req =
(m_state[IDLE] &
((r_ic_par & ~r_misc_bsy & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(r_ic_par & r_io_space & ~r_sbsy ))) ;
/*** dc_issue_req ************************************************************/
/*** This signal indicates when a request was made for an D-cache miss. ***/
/*** It is used to invalidate the DPAR register (dpar_valid). ***/
/*** IDLE -> DRD_C1 - D-cache read ***/
/*** -> DWR - D-cache write (~std) to memory (& ~st_miss_c) ***/
/*** (on cached store misses, wait until read allocate) ***/
/*** -> DRD_IO - D-cache I/O space read ***/
/*** -> DWR - D-cache write (~std) to I/O space ***/
/*** DWR -> DWR_DONE - D-cache write (std) to memory ***/
/*** -> DWR_DONE - D-cache write (std) to I/O space ***/
/*** DWR_CS -> DWR_CS - D-cache write to cntl space ***/
/*** D_ATOMIC-> DWR - D-cache write to memory ***/
/*** -> DWR - D-cache write to I/O space ***/
assign dc_issue_req =
(m_state[IDLE] &
((r_dc_par & (read_w | (write_x & ~wb_valid_x)) & ~ldsto_x &
~wb_valid_x & ~r_misc_bsy & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(r_dc_par & wb_valid_x & r_dcdaten & ~std_x &
~st_miss_c & ~r_misc_bsy & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(r_dc_par & ~st_miss_x & read_w & r_io_space & ~wb_valid_x &
~(ldsto_x & ~ldst_st) & ~fp_ld_mask & ~r_sbsy) |
(r_dc_par & wb_valid_x & r_io_space &
~std_x & r_dcdaten & ~r_sbsy ))) |
(m_state[DWR] &
((std_x & ~st_miss_c & (r_mem_space | (r_fb_space & ~afx_qbusy))) |
(std_x & r_io_space))) |
(m_state[DRD_CS] & read_w & ~wb_valid_x) |
(m_state[DWR_CS] & r_cntl_space ) |
(m_state[D_ATOMIC] &
((r_dcdaten & wb_valid_x & ~r_sbsy & r_io_space) |
(r_dcdaten & wb_valid_x &
(r_mem_space | (r_fb_space & ~afx_qbusy)) & ~r_misc_bsy))) ;
/*** Early warning of a pending mm_issue_req *********************************/
/*** This is needed to avoid refresh from starting in the 1-cycle ***/
/*** between the branch from IDLE, and the real issue_req. ***/
/*** ***/
/*** IDLE -> SB_WR0 - DMA write ***/
/*** -> MRD - MMU tablewalk write ***/
/*** -> DWR - D-cache write (std) to memory ***/
/*** SB_WR0 -> SB_WR1 - Any DMA (SBC) write to memory ***/
assign issue_req_early = (m_state[IDLE] &
((r_sb_par & sb_write & ~mc_mbsy & ~r_misc_bsy ) |
(r_tw_par & tw_write_req & ~r_misc_bsy &
~sb_data_avail) |
(r_dc_par & wb_valid_x & r_dcdaten &
~sb_data_avail & std_x & ~mc_mbsy &
(r_mem_space | (r_fb_space & ~afx_qbusy))))) |
m_state[SB_WR0];
/*** Write buffer select *****************************************************/
/*** defaults to selecting MSW, which always has LSW for 1-word store ******/
assign mm_wbsel1 =
~(m_state[IDLE] &
((r_dc_par & wb_valid_x & r_dcdaten & ~sb_data_avail & std_x &
(r_mem_space | (r_fb_space & ~afx_qbusy)) & ~mc_mbsy) |
(r_dc_par & wb_valid_x & r_io_space & r_dcdaten & std_x & ~r_sbsy))) ;
/*** cs_st_op ****************************************************************/
/* signal the marb DWR_CS and DWR_CS1 states to generate bad_io_xlate */
assign cs_st_op = m_state[DWR_CS] | m_state[DWR_CS1];
/*** marb_sm busy ************************************************************/
/*** The marb_sm is set to "busy" any time it is not in the IDLE state ***/
assign marb_busy = ~m_state[IDLE] ;
/*** ldst_st decode - indicates store portion of ldst miss *******************/
/*** Set when dstat_avail issued for read of ldst miss ***/
/*** Set when sb_data_avail issued on PIO read data returning ***/
/*** Clear when write is issued or trap detected ***/
wire ldst_st ;
wire ldst_st_in
= (ldsto_x & mm_dstat_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(ldsto_x & sb_data_avail & ~r_sb_ic_op) |
(ldst_st & ~(m_state[DWR] | (r_trap_w & r_io_space))) ;
Mflipflop_r_1 ldst_st_ff_1(ldst_st,ldst_st_in,~ss_reset,ss_clock) ;
/*** ldst_block - block dvma_req in PAR *************************************/
/*** This signal is set in the cycle of issue_req for memory atomics ***/
/*** and prevents DC_PAR from allowing DVMA inbetween ld & st ***/
wire ldst_block_in = ldst_st_in |
(m_state[IDLE] &
(r_dc_par & read_w & ldsto_x & ~wb_valid_x & ~r_misc_bsy &
(r_mem_space | (r_fb_space & ~afx_qbusy)) & ~sb_data_avail));
wire ldst_block_q ;
Mflipflop_r_1 ldst_block_ff_1(ldst_block_q,ldst_block_in,~ss_reset,ss_clock) ;
assign ldst_block = ldst_block_q | (m_state[IDLE] &
(r_dc_par & read_w & ldsto_x & ~wb_valid_x & ~r_misc_bsy &
(r_mem_space | (r_fb_space & ~afx_qbusy)) & ~sb_data_avail));
/*** sb_data_clr decode ******************************************************/
/*** For clearing r_sb_ioreq registers in mmu_lgc ***/
assign sb_data_clr = m_state[DRD_IOD] | m_state[IRD_IOD] | m_state[SB_WR1];
/*** pio_data_rcvd decode ****************************************************/
/*** For AFSR far decode **************************************************/
assign pio_data_rcvd = sb_data_avail & ~r_sb_data_avail ;
/*** sb_par_clr decode *******************************************************/
/*** This is need for IO Control space ops. Since there is no issue_req ***/
/*** there has to be a way to clear PAR state machine. ***/
/*** PAR held for c_space ops ***/
assign sb_par_clr = m_state[SB_WR1] | m_state[SB_RD_CS] ;
/*** Status Valid decode for I-cache *****************************************/
/*** IDLE -> IRD_C1 - I-cache read ***/
/*** -> IRD_IO - I-cache I/O space read ***/
assign mm_istat_avail =
m_state[IDLE] &
((r_ic_par & ~r_misc_bsy & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(r_ic_par & r_io_space & ~r_sbsy)) ;
/*** Status Valid decode for I-cache *****************************************/
/*** IDLE -> DRD_C1 - D-cache read ***/
/*** -> DWR - D-cache write (~std) ***/
/*** DWR -> DWR_DONE - D-cache write (std) ***/
/*** ASI WR done force dstat_avail on (dnocache_done _aarb) ***/
/*** ASI RD done force dstat_avail on (A_MM_RD see _aarb) ***/
wire mm_dstat_avail_marb =
(m_state[IDLE] &
((r_dc_par & read_w & ~wb_valid_x & r_io_space &
~fp_ld_mask & ~r_sbsy) |
(r_dc_par & read_w & ~wb_valid_x & ~sb_data_avail &
~r_misc_bsy & (r_memcs_space | (r_fb_space & ~afx_qbusy))) |
(r_dc_par & wb_valid_x & (~std_x | r_cntl_space) & st_miss_x & ~ldsto_x &
r_dcdaten & ~dc_asi & ~sb_data_avail & r_io_space & ~r_sbsy) |
(r_dc_par & wb_valid_x & (~std_x | r_cntl_space) & st_miss_x & ~ldsto_x &
r_dcdaten & ~dc_asi & ~sb_data_avail & ~r_misc_bsy &
(r_memcs_space | (r_fb_space & ~afx_qbusy))))) |
(m_state[DWR] &
((std_x & st_miss_x & r_io_space & ~r_sbsy) |
(std_x & st_miss_x & ~r_misc_bsy &
(r_mem_space | (r_fb_space & ~afx_qbusy))))) ;
/*** tristate enable for MMU (misc) ******************************************/
/*** IDLE -> MRD - MMU tablewalk write ***/
/*** state DRD_CS - D-cache Control space read ***/
/*** state SB_RD_CS - SBC sontrol space read ***/
/*** mm_dstat_avail (data driven next cycle on misc) ***/
/*** mm_istat_avail (data driven next cycle on misc) ***/
assign mmdaten_marb =
(m_state[IDLE] & ~sb_data_avail &
(r_tw_par & tw_write_req & ~r_misc_bsy)) |
(m_state[DRD_CS] & ~wb_valid_x) |
(m_state[SB_RD_CS]) |
mm_dstat_avail |
mm_istat_avail ;
/*** tristate enable for I-cache (misc) **************************************/
/*** The only time the I-cache drives data on misc is for ASI Ops. ***/
/*** tristate enable for SBC (misc) ******************************************/
/*** IDLE -> SB_WR0 - DMA write ***/
/*** state DRD_IO - PIO D-cache reads ***/
/*** state DRD_IOD - PIO ldd reads ***/
/*** state IRD_IO - PIO I-cache instruction fetches ***/
/*** state IRD_IOD - PIO I-cache instruction fetches ***/
assign mm_iodaten =
((m_state[IDLE] & r_sb_par & sb_write &
~mc_mbsy & ~r_misc_bsy) |
(m_state[IDLE] & sb_data_avail & ~r_misc_bsy) |
(m_state[DRD_IOD] & ldd_w) |
(m_state[IRD_IOD]) |
(m_state[SB_WR0] ) |
(m_state[SB_WR1] & (r_sb_ioreq == SWR_4W)) |
(m_state[SB_WR2]) ) & (~ss_scan_mode); // added
/*** mm_slock signal to SBC **************************************************/
/*** Just an SR F/F set by DRD_IO and ldsto_x ***/
/*** reset by completing a D$ write ***/
/*** OR by having a trap in the D_ATOMIC state ***/
wire slock;
wire mm_slock;
Mflipflop_r_1 slock_ff_1(mm_slock,slock,~ss_reset,ss_clock) ;
assign slock = ((m_state[DRD_IO] & ldsto_x) | mm_slock) &
~(m_state[DWR_DONE] | (m_state[D_ATOMIC] & r_trap_w));
/*** tristate enable for MEMIF (misc) ****************************************/
/*** state SB_RD - DMA read (for word read remove 1-cycle early) ***/
/*** state SB_RD2 - DMA read (quad word) ***/
/*** state SB_RD3 - DMA read (8-word - words 5 & 6) ***/
/*** state SB_RD4 - DMA read (8-word - words 7 & 8) ***/
/*** state MRD - (& ~tw_write_req) MMU tablewalk read ***/
assign mm_mfdaten =
((m_state[SB_RD] ) |
(m_state[SB_RD2]) |
(m_state[SB_RD3]) |
(m_state[SB_RD4]) |
(m_state[MRD] & ~tw_write_req) ) & (~ss_scan_mode); // added
/*** Data Strobe for MMU (misc) **********************************************/
/*** state MRD - MMU tablewalk read (1-cycle before data valid) ***/
/*** state DRD_CS - D-cache Control space write ***/
/*** state SB_WR1 - IO Control Space write ***/
assign mmstben_marb = (m_state[MRD] & ~mc_mstb_l) |
(m_state[DRD_CS] & wb_valid_x) |
(m_state[SB_WR0] & r_cntl_space) ;
/*** Data Strobe for SBC (misc) **********************************************/
assign mm_iostben = ((m_state[SB_RD] |
m_state[SB_RD2]| m_state[SB_RD3]|
m_state[SB_RD4] ) & ~mc_mstb_l) |
(m_state[SB_RD_CS]) ;
/*** Data Strobe for D-cache (cachefill) *************************************/
/*** state DRD_C1 - D-cache read ***/
/*** state DRD_C2 - D-cache read ***/
/*** state DRD_IOD - D-cache read word from I/O space ***/
/*** state DRD_IOD2 - D-cache read 2-words from I/O space ***/
wire r_drd_iod;
Mflipflop_r_1 drd_iod_ff_1(r_drd_iod,m_state[DRD_IOD],~ss_reset,ss_clock) ;
assign dccfstb_marb =
(m_state[DRD_C1] & ~mc_mstb_l) |
(m_state[DRD_C2] & ~mc_mstb_l) |
(m_state[D_ATOMIC] & ~mc_mstb_l) |
(m_state[DRD_IOD3]) |
(m_state[D_ATOMIC] & r_io_space & r_drd_iod) ;
/*** Data Strobe for I-cache (cachefill) *************************************/
/*** state IRD_C1 - I-cache read (words 0 & 1) ***/
/*** state IRD_C2 - I-cache read (words 2 & 3) ***/
/*** state IRD_C3 - I-cache read (words 4 & 5) ***/
/*** state IRD_C4 - I-cache read (words 6 & 7) ***/
/*** state IRD_IOD2 - I-cache read 2-words from I/O space ***/
assign iccfstb_marb =
(m_state[IRD_C1] & ~mc_mstb_l) |
(m_state[IRD_C2] & ~mc_mstb_l) |
(m_state[IRD_C3] & ~mc_mstb_l) |
(m_state[IRD_C4] & ~mc_mstb_l) |
(m_state[IRD_IOD3]) ;
/*** transfer misc to cachefill (MEMIF) **************************************/
/*** state DRD_IO - D-cache read from I/O space ***/
/*** state DRD_IOD - D-cache read from I/O space ***/
/*** state DRD_IOD3 - D-cache read from I/O space ***/
/*** state DRD_IOD2 - D-cache read (ldd) from I/O space ***/
/*** state IRD_IO - I-cache read from I/O space ***/
/*** state IRD_IOD - I-cache read from I/O space ***/
assign misc2cf_marb =
(m_state[DRD_IOD]) |
(m_state[DRD_IOD2]) |
(m_state[DRD_IOD3]) |
// (m_state[IRD_IO]) |
(m_state[IRD_IOD]) |
(m_state[IRD_IOD3]) |
(m_state[IRD_IOD2]) |
(m_state[D_ATOMIC] & r_io_space) ;
/*** indicate 2nd word of transfer misc to cachefill (MEMIF) *****************/
/*** state IRD_IOD2 - I-cache read 2-words from I/O space ***/
/*** state DRD_IOD2 - D-cache read 2-words from I/O space ***/
assign mm_misc2cf_2nd =
(m_state[IRD_IOD2]) |
(m_state[DRD_IOD2] & r_sb_data_avail) ;
/*** PA strobe for SBC *******************************************************/
/*** state IDLE - DMA read request ***/
/*** - DMA translate request ***/
assign sbc_pa_valid = (m_state[IDLE] &
(r_srd_ioreq & r_sb_par & ~r_misc_bsy) |
(r_sxlate & r_sb_par)) ;
/*** Waiting for instruction read ********************************************/
/*** state IRD_C1 - I-cache read from memory (1st word) ***/
assign iwait_state = m_state[IRD_C1] ;
/*** Performance monitor decodes ********************************************/
assign ic_stream = m_state[IRD_C2] | m_state[IRD_C3] | m_state[IRD_C4] ;
assign dc_stream = m_state[DRD_C2] ;
assign drd_c1 = m_state[DRD_C1] ;
/*****************************************************************************/
/*** Monitor for checking tri-state enables ********************************/
/*****************************************************************************/
// synopsys translate_off
always @(posedge ss_clock) begin
if (~((mmdaten & ~mm_dcdaten & ~mm_dct_daten &
~mm_icdaten & ~mm_iodaten & ~mm_mfdaten) | //mmdaten
(~mmdaten & mm_dcdaten & ~mm_dct_daten &
~mm_icdaten & ~mm_iodaten & ~mm_mfdaten) | // mm_dcdaten
(~mmdaten & ~mm_dcdaten & mm_dct_daten &
~mm_icdaten & ~mm_iodaten & ~mm_mfdaten) | // mm_dct_daten
(~mmdaten & ~mm_dcdaten & ~mm_dct_daten &
mm_icdaten & ~mm_iodaten & ~mm_mfdaten) | // mm_icdaten
(~mmdaten & ~mm_dcdaten & ~mm_dct_daten &
~mm_icdaten & mm_iodaten & ~mm_mfdaten) | // mm_iodaten
(~mmdaten & ~mm_dcdaten & ~mm_dct_daten &
~mm_icdaten & ~mm_iodaten & mm_mfdaten)) & // mm_mfdaten
~ss_reset)
Mclocks.print_error("BAD misc tri-state enables ") ;
end
// synopsys translate_on
/*****************************************************************************/
/*** ASI Access State Machine *******************************************/
/*****************************************************************************/
function[10:0] next_a_state;
input marb_busy;
input mmu_asi;
input ic_asi;
input dc_asi;
input asi_dcd6;
input wb_valid_x;
input mc_mbsy;
input probe_done;
input flush_done;
input r_dc_miss;
input [10:0] a_state;
begin /* ASI access function */
next_a_state = 11'b0; /* set to default */
case (1'b1) // synopsys full_case parallel_case
a_state == 11'b0: next_a_state[AIDLE] = 1'b1;
/*** IDLE state **************************************************************/
a_state[AIDLE]:
case(1'b1) // synopsys parallel_case
/** ASI read of MMU registers (or TLB) *********************/
/** or write to TLB (must R/M/W TLB entries due to size) */
((mmu_asi & (~wb_valid_x | asi_dcd6) &
~marb_busy & ~mc_mbsy) |
(probe_done & ~marb_busy & ~mc_mbsy)):
next_a_state[A_MM_RD] = 1'b1;
/** ASI write of MMU registers *****************************/
((mmu_asi & wb_valid_x & ~asi_dcd6 &
~marb_busy & ~mc_mbsy) | (flush_done & ~marb_busy)):
next_a_state[A_MM_WR] = 1'b1;
/** ASI read of I-cache data/tags **************************/
((dc_asi | ic_asi) & ~wb_valid_x & ~marb_busy & ~mc_mbsy):
next_a_state[A_IC_RD] = 1'b1;
/** ASI write of I-cache data/tags *************************/
((dc_asi | ic_asi) & wb_valid_x & ~marb_busy & ~mc_mbsy):
next_a_state[A_IC_WR] = 1'b1;
/** Default - stay in AIDLE ********************************/
/** use default for gate level mismatch rtl . The follow **/
/** eqaution create illegal transition for MM_WR->IDLE ****/
/** MM_RD->IDLE (probe_done & ~marb_busy) ****************/
/** MM_WR->IDLE (flush_done & ~marb_busy) ****************/
/** also dc_asi case ****************/
default:
next_a_state[AIDLE] = 1'b1;
endcase
/*****************************************************************************/
/*** A_MM_RD state - ASI read of MMU regs (or TLB) ***************************/
a_state[A_MM_RD]:
case(1'b1) // synopsys full_case parallel_case
/** ASI read of MMU registers ******************************/
(asi_dcd6):
next_a_state[A_TLB_RD1] = 1'b1;
/** ASI read of MMU registers ******************************/
(~asi_dcd6):
next_a_state[A_MM2MISC] = 1'b1;
endcase
/*****************************************************************************/
/*** A_TLB_RD1 state - ASI read of TLB ***************************************/
a_state[A_TLB_RD1]:
next_a_state[A_TLB_RD2] = 1'b1;
/*****************************************************************************/
/*** A_TLB_RD2 state - ASI read of TLB ***************************************/
a_state[A_TLB_RD2]:
case(1'b1)
/** ASI write of TLB entry ***********************************/
(wb_valid_x):
next_a_state[A_MM_WR] = 1'b1;
/** ASI read of TLB entry ***********************************/
(~wb_valid_x):
next_a_state[A_MM2MISC] = 1'b1;
endcase
/*****************************************************************************/
/*** A_MM2MISC state - ASI transfer MMU data on misc (to MEMIF) **************/
a_state[A_MM2MISC]:
next_a_state[A_MISC2CF] = 1'b1;
/*****************************************************************************/
/*** A_IC_RD state - ASI read of I-cache data/tags ***************************/
a_state[A_IC_RD]:
next_a_state[A_IC2MISC] = 1'b1;
/*****************************************************************************/
/*** A_IC2MISC state - ASI transfer of I$ data/tags on misc (to MEMIF) *******/
a_state[A_IC2MISC]:
next_a_state[A_MISC2CF] = 1'b1;
/*****************************************************************************/
/*** A_MISC2CF state - transfer of MEMIF (ASI) data to cachefill bus *********/
a_state[A_MISC2CF]:
next_a_state[A_MM_WAIT] = 1'b1;
/*****************************************************************************/
/*** A_MM_WR state - writing the MMU regsiters *********/
a_state[A_MM_WR]:
next_a_state[A_MM_WAIT] = 1'b1;
/*****************************************************************************/
/*** A_MM_WAIT state - done writing the MMU regsiters just witing for DC ****/
a_state[A_MM_WAIT]:
next_a_state[AIDLE] = 1'b1;
/*****************************************************************************/
/*** A_IC_WR state - writing the I-cache tags or data *********/
a_state[A_IC_WR]:
next_a_state[A_MISC2CF] = 1'b1;
/*****************************************************************************/
endcase /* state decode case */
end /* ASI access function */
endfunction /* asi_sm */
/*****************************************************************************/
/*** Instantiate asi_sm *****************************************************/
wire[10:0] a_state_in = next_a_state(marb_busy, mmu_asi, ic_asi, dc_asi,
asi_dcd6, wb_valid_x, mc_mbsy,
probe_done, flush_done, r_dc_miss, a_state) ;
/*** asi_sm state registers **************************************************/
Mflipflop_r_11 asi_state_ff_11(a_state,a_state_in,~ss_reset,ss_clock) ;
/*****************************************************************************/
/*** Output Decodes (asi_sm related) *****************************************/
/*** ASI state machine Busy decode *******************************************/
/*** state AIDLE - ASI idle state ***/
/*** AIDLE -> any other state ***/
assign asi_bsy = (~a_state[AIDLE]) |
(a_state[AIDLE] & ~marb_busy & ~mc_mbsy &
(mmu_asi | ic_asi | dc_asi )) ;
assign aarb_bsy = ~a_state[AIDLE] ;
/*** D-no-cache Done decode **************************************************/
assign mm_dnocache_done = a_state[A_MM2MISC] | a_state[A_MISC2CF] |
a_state[A_MM_WR] ;
/*** NEED to add error case to abort bad control space decodes !!!! **********/
/*** Data Strobe for MMU (misc) **********************************************/
/*** state A_MM_WR - ASI write to MMU reg. or TLB ***/
assign mmstben_aarb = (a_state[A_MM_WR]) ;
/*** Clear Strobe for MMU registers ******************************************/
/*** state A_MM2MISC - transfer misc data to cache-fill bus (MEMIF)***/
/*** state SB_RD_CS - SBC sontrol space read ***/
/*** state DRD_CS - D-cache Control space read ***/
assign mmreg_rd_asi = a_state[A_MM2MISC] ;
assign mmreg_rd_cs = (m_state[SB_RD_CS] | (m_state[DRD_CS] & ~wb_valid_x)) ;
/*** tristate enable for MMU (misc) ******************************************/
/*** state A_MM2MISC - MMU register read ***/
/*** state A_TLB_RD1 - MMU TLB read (2-cycle TLB read op) ***/
/*** state A_TLB_RD2 - MMU TLB read (2-cycle TLB read op) ***/
/*** state A_TLB_RD2 & wb_valid_x will be MMU TLB write ***/
/*** mmdaten shouldn't turn on on MMU TLB write ***/
wire mmdaten_aarb = ((mm_dnocache_done & ~read_w & ~(dc_asi | ic_asi)) |
a_state[A_MM2MISC] |
a_state[A_TLB_RD1] |
(a_state[A_TLB_RD2] & ~wb_valid_x)) ;
/*** Data Strobe for D-cache (cachefill) *************************************/
/*** state A_MISC2CF - transfer misc data to cache-fill bus (MEMIF)***/
wire dccfstb_aarb = (a_state[A_MM_WAIT] & read_w) ;
/*** Data Strobe for I-cache (cachefill) *************************************/
/*** state A_IC_WR - I-cache write data/tag state ***/
assign mm_icstben = a_state[A_MM_WAIT] & ic_asi & ~read_w;
/*** tristate enable for D-cache Tag(misc) ***********************************/
/*** state A_IC_RD - transfer I-cache data onto misc bus ***/
assign mm_dct_daten = ((a_state[A_IC2MISC] | a_state[A_MISC2CF]) & dc_asi & read_w) & (~ss_scan_mode); // added
/*** tristate enable for I-cache (misc) **************************************/
/*** state A_IC2MISC - transfer I-cache data onto misc bus ***/
assign mm_icdaten = (a_state[A_IC2MISC] & ~dc_asi & read_w) & (~ss_scan_mode); // added
/*** transfer misc to cachefill (MEMIF) **************************************/
/*** state A_MM2MISC - transfer misc data to cache-fill bus (MEMIF)***/
wire misc2cf_aarb = ((~flush_done & a_state[A_MM_WAIT]) | a_state[A_MISC2CF]) |
a_state[A_IC_WR] |
(a_state[AIDLE] &
(mmu_asi_op & wb_valid_x & ~marb_busy & ~mc_mbsy ));
// (mmu_asi_op & (dc_asi | ic_asi) & wb_valid_x & ~marb_busy & ~mc_mbsy )));
/*** Status Valid decode for D-cache *****************************************/
/*** ASI WR done force dstat_avail on (dnocache_done ) ***/
/*** ASI RD done force dstat_avail on (A_MM_RD ) ***/
/*** ASI IC_RD done force dstat_avail on (A_IC_RD ) ***/
wire mm_dstat_avail_aarb = a_state[A_MM_WR] |
(a_state[AIDLE] & ~marb_busy & ~mc_mbsy & probe_done) |
(a_state[AIDLE] & ~marb_busy & ~mc_mbsy &
(dc_asi | ic_asi | (mmu_asi & ~wb_valid_x & read_w)));
/*** Set TLB inputs for ASI read *********************************************/
wire tlb_asi_rd = (a_state[A_MM_RD] & asi_dcd6) |
a_state[A_TLB_RD1] ;
/**** direct cam read will turn on at MM_RD and cam data will show at tlb rd 2 ***/
wire tlb_c_rd_unbuf = a_state[A_MM_RD] & asi_dcd6;
JBUFC slow_buf7(tlb_c_rd_unbuf,buf_term2);
JBUFD slow_buf6(buf_term2,tlb_c_rd);
/*** Set TLB inputs for ASI write ********************************************/
wire tlb_asi_wr = (a_state[A_MM_WR] & asi_dcd6) ;
/*** Set TLB inputs for ASI access *******************************************/
assign tlb_asi_act = tlb_asi_rd | tlb_asi_wr ;
/*** Set TLB inputs for ASI access *******************************************/
assign mm_wbstb_aarb = (a_state[AIDLE] & ~read_w & flush_done)|
(((~asi_dcd6 & a_state[A_MM_WAIT]) |
(asi_dcd6 & a_state[A_MM_WR])) & ~read_w & ~flush_done);
assign asi_sm_done = a_state[A_MM_WAIT] ;
/***** output asi cam ram read hold signal ********/
assign asi_cam_read = asi_dcd6 & (a_state[A_MM2MISC] | a_state[A_MM_WR] | a_state[A_MM_WAIT]);
assign asi_ram_read = asi_dcd6 & (a_state[A_TLB_RD2] | a_state[A_MM2MISC] | a_state[A_MM_WR] | a_state[A_MM_WAIT]);
/*****************************************************************************/
/*** Output Decodes (merged from both state machines) ************************/
assign mmdaten = (mmdaten_marb | mmdaten_aarb) & (~ss_scan_mode) ; // added
/*** Write buffer strobe for memory ops, ASI ops, and aborted stores ********/
assign mm_wbstb = mm_wbstb_marb | mm_wbstb_aarb | derr_wbstb | wb_err ;
assign mm_dstat_avail = mm_dstat_avail_marb | mm_dstat_avail_aarb ;
assign mmstben = mmstben_marb ;
assign mm_dccfstb = dccfstb_marb | dccfstb_aarb ;
assign mm_misc2cf = misc2cf_marb | misc2cf_aarb ;
assign mm_iccfstb = iccfstb_marb ; /* (add iccfstb_aarb when IC ASIs added) */
assign sel_cache_stat = ((m_state[IDLE] & (a_state[IDLE] | a_state[A_MM_WR])) |
m_state[DWR] | m_state[D_ATOMIC]) & ~r_tw_par ;
/*** tristate enable for D-cache (misc) *** DEFAULT BUS DRIVER ***************/
assign mm_dcdaten = (~(mm_iodaten | mm_mfdaten | mmdaten |
mm_icdaten | mm_dct_daten)) & (~ss_scan_mode); // added
/*****************************************************************************/
endmodule // rl_marb_sm
/*****************************************************************************/
| This page: |
Created: | Thu Aug 19 12:02:57 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/rl_marb_sm.v
|