/******************************************************************************/
/* */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)rl_marb_sm.v
***
****************************************************************************
****************************************************************************/
//****************************************************************************
// @(#)rl_marb_sm.v 1.149 3/25/94
//
// Description:
// Preprocessed MMU Bus Arbiter State Machine
//
//****************************************************************************
/* functional model of MMU internal memory bus arbiter */
![[Up: m_mmu_cntl marb_sm]](v2html-up.gif)
module rl_marb_sm
(
mm_ifetch, /* ifetch from sbus (EPROM) op. */
cs_st_op, /* control space mmu reg store op. */
mm_cpcyc_stb_l, /* output indicating SBC data & addr. valid */
issue_req_early, /* output indicating a pending issue req */
mm_cpsb_wrt, /* output indicating SBC wrt */
mm_slock, /* output indicating PIO atomic op */
sb_data_clr, /* signal that sb_data_avail is being serviced */
sb_par_clr, /* signal IO control space op is done */
pio_data_rcvd, /* signal PIO data has been received */
mem_issue_req, /* Main memory issue request */
mem_issue_req2, /* Main memory issue request */
io_issue_req, /* IO space issue request */
mm_istat_avail, /* Status Valid decode for I-cache */
mm_dstat_avail, /* Status Valid decode for I-cache */
ic_issue_req, /* Issue request for I-cache op*/
dc_issue_req, /* Issue request for D-cache op*/
mmdaten, /* tristate enable for MMU (misc) */
mm_dcdaten, /* tristate enable for D-cache (misc) */
mm_dct_daten, /* tristate enable for D-cache Tag(misc) */
mm_icdaten, /* tristate enable for I-cache (misc) */
mm_iodaten, /* tristate enable for SBC (misc) */
mm_mfdaten, /* tristate enable for MEMIF (misc) */
mmstben, /* Data Strobe for MMU (misc) */
mm_iostben, /* Data Strobe for SBC (misc) */
mm_icstben, /* Data Strobe for I-cache ASI (misc) */
mm_dccfstb, /* Data Strobe for D-cache (cachefill) */
mm_iccfstb, /* Data Strobe for I-cache (cachefill) */
mm_misc2cf, /* transfer misc to cachefill (MEMIF) */
mm_misc2cf_2nd, /* transfer misc to cachefill (MEMIF) 2nd word */
sbc_pa_valid, /* PA valid for SBC */
r_sb_ic_op, /* Last PIO op was for an I-cache miss */
r_mbsy, /* */
r_fb_space, /* */
ldst_st, /* Store portion of ldsto (D_ATOMIC) */
ldst_block, /* block dvma req on ldst ops */
r_mstb_l, /* Reg'd mc_mstb_l */
iwait_state, /* Waiting for 1st instruction from mem */
mmstben_aarb, /* Data strobe for MMU on ASI stores */
mmreg_rd_asi, /* Data strobe for MMU on ASI loads */
mmreg_rd_cs, /* Data strobe for MMU on ASI loads */
mm_wbstb, /* Write buffer strobe for advancing wb */
mm_wbsel1, /* Write buffer select for std */
tlb_asi_act, /* tlb ASI op active, determined by state */
tlb_c_rd, /* tlb direct cam read */
mm_dnocache_done, /* non $ op done */
asi_sm_done, /* non $ asi op done */
asi_cam_read, /* output asi_cam_read operation */
asi_ram_read, /* output asi_ram read operation */
ic_stream, /* Perfromance monitor decode */
dc_stream, /* Perfromance monitor decode */
r_drd_c1, /* Marb state DRD_C1 reg'd */
sel_cache_stat, /* MMU register select decode */
marb_busy, /* Memory arbitration state machine busy */
aarb_bsy, /* ASI arbitration state machine busy */
pcic_ifetch, /* icache miss held until next request for pcic boot */
sb_err_type, /* drive timeout error for any sbus access */
sb_wrt_err, /* drive sb_wrt_err for write sbus access */
sb_errsize, /* drive sb_errsize for any sbus access */
sb_ioreq, /* drive sb_ioreq for any sbus access */
sb_ioreq_vld, /* drive sb_ioreq_vld for any sbus access */
/* inputs */
mm_sbsize, /* need to know size for sbus operation termination */
r_srd_ioreq,
probe_done, /* probe operation done */
flush_done, /* flush operation done */
r_dc_miss, /* registered dc_miss */
mc_mbsy, /* Memory busy signal */
sb_sbsy, /* SBC busy signal */
dvma_req_x, /* DVMA request signal */
r_dc_par, /* D-cache address in PAR */
r_ic_par, /* I-cache address in PAR */
r_sb_par, /* DMA (sbc) address in PAR */
sb_par, /* DMA (sbc) address in PAR unregistered*/
r_tw_par, /* tablewalk address in PAR */
r_io_space, /* PAR decode for IO space address */
r_cntl_space, /* PAR decode for Control space address */
r_mem_space, /* PAR decode for Main memory space address */
fb_space, /* PAR decode for AFX memory space address */
mop_c_bit, /* Current memory op cacheable bit */
mop_mreq, /* Current memory op cacheable bit */
mc_mstb_l, /* data strobe (low) from MEMIF (1-cycle early) */
wb_valid_x, /* D-cache address in PAR for write op (x-stage)*/
read_w, /* D-cache address in PAR for read/ldsto op */
ldsto_x, /* D-cache address in PAR for ldsto */
sb_write, /* DMA (sbc) address in PAR for write op */
r_sxlate, /* DMA (sbc) xlate op */
sb_data_avail, /* Data available from SBC (on PIO reads) */
r_sb_ioreq, /* SBC request for current memory op */
tw_read_req, /* tablewalk read request */
tw_write_req, /* tablewalk address is PAR for write op */
std_x, /* Store is double word size */
ldd_w, /* D-cache load in W-stage is double word */
asi_dcd6, /* decode of W-stage ASI = 0x06 */
mmu_asi_op, /* decode of ASI state in PAR cntl */
mmu_asi, /* decode of W-stage ASI op */
ic_asi, /* decode of W-stage ASI is a I-cache target */
dc_asi, /* decode of W-stage ASI is a I-cache target */
write_x, /* Write in W-stage */
st_miss_c, /* Store miss in the W-stage - cacheable */
st_miss_x, /* Store miss in the W-stage */
derr_wbstb, /* Data error write buffer strobe */
dabort_in,
r_trap_w,
fp_ld_mask, /* FP mask for loads (until trap window done). */
wb_err,
afx_qbusy,
mmu_cr_14,
ss_clock,
ss_scan_mode, // added
ss_reset
);
/* Outputs */
output mm_ifetch; /* ifetch from EPROM */
output cs_st_op; /* */
output mm_cpcyc_stb_l; /* output indicating SBC data & addr. valid */
output issue_req_early; /* signal to memif of a pending issue_req */
output mm_cpsb_wrt; /* output indicating SBC wrt */
output mm_slock; /* mmu signal indicating PIO atomic */
output sb_data_clr; /* siganl that sb_data_avail has been seen*/
output sb_par_clr; /* signal IO control space op is done */
output pio_data_rcvd; /* signal PIO data has been received */
output mem_issue_req; /* Main memory issue request */
output mem_issue_req2; /* Main memory issue request */
output io_issue_req; /* IO space issue request */
output mm_istat_avail; /* Status Valid decode for I-cache */
output mm_dstat_avail; /* Status Valid decode for I-cache */
output ic_issue_req; /* Issue request for I-cache op*/
output dc_issue_req; /* Issue request for D-cache op*/
output mmdaten; /* tristate enable for MMU (misc) */
output mm_dcdaten; /* tristate enable for D-cache (misc) */
output mm_dct_daten; /* tristate enable for D-cache Tag(misc) */
output mm_icdaten; /* tristate enable for I-cache (misc) */
output mm_iodaten; /* tristate enable for SBC (misc) */
output mm_mfdaten; /* tristate enable for MEMIF (misc) */
output mmstben; /* Data Strobe for MMU (misc) */
output mm_iostben; /* Data Strobe for SBC (misc) */
output mm_icstben; /* Data Strobe for I-cache ASI (misc) */
output mm_dccfstb; /* Data Strobe for D-cache (cachefill) */
output mm_iccfstb; /* Data Strobe for I-cache (cachefill) */
output mm_misc2cf; /* transfer misc to cachefill (MEMIF) */
output mm_misc2cf_2nd; /* transfer misc to cachefill (MEMIF) */
output sbc_pa_valid; /* PA valid for SBC */
output r_sb_ic_op; /* Last PIO op was for an I-cache miss */
output r_mbsy; /* mem busy */
output r_fb_space; /* AFX space */
output ldst_st; /* Store portion of ldsto (D_ATOMIC) */
output ldst_block; /* Store portion of ldsto (D_ATOMIC) */
output r_mstb_l; /* Reg'd mc_mstb_l */
output iwait_state; /* Waiting for 1st instruction from mem */
output mmstben_aarb; /* Data strobe for MMU on ASI stores */
output mmreg_rd_asi; /* Data strobe for MMU on ASI loads */
output mmreg_rd_cs; /* Data strobe for MMU on ASI loads */
output mm_wbstb; /* Write buffer strobe for advancing wb */
output mm_wbsel1; /* Write buffer select for std */
output tlb_asi_act; /* tlb ASI op active, determined by state */
output tlb_c_rd; /* tlb direct cam read */
output mm_dnocache_done;/* non $ op done */
output asi_sm_done; /* non $ asi op done */
output asi_cam_read; /* asi is doing cam read */
output asi_ram_read; /* asi is doing ram read */
output ic_stream; /* Perfromance monitor decode */
output dc_stream; /* Perfromance monitor decode */
output r_drd_c1 ; /* Marb state DRD_C1 reg's */
output sel_cache_stat; /* MMU register select decode */
output marb_busy; /* Memory arbitration state machine busy */
output aarb_bsy; /* ASI arbitration state machine busy */
output pcic_ifetch; /* instruction cache miss held until next req */
output [1:0] sb_err_type; /* timeout error for any sbus access */
output sb_wrt_err; /* sb_wrt_err error for all sbus writes */
output [2:0] sb_errsize; /* size error for all sbus ops */
output [3:0] sb_ioreq; /* terminate PIO reads for all sbus reads */
output sb_ioreq_vld; /* terminate PIO reads for all sbus reads */
/* Inputs */
input [1:0] mm_sbsize; /* size of sb op to terminate */
input r_srd_ioreq;
input probe_done; /* probe operation done */
input flush_done; /* flush operation done */
input r_dc_miss; /* registered dc_miss */
input mc_mbsy; /* Memory Busy signal */
input sb_sbsy; /* SBC Busy signal */
input dvma_req_x; /* dvma request signal */
input r_dc_par; /* D-cache address in PAR */
input r_ic_par; /* I-cache address in PAR */
input r_sb_par; /* DMA (sbc) address in PAR */
input sb_par; /* DMA (sbc) address in PAR */
input r_tw_par; /* tablewalk address in PAR */
input r_io_space; /* PAR decode for IO space address */
input r_cntl_space; /* PAR decode for Control space address */
input r_mem_space; /* PAR decode for Main memory space address */
input fb_space; /* PAR decode for AFX memory space address */
input mop_c_bit; /* Current memory op cacheable bit */
input [3:0] mop_mreq; /* Current memory op mreq bit */
input mc_mstb_l; /* data strobe (low) from MEMIF */
input wb_valid_x; /* D-cache address in PAR for write op */
input read_w; /* D-cache address in PAR for read/ldsto op */
input ldsto_x; /* D-cache address in PAR for ldsto */
input sb_write; /* DMA (sbc) address in PAR for write op */
input r_sxlate; /* DMA (sbc) xlate op */
input sb_data_avail; /* Data available from SBC (on PIO reads) */
input[3:0] r_sb_ioreq; /* SBC request for current memory op */
input tw_read_req; /* tablewalk read request*/
input tw_write_req; /* tablewalk address is PAR for write op */
input std_x; /* Store is double word size */
input ldd_w; /* D-cache load in W-stage is double word */
input asi_dcd6; /* decode of W-stage ASI = 0x06 */
input mmu_asi_op; /* decode of ASI state in PAR cntl */
input mmu_asi; /* decode of W-stage ASI op */
input ic_asi; /* decode of W-stage ASI is a I-cache target */
input dc_asi; /* decode of W-stage ASI is a D-cache target */
input write_x; /* Write in W-stage */
input st_miss_c; /* Store miss in the W-stage - cacheable */
input st_miss_x; /* Store miss in the W-stage */
input derr_wbstb; /* Data error write buffer strobe */
input dabort_in;
input r_trap_w;
input fp_ld_mask; /* FP mask for loads (until trap window done).*/
input wb_err;
input afx_qbusy;
input mmu_cr_14;
input ss_clock;
input ss_scan_mode; // added
input ss_reset;
/*****************************************************************************/
// mreq operations
parameter [3:0] NOP = 4'b0000,
RD64 = 4'b0001,
RD128 = 4'b0010,
RD256 = 4'b0100,
WR8 = 4'b1001,
WR16 = 4'b1010,
WR32 = 4'b1011,
WR64 = 4'b1100;
// sb_ioreq operations
parameter [3:0] SNOP = 4'b0000,
SRD_8W = 4'b0001,
S_RSV0 = 4'b0010,
S_RSV1 = 4'b0011,
SCRDDATA = 4'b0100,
SRD_4W = 4'b0101,
S_RSV2 = 4'b0110,
SRD_DW = 4'b0111,
SWR = 4'b1000,
SWR_BY = 4'b1001,
SWR_HW = 4'b1010,
S_RSV3 = 4'b1011,
SWR_DW = 4'b1100,
SXLATE = 4'b1101,
SWR_4W = 4'b1110,
S_RSV4 = 4'b1111;
/*** Define marb_sm state names **********************************************/
parameter IDLE = 0,
MRD = 1,
DRD_C1 = 2,
DRD_C2 = 3,
D_ATOMIC = 4,
DWR = 5,
DWR_DONE = 6,
DRD_IO = 7,
DRD_IOD = 8,
DRD_IOD2 = 9,
DRD_CS = 10,
DWR_CS = 11,
IRD_C1 = 12,
IRD_C2 = 13,
IRD_C3 = 14,
IRD_C4 = 15,
IRD_IO = 16,
IRD_IOD = 17,
IRD_IOD2 = 18,
SB_RD = 19,
SB_RD2 = 20,
SB_RD3 = 21,
SB_RD4 = 22,
SB_WR0 = 23,
SB_WR1 = 24,
SB_WR2 = 25,
SB_WR3 = 26,
SB_RD_CS = 27,
SB_RD_CS2 = 28,
DWR_CS1 = 29,
DRD_IOD3 = 30,
IRD_IOD3 = 31;
/*** Define asi_sm state names ***********************************************/
parameter AIDLE = 0,
A_MM_RD = 1,
A_TLB_RD1 = 2,
A_TLB_RD2 = 3,
A_MM2MISC = 4,
A_IC_RD = 5,
A_IC2MISC = 6,
A_MISC2CF = 7,
A_IC_WR = 8,
A_MM_WR = 9,
A_MM_WAIT = 10;
/*****************************************************************************/
/*** Display routine for marb_sm state information ***************************/
// synopsys translate_off
wire [10:0] asi_state = rl_marb_sm.a_state;
wire [31:0] mem_state = rl_marb_sm.m_state;
reg[32*8:1] state_name;
integer i, acnt, mcnt;
always @(asi_state or mem_state) begin
acnt = 0; mcnt = 0;
for(i=0; i<10; i=i+1) acnt = acnt + asi_state[i];
for(i=0; i<32; i=i+1) mcnt = mcnt + mem_state[i];
if (~ss_reset & (asi_state == 11'b0 || mem_state == 32'b0)) begin
if(asi_state == 11'b0) begin
Mclocks.print_error("ASI arb state = 0 *** BAD A_STATE ***") ;
state_name = "*** ALL ZEROES *** BAD A_STATE!";
end
if(mem_state == 32'b0) begin
Mclocks.print_error("MEM arb state = 0 *** BAD M_STATE ***") ;
state_name = "*** ALL ZEROES *** BAD M_STATE!";
end
end
else if (~ss_reset & ~(asi_state[AIDLE] || mem_state[IDLE])) begin
Mclocks.print_error("Both MEM state machine active ***BUG NEWS***") ;
state_name = "[ERROR] - #$@!";
end
else if (acnt > 1 ) begin
Mclocks.print_error("More than 1 A_STATE bit asserted ") ;
state_name = "[ERROR] - #$@!";
end
else if (mcnt > 1 ) begin
Mclocks.print_error("More than 1 M_STATE bit asserted ") ;
state_name = "[ERROR] - #$@!";
end
else case (1'b1)
mem_state[IDLE] && asi_state[AIDLE]: state_name = "[idle] - idle";
mem_state[MRD]: state_name = "[mrd] - tablewalk read";
mem_state[DRD_C1]: state_name = "[drd_c1] - Data read 1";
mem_state[DRD_C2]: state_name = "[drd_c2] - Data read 2";
mem_state[D_ATOMIC]:state_name = "[d_atomic] - Data atomic";
mem_state[DWR]: state_name = "[dwr] - Data write";
mem_state[DWR_DONE]:state_name = "[dwr_done] - Data write done";
mem_state[DRD_IO]: state_name = "[drd_io] - Data IO read";
mem_state[DRD_IOD]: state_name = "[drd_iod] - Data IO read word0";
mem_state[DRD_IOD2]:state_name = "[drd_iod2] - Data IO read word1";
mem_state[DRD_IOD3]:state_name = "[drd_iod3] - Data IO read stb";
mem_state[DRD_CS]: state_name = "[drd_cs] - Data Cntl space read";
mem_state[DWR_CS]: state_name = "[dwr_cs] - Data Cntl spc write 0";
mem_state[DWR_CS1]: state_name = "[dwr_cs] - Data Cntl spc write 1";
mem_state[IRD_C1]: state_name = "[ird_c1] - Instr read 1";
mem_state[IRD_C2]: state_name = "[ird_c2] - Instr read 2";
mem_state[IRD_C3]: state_name = "[ird_c3] - Instr read 3";
mem_state[IRD_C4]: state_name = "[ird_c4] - Instr read 4";
mem_state[IRD_IO]: state_name = "[ird_io] - Instr I/O read";
mem_state[IRD_IOD]: state_name = "[ird_iod] - Instr I/O read data";
mem_state[IRD_IOD2]:state_name = "[ird_iod2] - Instr I/O read d2";
mem_state[IRD_IOD3]:state_name = "[ird_iod3] - Instr I/O read d3";
mem_state[SB_RD]: state_name = "[sb_rd] - SBC read 1";
mem_state[SB_RD2]: state_name = "[sb_rd2] - SBC read 2";
mem_state[SB_RD3]: state_name = "[sb_rd3] - SBC read 3";
mem_state[SB_RD4]: state_name = "[sb_rd4] - SBC read 4";
mem_state[SB_WR0]: state_name = "[sb_wr0] - SBC write 0";
mem_state[SB_WR1]: state_name = "[sb_wr1] - SBC write 1";
mem_state[SB_WR2]: state_name = "[sb_wr2] - SBC write 2";
mem_state[SB_WR3]: state_name = "[sb_wr3] - SBC write 3";
mem_state[SB_RD_CS]:state_name = "[sb_rd_cs] - SBC read Cntl spc";
mem_state[SB_RD_CS2]:state_name = "[sb_rd_cs2] - SBC read Cntl spc";
asi_state[A_MM_RD]: state_name = "[a_mm_rd] - ASI MMU read";
asi_state[A_MM_WR]: state_name = "[a_mm_wr] - ASI MMU Write";
asi_state[A_MM_WAIT]:state_name = "[a_mm_wait] - ASI MMU wait";
asi_state[A_TLB_RD1]:state_name = "[a_tlb_rd1] - ASI MMU read 1";
asi_state[A_TLB_RD2]:state_name = "[a_tlb_rd2] - ASI MMU read 2";
asi_state[A_MM2MISC]:state_name = "[a_mm2misc] - ASI MMU to misc";
asi_state[A_MISC2CF]:state_name = "[a_misc2cf] - ASI misc to CF";
asi_state[A_IC_RD]: state_name = "[a_ic_rd] - ASI I-cache Read";
asi_state[A_IC2MISC]:state_name = "[a_ic2misc] - ASI I$ to misc";
asi_state[A_IC_WR]: state_name = "[a_ic_wr] - ASI I-cache Write";
endcase
end
// synopsys translate_on
/*****************************************************************************/
/*** Memory Arbitration State Machine ****************************************/
/*****************************************************************************/
/*****************************************************************************/
/*** WIRE definitions ********************************************************/
wire mm_wbstb_marb; /* marb_sm decode for mm_wbstb*/
wire mm_wbstb_aarb; /* arb_sm decode for mm_wbstb*/
wire mmdaten_marb ; /* marb_sm decode for mmdaten */
wire mmstben_marb ; /* marb_sm decode for mmstben */
wire dccfstb_marb ; /* marb_sm decode for mm_dccfstb */
wire iccfstb_marb ; /* marb_sm decode for mm_iccfstb */
wire misc2cf_marb ; /* marb_sm decode for mm_misc2cf */
wire asi_bsy; /* asi_sm busy */
wire aarb_bsy; /* asi_sm busy */
wire ic_issue_req;
wire misc_bsy = mem_issue_req | mc_mbsy | asi_bsy ; /* decode for misc busy */
wire pcic_ifetch;
wire [1:0] sb_err_type; /* timeout error for any sbus access */
wire sb_wrt_err; /* turn around all sbus ops as errors */
wire [2:0] sb_errsize; /* turn around as timeouts */
wire sb_ioreq_vld; /* turn around PIO reads as timeouts */
wire [3:0] sb_ioreq; /* turn around PIO reads as timeouts */
/*****************************************************************************/
/*** REGISTER instantiations *************************************************/
// Add this to act as an enable for I-cache fetches for the pci controller
// for use in booting. boot_mode went off due to sta traffic.
wire pcic_ifetch_enable = mmu_cr_14 & ic_issue_req;
MflipflopR pcic_ifetch_boot(pcic_ifetch,pcic_ifetch_enable,ss_clock,
~mem_issue_req, ss_reset);
// Add decode and drivers to cause all sbus reads and writes to result
// in errors.
wire io_issue_req_d1;
Mflipflop_r_1 io_issue_ff_1(io_issue_req_d1,io_issue_req,~ss_reset,ss_clock) ;
wire io_issue_req_d2;
Mflipflop_r_1 io_issue_ff_2(io_issue_req_d2,io_issue_req_d1,~ss_reset,ss_clock) ;
wire io_issue_wrt_d1;
Mflipflop_r_1 io_issue_wrt_ff_1(io_issue_wrt_d1,mm_cpsb_wrt,~ss_reset,ss_clock) ;
wire io_issue_wrt_d2;
Mflipflop_r_1 io_issue_wrt_ff_2(io_issue_wrt_d2,io_issue_wrt_d1,~ss_reset,ss_clock) ;
assign sb_err_type = (io_issue_req_d1 ) ? 2'b00 : 2'b11 ;
assign sb_wrt_err = (mm_cpsb_wrt | io_issue_wrt_d1 | io_issue_wrt_d2) ? 1'b1 : 1'b0 ;
assign sb_errsize = (io_issue_req_d1 | io_issue_req_d2) ?
{(mm_sbsize[1] & mm_sbsize[0]), mm_sbsize[1:0]} : 3'b000 ;
assign sb_ioreq_vld = (io_issue_req_d1 & ~io_issue_wrt_d1) ? 1'b1 : 1'b0 ;
assign sb_ioreq = (sb_ioreq_vld) ? 4'b0100 : 4'b0000 ;
wire r_fb_space;
Mflipflop_r_1 fb_space_ff_1(r_fb_space,fb_space,~ss_reset,ss_clock) ;
wire r_memfb_space = r_mem_space | r_fb_space ;
wire r_memcs_space = r_mem_space | r_cntl_space ;
wire r_mstb_l;
Mflipflop_r_1 mstb_l_ff_1(r_mstb_l,mc_mstb_l,~ss_reset,ss_clock) ;
wire r_mbsy;
Mflipflop_r_1 mbsy_ff_1(r_mbsy,mc_mbsy,~ss_reset,ss_clock) ;
wire r_misc_bsy;
Mflipflop_r_1 misc_bsy_ff_1(r_misc_bsy,misc_bsy,~ss_reset,ss_clock) ;
wire r_sbsy;
Mflipflop_r_1 sbsy_ff_1(r_sbsy,sb_sbsy,~ss_reset,ss_clock) ;
wire r_dcdaten;
Mflipflop_r_1 dcdaten_ff_1(r_dcdaten,mm_dcdaten,~ss_reset,ss_clock) ;
wire r_sb_data_avail;
Mflipflop_r_1 sb_data_avail_ff_1(r_sb_data_avail,sb_data_avail,~ss_reset,ss_clock) ;
wire drd_c1 ; // forward
wire r_drd_c1;
Mflipflop_r_1 drd_c1_ff_1(r_drd_c1,drd_c1,~ss_reset,ss_clock) ;
wire sb_ic_op_hld = mm_cpcyc_stb_l & ~iccfstb_marb;
wire r_sb_ic_op;
MflipflopR_1 sb_ic_op_ff_1(r_sb_ic_op,mm_istat_avail,ss_clock,sb_ic_op_hld,ss_reset) ;
wire [31:0] m_state;
wire [10:0] a_state;
/*****************************************************************************/
/*** State Machine Function **************************************************/
function[31:0] next_m_state;
input r_mbsy;
input mc_mbsy;
input afx_qbusy;
input r_sb_ic_op;
input r_misc_bsy;
input r_sbsy;
input mc_mstb_l;
input r_mstb_l;
input r_tw_par;
input mop_c_bit;
input tw_read_req;
input tw_write_req;
input r_sb_par;
input sb_write;
input sb_data_avail;
input r_dc_par;
input wb_valid_x;
input read_w;
input r_ic_par;
input r_memfb_space;
input r_memcs_space;
input r_mem_space;
input r_fb_space;
input r_io_space;
input r_cntl_space;
input write_x;
input r_dcdaten;
input std_x;
input [3:0] mop_mreq;
input r_srd_ioreq;
input [3:0]r_sb_ioreq;
input ldsto_x;
input ldd_w;
input r_trap_w;
input fp_ld_mask;
input [31:0] m_state;
begin
next_m_state = 32'b0; /* set to default */
case (1'b1) // synopsys full_case parallel_case
m_state == 32'b0: next_m_state[IDLE] = 1'b1;
/*** IDLE state **************************************************************/
m_state[IDLE]:
case(1'b1) // synopsys full_case parallel_case
/** MMU tablewalk memory read/write op *********************/
(r_tw_par & (tw_read_req | tw_write_req) &
~r_misc_bsy & ~sb_data_avail):
next_m_state[MRD] = 1'b1;
/** SBC DMA memory read op *********************************/
(r_sb_par & r_srd_ioreq & r_memfb_space &
~r_misc_bsy ):
next_m_state[SB_RD] = 1'b1;
/** SBC DMA write op (assert mm_iodaten) *******************/
(r_sb_par & sb_write & ~r_misc_bsy & ~mc_mbsy):
next_m_state[SB_WR0] = 1'b1;
/** SBC Control Space read/write op ************************/
(r_sb_par & r_srd_ioreq & r_cntl_space &
~r_misc_bsy ):
next_m_state[SB_RD_CS] = 1'b1;
/** D-cache memory read op *********************************/
(r_dc_par & (read_w | (write_x & ~wb_valid_x)) &
(r_mem_space | (r_fb_space & ~afx_qbusy)) &
~wb_valid_x & ~r_misc_bsy & ~sb_data_avail):
next_m_state[DRD_C1] = 1'b1;
/** D-cache I/O space read op ******************************/
(r_dc_par & read_w & ~wb_valid_x & r_io_space &
~fp_ld_mask & ~r_sbsy):
next_m_state[DRD_IO] = 1'b1;
/** D-cache Control space read op **************************/
(r_dc_par & r_cntl_space &
(read_w | (write_x & wb_valid_x & r_dcdaten)) &
~r_misc_bsy & ~fp_ld_mask & ~sb_data_avail):
next_m_state[DRD_CS] = 1'b1;
/** D-cache memory write op ********************************/
/** note: ~std_x issue_req in this cycle. ************/
/** std_x issue_req in DWR state. ************/
(r_dc_par & wb_valid_x & r_dcdaten & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy)) &
((std_x & ~mc_mbsy) | (~std_x & ~r_misc_bsy))):
next_m_state[DWR] = 1'b1;
/** D-cache I/O space write op *****************************/
/** note: ~std_x issue_req in this cycle. ************/
/** std_x issue_req in DWR state. ************/
(r_dc_par & wb_valid_x &
r_io_space & r_dcdaten & ~r_sbsy):
next_m_state[DWR] = 1'b1;
/** I-cache memory read op *********************************/
(r_ic_par & ~r_misc_bsy & ~sb_data_avail) &
(r_mem_space | (r_fb_space & ~afx_qbusy)) :
next_m_state[IRD_C1] = 1'b1;
/** I-cache I/O space read op ******************************/
/** ?need to add error if an cntl_space address? ********/
(r_ic_par & r_io_space & ~r_sbsy):
next_m_state[IRD_IO] = 1'b1;
/** PIO data valid for D-cache (sb_ioreq == 4'b0010) *******/
(sb_data_avail & ~r_misc_bsy & ~r_sb_ic_op):
next_m_state[DRD_IOD] = 1'b1;
/** PIO data valid for I-cache (sb_ioreq == 4'b0010) *******/
(sb_data_avail & ~r_misc_bsy & r_sb_ic_op):
next_m_state[IRD_IOD] = 1'b1;
/** Default case - stay in IDLE ****************************/
(~((r_tw_par & (tw_read_req | tw_write_req) &
~r_misc_bsy & ~sb_data_avail)|
(r_sb_par & r_srd_ioreq & r_memfb_space & ~r_misc_bsy )|
(r_sb_par & sb_write & ~r_misc_bsy & ~mc_mbsy)|
(r_sb_par & r_srd_ioreq & r_cntl_space & ~r_misc_bsy )|
(r_dc_par & (read_w | (write_x & ~wb_valid_x)) &
(r_mem_space | (r_fb_space & ~afx_qbusy)) &
~wb_valid_x & ~r_misc_bsy & ~sb_data_avail)|
(r_dc_par & read_w & ~wb_valid_x & r_io_space & ~r_sbsy)|
(r_dc_par & r_cntl_space &
(read_w | (write_x & wb_valid_x & r_dcdaten)) &
~r_misc_bsy & ~sb_data_avail)|
(r_dc_par & wb_valid_x & r_dcdaten & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy)) &
((std_x & ~mc_mbsy) | (~std_x & ~r_misc_bsy)))|
(r_dc_par & wb_valid_x &
r_io_space & r_dcdaten & ~r_sbsy )|
(r_ic_par & ~r_misc_bsy & ~sb_data_avail &
(r_mem_space | (r_fb_space & ~afx_qbusy))) |
(r_ic_par & r_io_space & ~r_sbsy)|
(sb_data_avail & ~r_misc_bsy & ~r_sb_ic_op)|
(sb_data_avail & ~r_misc_bsy & r_sb_ic_op))):
next_m_state[IDLE] = 1'b1;
endcase
/*****************************************************************************/
/*** MRD state *** MMU tablewalk read/write state ****************************/
m_state[MRD]:
case(1'b1) // synopsys full_case parallel_case
/** Tablewalk memory write (request) ***********************/
(~tw_read_req):
next_m_state[IDLE] = 1'b1;
/** Tablewalk memory read - data valid *********************/
(tw_read_req & ~r_mstb_l):
next_m_state[IDLE] = 1'b1;
/** Tablewalk memory read - waiting ************************/
(tw_read_req & r_mstb_l):
next_m_state[MRD] = 1'b1;
endcase
/*****************************************************************************/
/*** SB_RD state *** SBC DMA read memory state *******************************/
m_state[SB_RD]:
case(1'b1) // synopsys full_case parallel_case
/** SBC DMA read - waiting for data ************************/
(r_mstb_l):
next_m_state[SB_RD] = 1'b1;
/** SBC DMA read 4/8 words - data valid ********************/
(~r_mstb_l & ~(mop_mreq == RD64)):
next_m_state[SB_RD2] = 1'b1;
/** SBC DMA read word - data valid *************************/
(~r_mstb_l & (mop_mreq == RD64)):
next_m_state[IDLE] = 1'b1;
endcase
/*****************************************************************************/
/*** SB_RD2 state *** SBC DMA read memory state (word 2) *********************/
m_state[SB_RD2]:
case(1'b1) // synopsys full_case parallel_case
/** SBC DMA read - waiting for data ************************/
(r_mstb_l):
next_m_state[SB_RD2] = 1'b1;
/** SBC DMA read 8 words - data valid **********************/
(~r_mstb_l & (mop_mreq == RD256)):
next_m_state[SB_RD3] = 1'b1;
/** SBC DMA read 4 words - data valid **********************/
(~r_mstb_l & ~(mop_mreq == RD256)):
next_m_state[IDLE] = 1'b1;
endcase
/*****************************************************************************/
/*** SB_RD3 state *** SBC DMA read memory state (word 3) *********************/
m_state[SB_RD3]:
case(1'b1) // synopsys full_case parallel_case
/** SBC DMA read - waiting for data ************************/
(r_mstb_l):
next_m_state[SB_RD3] = 1'b1;
/** SBC DMA read 6 words - data valid **********************/
(~r_mstb_l):
next_m_state[SB_RD4] = 1'b1;
endcase
/*****************************************************************************/
/*** SB_RD4 state *** SBC DMA read memory state (word 4) *********************/
m_state[SB_RD4]:
case(1'b1) // synopsys full_case parallel_case
/** SBC DMA read - waiting for data ************************/
(r_mstb_l):
next_m_state[SB_RD4] = 1'b1;
/** SBC DMA read 8 words - data valid **********************/
(~r_mstb_l):
next_m_state[IDLE] = 1'b1;
endcase
/*****************************************************************************/
/*** SB_WR0 state *** SBC DMA write memory state (word 0) ********************/
m_state[SB_WR0]:
next_m_state[SB_WR1] = 1'b1;
/*****************************************************************************/
/*** SB_WR1 state *** SBC DMA write memory state (word 1) ********************/
/*** *** Assert mm_issue_req in this cycle ********************/
m_state[SB_WR1]:
if (r_sb_ioreq == SWR_4W)
next_m_state[SB_WR2] = 1'b1;
else
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** SB_WR2 state *** SBC DMA write memory state (word 2) ********************/
m_state[SB_WR2]:
next_m_state[SB_WR3] = 1'b1;
/*****************************************************************************/
/*** SB_WR3 state *** SBC DMA write memory state (word 3) ********************/
m_state[SB_WR3]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** SB_RD_CS state *** SBC readControl Space state **************************/
m_state[SB_RD_CS]:
next_m_state[SB_RD_CS2] = 1'b1;
/*****************************************************************************/
/*** SB_RD_CS2 state *** SBC read Control Space state (data transfer) ********/
m_state[SB_RD_CS2]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** DRD_C1 state *** D-cache read memory state (word pair 1) ****************/
m_state[DRD_C1]:
case(1'b1) // synopsys full_case parallel_case
/** D-cache read - non-cached & atomic *********************/
(ldsto_x & ~mc_mstb_l):
next_m_state[D_ATOMIC] = 1'b1;
/** D-cache read - cached & ~atomic ************************/
(mop_c_bit & ~mc_mstb_l & ~ldsto_x):
next_m_state[DRD_C2] = 1'b1;
/** D-cache read - non-cached & ~atomic ********************/
(~mop_c_bit & ~mc_mstb_l & ~ldsto_x):
next_m_state[IDLE] = 1'b1;
/** D-cache read - wait for data ***************************/
(mc_mstb_l):
next_m_state[DRD_C1] = 1'b1;
endcase
/*****************************************************************************/
/*** DRD_C2 state *** D-cache read memory state (word pair 2) ****************/
m_state[DRD_C2]:
case(1'b1) // synopsys full_case parallel_case
(~mc_mstb_l):
next_m_state[IDLE] = 1'b1;
/** D-cache read - wait for data ***************************/
(mc_mstb_l):
next_m_state[DRD_C2] = 1'b1;
endcase
/*****************************************************************************/
/*** DRD_IO state *** D-cache read I/O space state **************************/
m_state[DRD_IO]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** DRD_IOD state *** D-cache read I/O space state (data 0) *****************/
m_state[DRD_IOD]:
case(1'b1) // synopsys full_case parallel_case
/** D-cache (ldd) read I/O space ***************************/
(ldd_w):
next_m_state[DRD_IOD2] = 1'b1;
/** D-cache read I/O space *********************************/
(~ldd_w & ~ldsto_x):
next_m_state[DRD_IOD3] = 1'b1;
/** D-cache read I/O space (atomic) ************************/
(~ldd_w & ldsto_x):
next_m_state[D_ATOMIC] = 1'b1;
endcase
/*****************************************************************************/
/*** DRD_IOD2 state *** D-cache read I/O space state (data 1) ****************/
m_state[DRD_IOD2]:
next_m_state[DRD_IOD3] = 1'b1;
/*****************************************************************************/
/*** DRD_IOD3 state *** D-cache read I/O space state (data 1) ****************/
m_state[DRD_IOD3]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** D_ATOMIC state *** D-cache Atomic op state ******************************/
m_state[D_ATOMIC]:
if ((r_dcdaten & wb_valid_x & r_io_space & ~r_sbsy & ~r_trap_w) |
(r_dcdaten & wb_valid_x & ~r_misc_bsy &
(r_mem_space | (r_fb_space & ~afx_qbusy))))
next_m_state[DWR] = 1'b1;
else if (r_trap_w & r_io_space)
next_m_state[IDLE] = 1'b1;
else
next_m_state[D_ATOMIC] = 1'b1;
/*****************************************************************************/
/*** DWR state *** D-cache write memory or I/O space state *******************/
m_state[DWR]:
next_m_state[DWR_DONE] = 1'b1;
/*****************************************************************************/
/*** DWR_DONE state *** D-cache write memory or I/O space Done state *********/
/*** *** [Do we really need this state?? - keep for now 5/18]**/
m_state[DWR_DONE]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** DRD_CS state *** D-cache read/write Control Space state *****************/
m_state[DRD_CS]:
case(1'b1) // synopsys full_case parallel_case
/** D-cache Control Space write ****************************/
(wb_valid_x):
next_m_state[DWR_CS] = 1'b1;
/** D-cache Control Space read *****************************/
(~wb_valid_x):
next_m_state[DRD_IOD2] = 1'b1;
endcase
/*****************************************************************************/
/*** DWR_CS state *** D-cache write Control Space state **********************/
m_state[DWR_CS]:
next_m_state[DWR_CS1] = 1'b1;
/*****************************************************************************/
/*** DWR_CS state *** D-cache write Control Space state **********************/
m_state[DWR_CS1]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** IRD_C1 state *** I-cache read memory state (word pair 1) ****************/
m_state[IRD_C1]:
case(1'b1) // synopsys full_case parallel_case
/** I-cache non-cached access (memory) *********************/
(~mop_c_bit & ~mc_mstb_l):
next_m_state[IDLE] = 1'b1;
/** I-cache cached access (line fill) **********************/
(mop_c_bit & ~mc_mstb_l):
next_m_state[IRD_C2] = 1'b1;
/** I-cache access *****************************************/
(mc_mstb_l):
next_m_state[IRD_C1] = 1'b1;
endcase
/*****************************************************************************/
/*** IRD_C2 state *** I-cache read memory state (word pair 2) ****************/
m_state[IRD_C2]:
case(1'b1) // synopsys full_case parallel_case
/** I-cache cached access (line fill) **********************/
(~mc_mstb_l):
next_m_state[IRD_C3] = 1'b1;
/** I-cache access *****************************************/
(mc_mstb_l):
next_m_state[IRD_C2] = 1'b1;
endcase
/*****************************************************************************/
/*** IRD_C3 state *** I-cache read memory state (word pair 3) ****************/
m_state[IRD_C3]:
case(1'b1) // synopsys full_case parallel_case
/** I-cache cached access (line fill) **********************/
(~mc_mstb_l):
next_m_state[IRD_C4] = 1'b1;
/** I-cache access *****************************************/
(mc_mstb_l):
next_m_state[IRD_C3] = 1'b1;
endcase
/*****************************************************************************/
/*** IRD_C4 state *** I-cache read memory state (word pair 4) ****************/
m_state[IRD_C4]:
case(1'b1) // synopsys full_case parallel_case
/** I-cache cached access (line fill) **********************/
(~mc_mstb_l):
next_m_state[IDLE] = 1'b1;
/** I-cache access *****************************************/
(mc_mstb_l):
next_m_state[IRD_C4] = 1'b1;
endcase
/*****************************************************************************/
/*** IRD_IO state *** I-cache read I/O space state ***************************/
m_state[IRD_IO]:
next_m_state[IDLE] = 1'b1;
/*****************************************************************************/
/*** IRD_IOD state *** I-cache read I/O space state (word 0) *****************/
m_state[IRD_IOD]:
next_m_state[IRD_IOD2] = 1'b1;
/*****************************************************************************/
/*** IRD_IOD2 state *** I-cache read I/O space state (word 1) ****************/
m_state[IRD_IOD2]:
next_m_state[IRD_IOD3] = 1'b1;
/*****************************************************************************/
/*** IRD_IOD3 state *** I-cache read I/O space cleanup ****************/
m_state[IRD_IOD3]:
next_m_state[IDLE] = 1'b1;
endcase /* state decode case */
end
endfunction /* marb_sm */
/*****************************************************************************/
/*** Instantiate marb_sm *****************************************************/
wire[31:0] m_state_in = next_m_state(r_mbsy, mc_mbsy, afx_qbusy,
r_sb_ic_op, r_misc_bsy,
r_sbsy, mc_mstb_l, r_mstb_l, r_tw_par,mop_c_bit,
tw_read_req, tw_write_req, r_sb_par, sb_write,
sb_data_avail, r_dc_par, wb_valid_x, read_w,
r_ic_par,
r_memfb_space, r_memcs_space, r_mem_space, r_fb_space,
r_io_space, r_cntl_space,
write_x,r_dcdaten, std_x, mop_mreq,
r_srd_ioreq, r_sb_ioreq, ldsto_x, ldd_w, r_trap_w,
fp_ld_mask, m_state) ;
/*** marb_sm state registers ************************************************/
Mflipflop_r_32 memarbsm_reg_32(m_state,m_state_in,~ss_reset,ss_clock) ;
/*****************************************************************************/
/*** Output Decodes (marb_sm related) ****************************************/
/*** Main memory issue request ***********************************************/
/*** IDLE -> MRD - MMU tablewalk read ***/
/*** -> SB_RD - DMA (SBC) read ***/
/*** -> DRD_C1 - D-cache read ***/
/*** -> DWR - D-cache write (~std) to memory ***/
/*** -> IRD_C1 - I-cache read ***/
/*** DWR -> DWR_DONE - D-cache write (std) to memory ***/
/*** SB_WR1 -> IDLE/SB_WR2 - Any DMA (SBC) write to memory ***/
/*** D_ATOMIC-> DWR - D-cache write to memory ***/
assign mem_issue_req =
(m_state[IDLE] &
((r_tw_par & tw_read_req & ~r_misc_bsy & ~sb_data_avail) |
(r_sb_par & r_srd_ioreq & r_memfb_space & ~r_misc_bsy) |
(r_dc_par & (read_w | (write_x & ~wb_valid_x)) &
~wb_valid_x & ~r_misc_bsy & ~sb_data_avail &
| This page: |
Created: | Thu Aug 19 12:02:56 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/rl_marb_sm.v
|