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Xilinx Answer #100 : Xilinx Libraries: All Xilinx/Viewlogic components have a LEVEL= attribute to decrease runtime
Xilinx Answer #101 : Viewsim: About ? Nodes in Timing Simulations
Xilinx Answer #102 : FPGA Configuration: DONE Doesn't Go High; General XC4000 Debugging Hints
Xilinx Answer #103 : XC4000: The Five Configurations of TBUFs
Xilinx Answer #105 : Initializing QuickSim simulation: Net names for the global reset signal
Xilinx Answer #106 : XC3100:Timing of Direct Connects
Xilinx Answer #107 : XC4000: Table of Connections To and From BUFGP and BUFGS
Xilinx Answer #109 : PROcapture: Do not remove the security key during the middle of a session
Xilinx Answer #110 : Viewlogic Simulation: Forcing a value to a signal and then releasing will cancel any FLOATVAL attributes
Xilinx Answer #114 : XC2000/XC3000/XC4000/XC5200: About decoupling capacitors for FPGAs
Xilinx Answer #116 : XC3000/XC4000: Can I source ACLK/GCLK from internal logic? BUFGS, BUFGP?
Xilinx Answer #120 : VST gets stuck or stalls while simulating
Xilinx Answer #121 : XC3000/XC4000: Pin sense of internal tristate buffers
Xilinx Answer #122 : XC3000/XC4000: Using latches in 3k and 4k designs
Xilinx Answer #123 : XC4000: Use NODELAY attribute to get (fast) Input FF databook speed w/o delay
Xilinx Answer #124 : FPGA Configuration:init goes low, addresses keep incrementing (master parallel)
Xilinx Answer #126 : XC3000/XC4000/XC4000: Clock Buffers- (ACLK GCLK BUFGP BUFGS): When to use them
Xilinx Answer #127 : PACKAGES: Sources and information for sockets, contactors, receptacles, lead forming.
Xilinx Answer #128 : ViewSim: Global reset signal names for 2k, 3k, 4k, 5k, 7k, and 9k (startup)
Xilinx Answer #130 : Mentor 8.x: PLD_DA can't instantiate components, parts come up blank
Xilinx Answer #134 : FPGA CONFIGURATION: Effect of power-glitch invoked reset on XC2000/3000 devices
Xilinx Answer #135 : WIR2XNF:SEC:license not found For product GENERIC Error 4:iwinit failure
Xilinx Answer #136 : PROMS: AT&T flash serial proms cannot FAST configure an XC4000 device
Xilinx Answer #138 : PROMS: How to program a 'D' type prom from a different type master prom
Xilinx Answer #139 : Data I/O Tech Support and BBS numbers
Xilinx Answer #140 : XC4000: weight of 4005CB164 in Military B package - 11.5 grams
Xilinx Answer #141 : QuickSim: Unable to resolve expression symbol lca_technology, NULL modelwill be inserted
Xilinx Answer #143 : BOUNDARY SCAN/JTAG: XC4000 /INIT pin state during boundary scan
Xilinx Answer #144 : PACKAGES: PACKAGING- Plastic packages are not hermetic.
Xilinx Answer #146 : VIEWLOGIC programs report no license for symbol or schematic
Xilinx Answer #147 : XC2000/XC3000: Can the crystal oscillator be used before configuration?
Xilinx Answer #149 : FPGA Configuration: How to reconfigure one 3k/4k device out of a daisy chain
Xilinx Answer #150 : XC3000, XC4000:Can the longline weak keeper circuit in be used as a storage element?
Xilinx Answer #151 : XC2000/XC3000/XC4000/XC5200: What set, reset capabilities do the 2000. 4000, 5200 flip flops have?
Xilinx Answer #152 : FPGA: Default configuration of 2000, 3000, 4000 family IOBs (pullup)
Xilinx Answer #154 : XC4000H: Computing output transition time for 4000H
Xilinx Answer #155 : PLD_DA Check: Unable to evaluate property, unable to resolve lca_technology
Xilinx Answer #157 : FPGA Configuration: time to get off D7 after rs, before RDY/BUSY in async periph
Xilinx Answer #158 : XC4000 Configuration: Done goes high but outputs never become active
Xilinx Answer #159 : XNF file created by EDIF2XNF contains high-level symbols instead of primitives
Xilinx Answer #160 : PACKAGING: What is the lead finish for the various packages?
Xilinx Answer #161 : How to see more of the error messages in PROcapture status window
Xilinx Answer #163 : XC2000/XC4000/XC5200- I/O pullup/pulldown availability
Xilinx Answer #164 : PROMS: What is the difference between a 1736A and 1736M part?
Xilinx Answer #165 : 93 DATA BOOK: Error in boundary scan order for 4004a on p. 2-77
Xilinx Answer #168 : VST or VST386+ gives ''error, unable to load primitives''
Xilinx Answer #173 : XC4000/A: XC4000 and XC4000A bitstreams are NOT compatible!
Xilinx Answer #174 : SYNOPSYS/XSI: Using an Input Latch (ILD_1) with No Delay
Xilinx Answer #175 : XC4000H: Why are there two tristate pins (TP and TS ) on the 4000H IOBs?
Xilinx Answer #177 : XC4000: How are 4000A parts different from 4000 parts?
Xilinx Answer #178 : XC4000: What values do rams contain immediately after configuration?
Xilinx Answer #179 : Can an old 2020 .PRG file be used to program the 7272 parts?
Xilinx Answer #181 : FPGA CONFIGURATION: Serial slave mode, PROM file:Shift LSB or MSB first?
Xilinx Answer #183 : PROwave: Viewing an arbitrary set of signals as a bus in the waveform window
Xilinx Answer #188 : PROMS: addresses for controlling programmable resets / reset polarity ofXilinx PROMs (Data I/O programmers only)
Xilinx Answer #189 : Licensing: Forcing XACT License programs to use LM_LICENSE_FILE (Not forM1 version of software)
Xilinx Answer #191 : BOUNDARY SCAN/JTAG: Using TI ASSET tester with Xilinx BSDL files (Instruction_Private)
Xilinx Answer #194 : BOUNDARY SCAN/JTAG: How to use EXTEST instruction before configuration in a XC4K/XC5K device?
Xilinx Answer #204 : XC4000, XC4000E Ground bounce app note is available
Xilinx Answer #205 : SYNOPSYS/XSI 5.2.1: How to use it with and without X-BLOX libraries.
Xilinx Answer #208 : 94 DATA BOOK: Error, p2-165 1994 data book on 3064a -6, Tcko
Xilinx Answer #209 : 94 DATA BOOK: TCLKIN missing from 3030VQ64 pinout
Xilinx Answer #210 : XC4000/XC5200: Definition of DRCK on the BSCAN symbol
Xilinx Answer #214 : 94 DATA BOOK: DATA 4 (I) missing on page 2-43 of 1994 data book
Xilinx Answer #216 : XBLOX gives error "Cannot create XIF" on Concept design
Xilinx Answer #217 : CADENCE/CONCEPT 9402: GXILINX does not write EXT records to the XNF file
Xilinx Answer #218 : Powerview: values not displayed on schematic during simulation
Xilinx Answer #219 : Global reset signal name for FPGAs/EPLDs
Xilinx Answer #221 : What format is the .PRG file?
Xilinx Answer #223 : 94 DATA BOOK 3rd: error in 4005pq160 pinout, p. 2-57
Xilinx Answer #225 : CADENCE GXILINX: APR/PPR guide may not work on pre-Unified Concept designs translated by GXilinx
Xilinx Answer #226 : VHDL: Implementing the XC3000/XC4000 readback function.
Xilinx Answer #228 : XC4000: capacitance of XC4000 inputs
Xilinx Answer #230 : 94 DATA BOOK 2nd: Presettable Down Counter on page 8-72 is misdrawn
Xilinx Answer #231 : HW-120 : Unable to find programmer, stuck in "Waiting for CTS" or "downloading" mode
Xilinx Answer #233 : SDT 386+ issues error: handler_.exe failed
Xilinx Answer #234 : 94 DATA BOOK: 4005H boundary scan pinout incomplete page 2-101
Xilinx Answer #236 : 94 DATA BOOK: 4010 pinouts missing reference to DOUT page 2-63
Xilinx Answer #237 : Programming XC7000 part with a JEDEC file gives checksum error
Xilinx Answer #239 : BOUNDARY SCAN/JTAG: Preventing inadvertent activation of boundary scan in XC4K/XC5K devices
Xilinx Answer #240 : PROcapture: Do not use RAM16.1, RAM32.1, ROM16.1, and ROM32.1 components
Xilinx Answer #242 : Emulating Boundary Scan in a 3000 device
Xilinx Answer #246 : VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000`reset' flip-flop
Xilinx Answer #250 : XDM fails, 'can't find termcap.xct, aborting'
Xilinx Answer #251 : Viewsim:ERROR:Multiple conflicting floatval attributes
Xilinx Answer #253 : XSIMMAKE may hang up while running CHECK if viewdraw.ini has invalid library
Xilinx Answer #254 : XACT 5 software won't work with pre-XACT 5 license programs 'invalid data'
Xilinx Answer #258 : ABL2XNF issues error, 'can't find <design>.bl0
Xilinx Answer #259 : 94 DATA BOOK has incorrect pinout for 73108 EPLD pin 160
Xilinx Answer #260 : XBLOX 5.x: Implementing DATA_REG in IOB resources
Xilinx Answer #265 : XACT 5 install:It is possible to install place and route tools but not packages
Xilinx Answer #267 : XPP 5.0.0: -d option programs proms incorrectly if .bit file is split across multiple proms
Xilinx Answer #268 : XACT 5 license manager 'invalid data' error messages
Xilinx Answer #269 : XABEL 5.0, ERROR 12500: Make sure you have environment variable set
Xilinx Answer #270 : 7318/7336 inverted input in UIM causes warning 205
Xilinx Answer #271 : Minimum delay specifications for Xilinx devices.
Xilinx Answer #277 : Processing multi-page flat OrCAD designs.
Xilinx Answer #278 : SDT 4.xx gives error: 'library header is incorrect'
Xilinx Answer #280 : SDT2XNF error 014, or xdraft 5.0: error 003; ds35 not installed
Xilinx Answer #281 : SDT2XNF 'error 033, no standard libraries used'
Xilinx Answer #284 : PPR 5.2: What are the SaveSig (S), eXternal (X) netflags?
Xilinx Answer #285 : PPR 5.2: Memory requirements for various parts
Xilinx Answer #287 : XDM, PPR 5.2: XDM forces the use of invalid default TIMESPEC syntax
Xilinx Answer #288 : 94 DATA BOOK: 4005Hpg223 pinout missing pins L15 and L3 PAGE 2-101
Xilinx Answer #289 : Workstation licensing: possible cause of 'cannot open DAEMON LOCK FILE'
Xilinx Answer #292 : Mentor Version 8 Interface User Guide (April 1994): erroneous statement on page 11-63
Xilinx Answer #293 : XABEL 5.0: How to change colors on Sun version
Xilinx Answer #294 : SDT2XNF, INF2XNF ERROR 1, internal program error, code 0, return code 3
Xilinx Answer #297 : PPR 5.0: Information for users upgrading from APR for 3000A designs
Xilinx Answer #303 : PPR 5.0: About 'HEAPMGMT - heap error #6' under windows DOS shell
Xilinx Answer #305 : SYMGEN 5.2, XDM 5.2: XDM Appears to hang when SYMGEN is invoked
Xilinx Answer #308 : Mentor 8: Using XACT 5 Timespec, TNM on an old library XC3000A/XC4000 design
Xilinx Answer #310 : FITNET DRC error, flip flop using both SET and RESET
Xilinx Answer #311 : PPR 5.0: PPR Error 9062: Global Buffer Driven by IO, IBUF
Xilinx Answer #314 : XBLOX 5.x: Error message regarding CAST (20051, 20141, 20142, 20184, 20177, 20199, 20336)
Xilinx Answer #315 : XBLOX 5.x: I/O signals disappear in simulation
Xilinx Answer #316 : Xsimmake 5.2: Error message says to run functional simulation
Xilinx Answer #317 : XBLOX 5.x models DATA_REG of STYLE=ILD as flip-flops in functional simulation
Xilinx Answer #318 : XBLOX 5.0: Internal error 20156 due to single bits connecting through busses
Xilinx Answer #320 : XBLOX 5.x: XC3000A data registers not mapped with combinational logic
Xilinx Answer #322 : XKEY 5.0 will not run on machines that don't have math coprocessors
Xilinx Answer #324 : XABEL 5.0: How to do standalone designs
Xilinx Answer #325 : XBLOX 5.x issues error 20066: "The specified Part type <part> is unknown"
Xilinx Answer #326 : PPR 5.0: Methods to reduce PPR runtime
Xilinx Answer #328 : PPR 5.0: CST file constraints do not override schematic constraints
Xilinx Answer #329 : XACT 5.x Design Architect: calling up old design gives "cannot determineversion" error
Xilinx Answer #335 : 94 DATA BOOK 3rd: TQ176 package dimensions on page 4-18 are incorrect
Xilinx Answer #340 : XACT 5.0 Programmable Key: May not be recognized/transparent on some machines
Xilinx Answer #341 : xnf2wir 5.0: VSM gives 'ER Error - Could not find WIR file startup.1.'
Xilinx Answer #345 : PPR 5.0: Getting report of timespec failed paths BEFORE routing phase
Xilinx Answer #348 : 94 DATA BOOK: P 2-68 incorrectly list 4025 as available in mq208, not inpq223
Xilinx Answer #350 : Quicksim, XACT 5: Functional simulation of carry-logic macros may glitch
Xilinx Answer #351 : VIEWSIM Error, XC7000 EPLD: Could not find WIR file xc7000:pl22v10.1
Xilinx Answer #352 : SDT2XNF Error 16 issued, but no filename given
Xilinx Answer #354 : Behavioral blocks in EPLD schematic are not being updated
Xilinx Answer #357 : ABL2XNF 5.0:AHDL2X gives Error 0250 [XLM:AUTHORIZATION_FAILURE]
Xilinx Answer #360 : PPR 5.0: Possible cause of Segmentation or Memory Protection faults (TNMs)
Xilinx Answer #361 : PPR 5.0: Notplace * constraint with MD0, MD1 pins gives errors 9016, 9034
Xilinx Answer #362 : What is the fastest pin to pin delay?
Xilinx Answer #363 : Synthx 5.0 may report ignoring maxclbs option even though it uses it
Xilinx Answer #364 : PROMS: AT&T flash proms may sometimes put out incorrect data
Xilinx Answer #366 : XMAKE 5.2:Error 3515,3516 about mixed libraries when -L used on old design
Xilinx Answer #370 : XDELAY 5.2: Correlating delays through TBUFs with data book values
Xilinx Answer #371 : XABEL 5.0, SYMGEN 5.0: pins are absent from symbol with istype 'reg,invert'
Xilinx Answer #372 : XDM 5.2: Symgen does not appear in menus if XC7200 or XC7300 part is selected
Xilinx Answer #376 : Possible cause of 'pld pds files not found'
Xilinx Answer #377 : XDM 5.0 only allows you to set APR seed value of 0-99
Xilinx Answer #378 : XACT 5: Using ViewSim to simulate board-level epld design
Xilinx Answer #382 : PPR 5.0: May ignore MAP=PLC on XC3000A CLBMAP symbols
Xilinx Answer #384 : AHDL2X 5.02: 'Assertion failed' error due to > 128 states
Xilinx Answer #386 : SYNTHX 5.0: Possible cause of 'pin was not defined', design worked in last rev
Xilinx Answer #387 : XKEY 5.0: Possible workaround for [XLM:KEY_NOT_FOUND]|
Xilinx Answer #390 : GEN_SCH8 5.x: Can't open shared lib /tools/idea/lib/libC.sl
Xilinx Answer #391 : PLD_DA/Design Architect: "Error: Attempt to connect failed (for child ofschematic named schematic)"
Xilinx Answer #392 : XSIMMAKE 5.2, Viewlogic: Possible cause of ERROR 7
Xilinx Answer #396 : EDIF2XNF 5.x: Error 3, port name not found on external library primitivefor cell
Xilinx Answer #397 : EDIF2XNF 5.x: S Netflag does not save unconnected nets and symbols
Xilinx Answer #399 : EDIF2XNF 5.x: Error 5, no direction/pintype for port (possibly Autologic)
Xilinx Answer #400 : XSIMMAKE/XDRAW 5.2: XSIMMAKE seemingly halts exectution during XDRAW
Xilinx Answer #402 : XBLOX 5.x and Viewsim/PROsim: Possible cause of contention ("X" values) on busses
Xilinx Answer #403 : Workstation licensing, XACT 5.0: Use XLMCON to debug them.
Xilinx Answer #408 : Xilinx Programmable key: (In)compatiblity information from key vendor
Xilinx Answer #409 : PPR 5.2: Defining point-to-point timespecs in cst file
Xilinx Answer #412 : PPR 5.0: PPR (possibly other programs) gives PHARLAP error when invoked
Xilinx Answer #416 : PPR 5.0: using XDE-EDITLCA colorblk command in guide file may cause error 12205
Xilinx Answer #417 : PROwave: Dynamic annotation of signal values in PROcapture stored in PROwave
Xilinx Answer #418 : SDT2XNF CLB equation(EQUATE) translates incorrectly into xnf netlist, XNFPREP Error 4074,4066
Xilinx Answer #419 : PPR 5.0: Constraining RPMs in a CST file (includes RPMCON instructions)
Xilinx Answer #420 : PPR 5.0: TNM placed on a net does not get traced forward to all elements
Xilinx Answer #421 : XABEL 5.0: How to optimize your XABEL design to use IOB flip-flops
Xilinx Answer #424 : XABEL 5.0 and XC7000 EPLDS: The .D extension is not supported by PLUSASM
Xilinx Answer #425 : XABEL 5.0: Making a registered preset signal
Xilinx Answer #426 : XABEL 5.0, XC7000 EPLD: Trouble accessing D1 and D2 alu pins
Xilinx Answer #427 : SYNOPSYS FPGA COMPILER: To prevent Timespecs from apprearing in the XNF file.
Xilinx Answer #428 : VIEWSIM: How to fix 'Could not open VHDL file...', 'Unrecognized component...'
Xilinx Answer #429 : PLD_DA/EDIF2XNF 5.x: LOC properties placed on pads do not appear in netlist
Xilinx Answer #430 : Gen_sch8 5.x: possible cause of error 396: could not find pin SD on symbol DFF
Xilinx Answer #431 : XNFPREP: Possible cause of 'ERROR 1303, comma required' on Orcad designs
Xilinx Answer #432 : How flip-flop initial states are determined
Xilinx Answer #434 : SYNOPSYS: Does Xilinx support VSS simulation?
Xilinx Answer #435 : PowerView,wir2xnf,xnf2wir: Working around 'SEC: host is not responding'
Xilinx Answer #436 : XPP 5.0: Why does it always ask for the "first" device?
Xilinx Answer #437 : PPR 5.0:Possible cause of 'Error 5805: Constraints to mapping symbol conflict'
Xilinx Answer #438 : SYNOPSYS: XNFPREP issues ERROR 3673 due to multiple clock buffers inserted.
Xilinx Answer #439 : 94 DATA BOOK: Error in PG299 Package Drawing, page 4-24
Xilinx Answer #440 : XC2000: XDE 5.0: About "Can't open 2018.spd" message.
Xilinx Answer #446 : Error "could not read design database"
Xilinx Answer #450 : 94 DATA BOOK 2nd: Which 7300 outputs have 24mA drive capability?
Xilinx Answer #452 : XNFPREP 5.0 issues error 7859 on a Timespec attribute.
Xilinx Answer #453 : SYN2XNF: Use of -s option causes creation of EXT records, XNFPREP Error 3527
Xilinx Answer #456 : Mentor Autologic: inserting PADs instead of PORTs causes XNFPrep ERROR 3527
Xilinx Answer #457 : XC4000 Readback: How to work around rdclk max high and low time specs
Xilinx Answer #459 : Use of /MR as input precludes use as reset, even during initialization
Xilinx Answer #460 : Slow VCC rise time does not require use of /MR as a 'hold-off'
Xilinx Answer #462 : XBLOX 5.x returns internal error 20104 on COUNTER module
Xilinx Answer #463 : PLD_DVE/PLD_DVE_Sim 5.x appears to hang
Xilinx Answer #464 : XSIMMAKE 5.2: XSIMMAKE may run XBLOX on a design even after you remove all XBLOX logic
Xilinx Answer #466 : PPR 5.0 will not guide correctly with a pre-XACT 5.0 lca file
Xilinx Answer #467 : XEMAKE: Schematic design changes are ignored
Xilinx Answer #470 : PPR issues ERROR 6105 due to XBLOX mapping down counter incorrectly
Xilinx Answer #471 : XBLOX 5.x: Internal error 20224: representation_error
Xilinx Answer #472 : Differences between the 7318/7336 and 7354/7372/73108/73144
Xilinx Answer #473 : Possible cause of Error 'tl2035 the xnf file cannont be read by XEMAKE'
Xilinx Answer #475 : Programmable Key: Programs issue XLM:KEY_NOT_FOUND in DOS shell in MS Windows
Xilinx Answer #476 : PROMS: About PROM/EEPROM file formats -- Intel MCS, Motorola EXOR, Tektronix HEX
Xilinx Answer #477 : XABEL 5.0,5.1:Key not recognized on fast PCs,AHDL2X gives XLM_KEY_NOT_FOUND
Xilinx Answer #478 : PPR 5.0 and Timespec: How to use the timespec 'ignore' property
Xilinx Answer #482 : XNF2WIR 5.x: Gives Error 210 if CY4 symbol is in design using pre XACT5 libs
Xilinx Answer #483 : PPR 5.0: Possible cause of Error 5607: Design has not been flattened
Xilinx Answer #484 : SDT2XNF: DS35-SDT-ERROR-032: Failed to add pin <pinname> of type 'U'
Xilinx Answer #485 : XNF2WIR ERROR 210 : could not load symbol of type [COULD_NOT_IDENTIFY]
Xilinx Answer #486 : VIEWSIM timing simulation: "x" on the output of flip flop. XSIMMAKE
Xilinx Answer #488 : SYNOPSYS/BSCAN: How to instantiate BSCAN in the 4k/5k in Verilog/VHDL inSynopsys(FPGA Compiler,Design Compiler,FPGA Express)
Xilinx Answer #489 : 94 DATA BOOK: page 2-148, 3090TQ176 pinout error: VSS (pin 133) is VCC
Xilinx Answer #492 : Min. pulse width on PROGRAM to reconfigure/reprogram a 4000(E) device is300ns.
Xilinx Answer #495 : XSIMMAKE 5.0, 5.1, 5.2: Possible cause of XNFBA error 301.
Xilinx Answer #499 : XC4000/XC5200: How accurate are the internal oscillators in these devices?
Xilinx Answer #500 : PPR, WIR2XNF 5.0: Possible cause of PPR error 9016: use of -f option
Xilinx Answer #503 : Workstation licensing: xlmasu gives 'no SERVER line' error, but line exists
Xilinx Answer #504 : CONCEPT2XNF 5.0: Does not translate Slew_rate=fast attribute
Xilinx Answer #505 : WIR2XNF 5.0: About 'Unexpected token design_may_contain_rippers_recompilation..'
Xilinx Answer #507 : Workstation Licensing: Using multiple license files at once
Xilinx Answer #508 : XC4000/XC5200: PROGRAM pin designed to ignore glitches <50nS)
Xilinx Answer #509 : Mentor Graphics 8.x on Sun workstations: F1 key gives Sun help instead of Mentor functions
Xilinx Answer #510 : CADENCE CONCEPT v9401, 9404, 9502 : plotting schematic sheets
Xilinx Answer #514 : PPR 5.1, XC3000A: PPR Routes 3000A Pip in the Wrong Direction
Xilinx Answer #515 : SYNOPSYS FPGA COMPILER: Problems reading an XNF file back into Synopsys.
Xilinx Answer #518 : XACT 5.X, Cadence VERILOG-XL: Performing Verilog simulation of Xilinx designs
Xilinx Answer #519 : 94 DATA BOOK 2nd Edition: P. 2-85, PG156 package is missing I/O (A6) pinnumber
Xilinx Answer #522 : VST/386+ Gives "Terminal Error - Incompatible Version of MODEL Files."
Xilinx Answer #524 : PPR 5.1: Use of 5.0 guide file with XBLOX counters causes ERROR 9081
Xilinx Answer #525 : PPR 5.0: produces ERROR 1173, 'can't find .tpm file for the NOTH_PICMAP cell'
Xilinx Answer #526 : MAKEPROM 5.1: 'Address is greater than 64k' error, using MCS format - what to do
Xilinx Answer #527 : PPR 5.1:Possible cause of ERROR 9015 on XC3000 design (placement constraints)
Xilinx Answer #530 : PPR 5.0,5.1: Possible cause of bad grouping using statements on TIMEGRP symbol
Xilinx Answer #533 : XC4000, SYNOPSYS FPGA Compiler: Example .synopsys_dc.setup file
Xilinx Answer #534 : XC4000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #537 : XC3000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #538 : XC7000, SYNOPSYS FPGA/Design Compiler: Example .synopsys_dc.setup file
Xilinx Answer #541 : XBLOX 5.x and View/PROsim: Finding and assigning values to XBLOX I/O (INPUTS, OUTPUTS, and BIDIR_IO)
Xilinx Answer #542 : XSI/SYNOPSYS: Constraining I/O pin locations from within Synopsys.
Xilinx Answer #543 : XABEL 5.1/EPLD designs: FOE pins are active *high*
Xilinx Answer #547 : MEN2XNF8 5.x: Could not find a registered simulation model with label: 'xc____'
Xilinx Answer #548 : SYNOPSYS/ XC3000/XC4000: How to force insertion of a BUFGP at a clock pad.
Xilinx Answer #549 : SYNOPSYS: How to invert the reset (GSR/GR) pin on the STARTUP block?
Xilinx Answer #550 : XBLOX 5.0/5.1: COUNTERs with different COUNT_TO values functionally simulate the same
Xilinx Answer #552 : VST: Possible cause of terminal error..."I" found as device pin number
Xilinx Answer #555 : Error es14 or es6: Too many shared D1 product terms
Xilinx Answer #556 : POWERVIEW 5.3.1, WIR2XNF 5.x:Error 4 'Couldn't find workview.msg in WDIR'
Xilinx Answer #557 : XBLXGS 5.x: possible cause of error "Bad status 79500182 from ddp_perform_check"
Xilinx Answer #558 : SDT2XNF fatal error DS35-SDT-ERROR-008: syntax error in inf file
Xilinx Answer #560 : XNFOUT: XBLOX PADNAME attribute not transmitted to XNF from Cadence Composer schematic
Xilinx Answer #561 : PROGRAMMABLE KEY: How to access Rainbow Technology technical support
Xilinx Answer #564 : FPGA COMPILER: PULLUPs/PULLDOWNs must be instantiated when using Synopsys.
Xilinx Answer #565 : VERILOG XL: About 'Warning! Implicit wire has no fanin [Verilog-IWFA]'
Xilinx Answer #566 : CONCEPT2XNF: Property RLOC_ORIGIN and RLOC_RANGE may be ignored by XNFMERGE (Warning 260)
Xilinx Answer #568 : 94 DATA BOOK 3rd: page 3-64, pinout error for 73144PQ160
Xilinx Answer #569 : XBLOX 5.x issues error 20107 on Protel design due to spaces in XNF PROG record
Xilinx Answer #573 : Various programs: internal error 1014 (message set error) caused by bad XACT/path variable
Xilinx Answer #575 : Design doesn't fit using 5.1, but used to fit with 5.0
Xilinx Answer #577 : XNF2WIR returns error 201 if viewdraw.ini is not in project directory
Xilinx Answer #583 : PROcapture 6.0: Iconified PROcapture automatically quits on MS Windows exit
Xilinx Answer #584 : PPR 5.x guide may leave clock enable on flip-flops where CE was removed (3000A)
Xilinx Answer #586 : PROsynthesis PC INSTALL: PC locks up/crashes while installing, possible cause
Xilinx Answer #587 : VIEWLOGIC SIMULATION: FXC2K, FXC3K, FXC4K, FXC7K libs give quicker simulation
Xilinx Answer #588 : PROCAPTURE: cannot recognize the Xilinx C key. (No valid license for product)
Xilinx Answer #590 : PROSERIES: Plotting, other features are not MS Windows standard.
Xilinx Answer #592 : PROFLOW: Does not call PPR with all user-defined parameters (PPR.PRO problem)
Xilinx Answer #594 : VIEWLOGIC PROFLOW 6.0: Will continue executing after Xilinx errors occur.
Xilinx Answer #597 : PROcapture: Plotting to PostScript file doesn't work, possible cause (SHARE.EXE)
Xilinx Answer #598 : PROSERIES 6.0: About error, "386 chip is currently exectuing in virtual mode"
Xilinx Answer #602 : FLOORPLANNER ONLINE-TUTORIAL: Large fonts do not display contents correctly
Xilinx Answer #604 : Viewlogic PROseries 6.0: System Error, sharing violation on drive <drive>:
Xilinx Answer #605 : XBLOX 5.1 may erroneously remove inverters from OBUFT/OBUFE output enable
Xilinx Answer #606 : XDELAY 5.2.1: How to make all the TSspecs in -SelectSpec unhighlighted
Xilinx Answer #609 : WIR2XNF 5.x: INIT attribute on macros may not be passed to lower levels.
Xilinx Answer #615 : Unbonded Fast Output Enable (FOE) can't be specified.
Xilinx Answer #618 : Timsim8/PLD_DVE_BA: "WARNING: Unknown design object" on Autologic design
Xilinx Answer #619 : XACT 5.x QuickSim: Board-level simulation for Xilinx FPGAs and CPLDs
Xilinx Answer #621 : PROWAVE: Printing section of waveform causes entire waveform to print.
Xilinx Answer #623 : XACT 5.x/M1 and Mentor compatibility information
Xilinx Answer #626 : EPLD Muncher always returns a warning on OrCAD OBUFT symbols
Xilinx Answer #627 : VERILOG-XL: How to handle upper/lower case conversion of Verilog signalnames
Xilinx Answer #630 : SYNOPSYS: How to tell what version of XSI (Xilinx-Synopsys Interface) you have.
Xilinx Answer #632 : PROsim, ViewSim: Using the LOADM command with Xilinx FPGA simulations
Xilinx Answer #633 : XC5200: How to shut off the internal oscillator
Xilinx Answer #634 : XNF2VERILOG V9502-1.21G ERROR: 'Could not find primitive...does_pin_have_delay'
Xilinx Answer #637 : PROFLOW: Does not always display all available Xilinx device speed grades.
Xilinx Answer #638 : CADENCE 9404: Known problems and workarounds for Cadence Interface to Xilinx
Xilinx Answer #646 : CADENCE VERILOG-XL: driving GSR, GR (global reset) and GTS in Verilog simulation.
Xilinx Answer #648 : CADENCE VERILOG-XL: Buffer output does not follow transitions on its input (transport and inertial delays)
Xilinx Answer #649 : XNF2CDS/XNF2Verilog: Symbol does not have corresponding entry in the PINfile
Xilinx Answer #650 : CADENCE CONCEPT: Attaching multiple LOC constraints / properties / attributes to XBLOX components
Xilinx Answer #651 : PPR Error 5802: PGA package pin location "Uxx" assumed to be unbonded
Xilinx Answer #653 : Program under Windows error: GROWSTUB General Protection Fault, pointer.dll
Xilinx Answer #654 : Hardware Debugger: Error states a file cannot be opened when it is actually corrupted
Xilinx Answer #655 : Using OrCAD Capture with XACT
Xilinx Answer #656 : FLOORPLANNER v5.2: The function keys don't work when the 'Num Lock' or 'Caps Lock' is on.
Xilinx Answer #657 : FLOORPLANNER v6.0/5.2: PPR May Fail Due to Invalid Floorplanner Placement
Xilinx Answer #658 : FLOORPLANNER v6.0/5.2: Warning 12926 : constraints file read that contains wildcards.
Xilinx Answer #659 : FLOORPLANNER v5.2: Multiple periods are not supported in filenames
Xilinx Answer #660 : FLOORPLANNER v6.0: Printing hangs the system if no default printer is selected.
Xilinx Answer #661 : FLOORPLANNER v6.0: Will not load file from directory that only has groupwrite permission.
Xilinx Answer #662 : FLOORPLANNER v6.0: Saving a file to a write protected floppy results in a system error.
Xilinx Answer #663 : XNF2NGD Core dumps due to bad or missing part statement in XNF file.
Xilinx Answer #664 : Programmer reports bad checksum for BG225 .PRG file
Xilinx Answer #665 : Sun4 version of Muncher fails with usage error
Xilinx Answer #666 : 7336 or 7318 functions incorrectly after being programmed by Data I/O programmer
Xilinx Answer #667 : XEMAKE/XEMAKE6: schematic design functions incorrectly in simulation or in system
Xilinx Answer #669 : No PLD file created when running from XDM
Xilinx Answer #670 : Which JEDEC formats are supported?
Xilinx Answer #671 : Error cl192 or cl126 while converting a PALASM (PDS) file
Xilinx Answer #672 : Xdelay/Timing Analyzer 6.0: Reported Setup Value on Carry Logic Path appears erroneous
Xilinx Answer #673 : Design Manager 6.0.1: Unhandled exception in 256 color mode on Compaq QVision boards.
Xilinx Answer #674 : PROMs/XC1700: Ordering ID (part number) and PROM Marking ID are different for the same part
Xilinx Answer #675 : XABEL 5.1 (BLIFOPTX) fails on Truth Table designs
Xilinx Answer #677 : PPR 5.2.0, 4000E: Data read during Dual Port RAM simultaneous read and write is incorrect
Xilinx Answer #678 : PROflow: DOS Error # 83: Buffer too small
Xilinx Answer #679 : Prom file formatter fails with an error: Could not get model for statbar!
Xilinx Answer #680 : SDT2XNF Fails to write TNMs into the .XNF file
Xilinx Answer #681 : XEMAKE6 gives the error: hi10:[Warning] Cannot open CTL file <design>.ctl.
Xilinx Answer #682 : abnormal program termination memory protection (or Page) fault
Xilinx Answer #687 : XSimMake, XDraw: "Could not access Sheet 1 of SCHEMATIC <top>." Powerview 5.3.2
Xilinx Answer #688 : CADENCE VERILOG-XL: Cannot run SDF Annotate, SDF libraries have not beenlinked in.
Xilinx Answer #689 : CADENCE CONCEPT2XNF 5.2 (9502) : TNM and Timespec properties attached to PADs do not get translated
Xilinx Answer #690 : CADENCE CONCEPT2XNF 9502: Net properties in schematic not translated toXNF
Xilinx Answer #691 : XSimMake: How to modify flows to run user programs, scripts, or batch files
Xilinx Answer #692 : EDIF2XNF: LOC or other I/O properties lost (ENWrite net bundles)
Xilinx Answer #694 : PPR 5.2.0 issues error 5846 on designs where the aclk or gclk is fed from a clb and the clb location is constrained
Xilinx Answer #695 : XC4000H: Input/Output mode defaults for 4000H
Xilinx Answer #696 : Configuration: Hazards of exceeding 3K CCLK low time maximum in Slave Serial Mode
Xilinx Answer #697 : 6.0: About WIN32S and XACTstep 6.0 (Design Manager Hangs)
Xilinx Answer #698 : 6.0, Compaq: Design Manager may give Unhandled Exception in 256 Color Mode.
Xilinx Answer #699 : 6.0: Programmable Key: Change parallel port settings if key is not seen.
Xilinx Answer #700 : 6.0: About "Problem inv.PROCapture...Leave PSFM"
Xilinx Answer #701 : 6.0: Memory requirements for various parts.
Xilinx Answer #703 : 6.0: PC install requires Swap Space > 0 Meg, due to Win32s.
Xilinx Answer #704 : 6.0: PC hangs if Virtual Memory is checked while Design Manager is running.
Xilinx Answer #705 : 6.0: List of files that XACTstep 6.0 install places in c:\windows and c:\windows\system
Xilinx Answer #706 : 6.0: win32s/WinProbe may cause Design Manager to hang during translate.
Xilinx Answer #707 : FITNET will not use PIN 1 (MR) even if MRINPUT=ON was specified in Viewlogic
Xilinx Answer #709 : Design Manager/Flow Engine 6.0.1: GROWSTUB General Protection Fault, pointer.dll
Xilinx Answer #710 : Design Manager 6.0.1: Cannot find input design or work directory
Xilinx Answer #711 : Design Manager 6.0.1: win32s/WinProbe may cause Design Manager to hang during translate under Windows 3.11
Xilinx Answer #713 : PROsim hangs with a win32s error (multiple causes/resolutions)
Xilinx Answer #714 : CADENCE: Can't start up Openbook--standard variable definitions not initialized
Xilinx Answer #715 : 6.0: "Win32s requires file sharing and locking support. Please executeshare.exe before continuing" (vshare.386)
Xilinx Answer #716 : Design Manager 6.0.1: System Error, Unhandled Exception: Subscript out of bounds.
Xilinx Answer #718 : Flow Engine 6.0.1: Optimize Step Must Be Run to Read in XACT-PerformanceChanges in Constraints File
Xilinx Answer #720 : Design Manager 6.0.1: PC hangs if Virtual Memory is checked while DesignManager is running.
Xilinx Answer #721 : Design Manager/Flow Engine 6.0.1: cancel button can cause memory leaks
Xilinx Answer #722 : Design Manager M1.5: Timing Simulation Data (time_sim.*) is not created
Xilinx Answer #723 : Design Manager 6.0.1: Target Family cannot be changed after project is created
Xilinx Answer #724 : Design Manager/Flow Engine 6.0: Application Error: Stack Overflow
Xilinx Answer #725 : Design Manager 6.0.1: Calling DOS program within a Windows application causes screen to go blank
Xilinx Answer #726 : Design Manager 6.0.1: How to change the default report browser/editor/viewer
Xilinx Answer #727 : Design Manager 6.0.1: Translate fails to creat a Version/Revision
Xilinx Answer #728 : Design Manager 6.0.1: Unable to create directory for the new revision
Xilinx Answer #729 : Design Manager 6.0.1: Manually deleting project data can cause System Error
Xilinx Answer #730 : Design Manager 6.0.1: Attempts to Rename the Design Name causes System Error
Xilinx Answer #731 : Design Manager 6.0.1: Report Browser error: The report file is missing
Xilinx Answer #732 : Flow Engine 6.0.1: Changes to Options Templates are not used
Xilinx Answer #733 : Design Manager 6.0.1: Guide Data Specified in two Dialogs
Xilinx Answer #735 : PLD_DMGR error in Solaris 2.x: font could not be loaded, loading failed
Xilinx Answer #736 : X2VPREP/TIMENET/TIMENETX: Error--Incompatible netlist version
Xilinx Answer #738 : XBLOX 5.x: internal error 20224, representation_error
Xilinx Answer #739 : Gen_sch8 fails under Mentor B.x with "call to undefined procedure"
Xilinx Answer #740 : FPGA Configuration:Asynch Peripherial mode-Done goes high, ouputs not active.
Xilinx Answer #741 : After Installing XACT 5.2/6.0 user can no longer plot from Viewlogic Software
Xilinx Answer #743 : XNF2CDS 5.0: complains that all the I/O pins are invalid in a plastic package
Xilinx Answer #745 : FITNET, CONCEPT2XNF: Fitnet drops LOC= I/O constraints in XNF file generated by CONCEPT2XNF v5.2.
Xilinx Answer #746 : Install: Online Help Hyperlinks do no work on workstation (sun, sparc, hp), Acrobat v1.0
Xilinx Answer #747 : FLOORPLANNER v5.1: The Floorplanner may cause segmentation faults/core dumps
Xilinx Answer #751 : XNF2WIR Error 10: Unknown record type 'bsm(X).xnf'.
Xilinx Answer #752 : Design Manager: System Error, Unhandled Exception: ERROR_FILE_NOT_FOUND
Xilinx Answer #754 : Design Manager 6.0.1: Translate process gives memory allocation error
Xilinx Answer #755 : PROSeries is not compatible with Windows 95/NT
Xilinx Answer #756 : Designs previously translated using GXILINX are not compatible with Concept2xnf, compatibility with XACT 5.x
Xilinx Answer #757 : PPR ignores timing constraints when invoked from the command line
Xilinx Answer #758 : HW-130: Programmer flashes red FAIL light with HW-12x adapter in place
Xilinx Answer #760 : XC4000E does not configure in socket designed for XC4000: possible workaround
Xilinx Answer #761 : POWER.EXE may slow down PPR
Xilinx Answer #762 : EDIF2XNF error 6, "module.eds" not found in directory: possible causes
Xilinx Answer #763 : How to run XACTstep 6.0 from the CD; installation procedure (long)
Xilinx Answer #765 : "Extra" RAM Components in ViewLogic 4KE Libraries, no license found for symbol
Xilinx Answer #766 : How to delete a design viewpoint in Mentor 8
Xilinx Answer #767 : xnf2wir error 214: pin names for <component> do not match Viewlogic symbol
Xilinx Answer #768 : Gen_sch8/XBLXGS: ld.so: libeddm.so.1/libbase_lib.so.14: not found
Xilinx Answer #770 : Hardware Debugger: Only one signal can be selected at a time in a waveform window
Xilinx Answer #771 : Hardware Debugger: Crosshair cursor is invisible on a black background
Xilinx Answer #772 : Translate (& other DOS tools) hang if "Exclusive in Foreground" is checked.
Xilinx Answer #774 : XC5200: Mode pins M0, M1, M2 are bidirectional, but library MD0, MD1, MD2 are unidirectional.
Xilinx Answer #775 : runtime error R6018 - unexpected heap error
Xilinx Answer #776 : Design Manager: PC connected to Novell network hangs when running translate.
Xilinx Answer #777 : Decoupling Capacitors
Xilinx Answer #778 : Benchmark. PPR runtime on various machines
Xilinx Answer #780 : MAKEBITS 5.2.X: length count differs due to new default -lc=aligned_lc
Xilinx Answer #781 : XBLOX 5.x: internal error 20224, existence_error
Xilinx Answer #782 : How can hold time violations occur when the data book states 0 ns hold times?
Xilinx Answer #783 : FLOW ENGINE 6.0: Hangs or freezes during a compile
Xilinx Answer #786 : Fncsim8/XBLXGS fails under Mentor B.x with "call to undefined procedure"
Xilinx Answer #787 : VST : component not found in library
Xilinx Answer #788 : XC7000/XC9500: Using the LOC attribute for Function block and macrocell assignment
Xilinx Answer #789 : How to simulate with Workview Office and XACTstep 6.0.1
Xilinx Answer #793 : HW-130 programmer does not accept .bit file format
Xilinx Answer #794 : XDE/EDIT LCA 5.2: INTERNAL PROGRAM ERROR (Please contact support personnel): bprog: 19,6: 10: not a pip
Xilinx Answer #796 : Hardware Debugger 6.0.1: Xchecker Cable Can't Be Detected or Readback Only Works Once
Xilinx Answer #797 : Install, setup, and licensing of Sun4-based XACT on machine with Solaris-based Cadence tools
Xilinx Answer #798 : Retargeting a design in Mentor Design Architect (Convert Design)
Xilinx Answer #799 : A Possible Solution for the 'Smalltalk Error' when Design Manager 6.0 isInvoked
Xilinx Answer #800 : M1.5 Constraints: TNM's cannot be attached to tri-stated output flip flops (OFDT) via the TIMEGRP statement.
Xilinx Answer #802 : Running XACTStep 6.0 Design Manager on OS/2 is not possible
Xilinx Answer #805 : Design Manager 6.0 Smalltalk Error
Xilinx Answer #806 : Post-synthesis Verilog-XL functional simulation is not supported by FUNCNET/FUNCNETX in Cadence and ES-Verilog interface, or in Xilinx M1.3
Xilinx Answer #807 : CONCEPT: How to do block mode designs (build symbols, integrate XNF files) into a schematic, chips_prt or schematic not found
Xilinx Answer #808 : XDM 5.x: XC3100A-09 not selectable, gives "-9 is not a valid speed grade"
Xilinx Answer #809 : How to select a pin on a symbol in PROcapture
Xilinx Answer #810 : XC3000: How to specify FGM mode in a schematic design using a CLBMAP
Xilinx Answer #813 : PROM File Formatter errors on 5202 only:unpadbs : HS round : frame 111 nframe 112 bit 2 of 4;
Xilinx Answer #815 : CONCEPT2XNF 9404, 9502: Problems with GND and VCC symbols in XPADS_HDL library
Xilinx Answer #816 : Installing and Running Xact Step 6.0 over a Network.
Xilinx Answer #818 : Printing problems with PROcapture 6.1: Missing or greyed out lines
Xilinx Answer #819 : XC5200: Dedicated GCLK pins for I/O when using BUFGP
Xilinx Answer #821 : XC3000/XC4000/XC5200: xde in vesa16 mode requires 800x600x16 color support
Xilinx Answer #822 : Mentor/PLD_DA 5.2: Convert Design loses NET, LOC, other port properties
Xilinx Answer #823 : Hardware Debugger 6.0.1: Groups cannot be used to create other groups.
Xilinx Answer #824 : Hardware Debugger 6.0.1: Groups w/ many signals may not be displayed properly in graphical waveform windows
Xilinx Answer #825 : Hardware Debugger 6.0.1: The Console becomes jumbled when it made too small.
Xilinx Answer #826 : Hardware Debugger 6.0.1: The Cable command Logic Level of Pins is not a continuous probe.
Xilinx Answer #827 : Hardware Debugger 6.0.1: A group cannot be deleted from the Signal Groups dialog.
Xilinx Answer #828 : Hardware Debugger 6.0.1: Nothing can be selected when viewing waveforms textually.
Xilinx Answer #829 : Hardware Debugger 6.0.1: A group cannot be modified using the Signal Groups dialog.
Xilinx Answer #830 : Hardware Debugger 6.0.1: Help will be disabled if the help file is located on a network drive.
Xilinx Answer #831 : Hardware Debugger 6.0.1: Printing graphical waveform using Landscape orientation does not rotate waveform.
Xilinx Answer #832 : Hardware Debugger 6.0.1: Once a signal or group is selected in a graphical waveform, it can't be unselected
Xilinx Answer #833 : Hardware Debugger 6.0.1: Double-clicking on close box in a window's title bar doesn't close the window
Xilinx Answer #834 : Hardware Debugger 6.0.1: Nets split during implementation are shown as split nets in available signals list
Xilinx Answer #835 : Hardware Debugger 6.0.1: Timeout After X Seconds option only for External triggers.
Xilinx Answer #836 : Hardware Debugger 6.0.1: Clicking No in Press enter to Start Readback dialog shows FailedReadback message
Xilinx Answer #837 : Hardware Debugger 6.0.1: Selecting File->Print without a printer installed gives an internal warning
Xilinx Answer #838 : Hardware Debugger 6.0.1: The Hardware Debugger can crash if too many waveform windows are opened at once
Xilinx Answer #839 : Hardware Debugger 6.0.1: Once a macro has been issued, there is no way to interrupt it.
Xilinx Answer #840 : Hardware Debugger 6.0.1: When a macro is saved, invalid macro commands are not flagged.
Xilinx Answer #841 : Hardware Debugger 6.0.1: Non-consecutive lines in the Console window cannot be selected using the CTRL key
Xilinx Answer #842 : Hardware Debugger 6.0.1: Printing only prints the currently displayed waveform portions.
Xilinx Answer #843 : Hardware Debugger 6.0.1: Clicking Run macro toolbar icon generates an error if a macro is not in focus.
Xilinx Answer #844 : Hardware Debugger 6.0.1: Console and macro windows cannot be printed from the Hardware Debugger.
Xilinx Answer #845 : Hardware Debugger 6.0.1: More than 500 snapshots will not be displayed.
Xilinx Answer #846 : Hardware Debugger 6.0.1: A readback text file (.rdb) of 0 bytes will be created if not enough disk space
Xilinx Answer #847 : Hardware Debugger 6.0.1: Textually saved waveforms cannot be re-opened into the Hardware Debugger.
Xilinx Answer #848 : Hardware Debugger 6.0.1: Cannot download using the Hardware Debugger if running from an executable CDROM.
Xilinx Answer #849 : Hardware Debugger 6.0.1: The Hardware Debugger cannot readback at 9600 baud on some machines.
Xilinx Answer #850 : Hardware Debugger 6.0.1: 1st readback may fail after a verify performed in the middle of several readbacks
Xilinx Answer #851 : Hardware Debugger 6.0.1: "Save Readback" in the File menu is de-activated when a waveform is iconized.
Xilinx Answer #852 : Hardware Debugger 6.0.1: Text waveforms cannot be printed from the Hardware Debugger.
Xilinx Answer #853 : Hardware Debugger 6.0.1: Help button in the New Group Name dialog does not invoke help.
Xilinx Answer #854 : Hardware Debugger 6.0.1: Hardware Debugger may issue an EMM386 error or hang on invocation.
Xilinx Answer #855 : Hardware Debugger 6.0.1: Only 3 characters show when displaying # of clocks applied before first snapshot
Xilinx Answer #856 : ProWave and ProSim: How to change system colors
Xilinx Answer #857 : Synopsys: XC5200: clock inversion is implemented in a function generator, not at the flip-flop.
Xilinx Answer #859 : XABEL-CPLD: Switching between 9500 and 7300
Xilinx Answer #860 : XC4000E: 4025E pinout update for the MQ240, HQ240, and HQ304 packages
Xilinx Answer #864 : How to reach Viewlogic technical support.
Xilinx Answer #865 : How to contact OrCAD technical support: hotline, bbs numbers
Xilinx Answer #867 : Proflow changes the Viewdraw.ini file while using Pre-Unified Libraries
Xilinx Answer #868 : Differences between DS550 (EPLD) software versions 5.x and 6.0
Xilinx Answer #869 : How to reach Cadence technical support
Xilinx Answer #870 : CONCEPT2XNF 9502: TNM, LOC and other Properties (attributes) attached tonets do not get translated to the XNF
Xilinx Answer #872 : Workview: Viewdraw gives Pharlap error 33 when plotting
Xilinx Answer #874 : XC2000/XC3000/XC4000/XC52000: How to reach Chip Supply for dies, multi-chip module (MCM) information
Xilinx Answer #875 : VSMUPD: vsec: Error 8037: License node restriction does not match client's node for product ViewBASE
Xilinx Answer #880 : How to reach Commercial Documentation Services (CDS) & Viewlogic telesales for hard-copy manuals
Xilinx Answer #881 : Specifying an FDCE in VIEWsynthesis
Xilinx Answer #882 : MAKEPROM: INTERNAL PROGRAM ERROR when ran on a xc5200 device.
Xilinx Answer #883 : XCHECKER cannot pull the DONE pin LOW.
Xilinx Answer #885 : XC5200: Express Mode Bitstream loaded to the same pins as Peripheral Download.
Xilinx Answer #890 : In Windows 95, Prom File Formatter menus do not function correctly
Xilinx Answer #891 : Workstation licensing(DNS/NIS): Invoking XACT tools gives error, "Cannotfind server hostname in network database."
Xilinx Answer #893 : QuickSim/Solaris: Could not load object file xxx.ss5_b, no such file or directory
Xilinx Answer #894 : Gen_sch8 5.x fails on Solaris with "crt1:bad open" or "libbase: can't open file"
Xilinx Answer #895 : XBLXGS 5.x fails on Solaris with "crt1:bad open" or "libbase: can't openfile"
Xilinx Answer #897 : ProCapture Error when printing : vlwp Metafile does not exist
Xilinx Answer #898 : check -p sdesign.1 fails because of invalid/overlapping nets
Xilinx Answer #900 : Foundation: Library access errors
Xilinx Answer #902 : Information about running XACT 5.2.1/6.0.1 (with WVO) in Windows NT
Xilinx Answer #905 : Mentor/EDIF2XNF: purple LOC properties on PADs are lost, gold propertiesare fine
Xilinx Answer #906 : PPR Error #1173 fplan.p file cannot be found when PPR is Run From FloorPlanner.
Xilinx Answer #907 : XC5200: Minimum pulse width on PROGRAM to reconfigure a 5200 device : 5k configuration
Xilinx Answer #908 : Design Manager 6.0: Design Manager doesn't start. Says "Not enough Memory"
Xilinx Answer #909 : NeoCad's compatibility with Solaris
Xilinx Answer #910 : Foundation 6.x: is there Windows 95, Windows NT, OS/2 support?
Xilinx Answer #912 : Foundation HDL Editor: editor will not start
Xilinx Answer #913 : PLD_Men2XNF8 5.x: "test: unknown operator"
Xilinx Answer #914 : Installing XABEL-CPLD Software Over A Network
Xilinx Answer #915 : PPR : Error 5606 : Unable to create output MXN or PIC cell.
Xilinx Answer #916 : Xilinx key does not work with Synopsys Logic Modeling (GlenCo) key
Xilinx Answer #917 : Design Manager: Unhandled exception, invalid file name, PCFilename class
Xilinx Answer #918 : SYNOPSYS: Cannot find the architecture " " in the library
Xilinx Answer #921 : FLOORPLANNER: Unable to load fplan.pm occurs when opening the Floorplanner.
Xilinx Answer #922 : WIR2XNF error: could not find WIR file for a user-created component
Xilinx Answer #926 : HW-130: Installation and Debugging tips (PC platforms)
Xilinx Answer #928 : PPR, XNFPREP: INIT=S property ignored because INIT converted to "init"
Xilinx Answer #930 : PROGRAMMERS: checksums on Data I/O programmers may not match when doinga "load" and doing a "read"
Xilinx Answer #931 : Concept2xnf: timespec name other than TS01 through TS10 not translated to XNF file
Xilinx Answer #932 : X2VPREP/XCDSPREP: Error: XNF v6.0 is not supported
Xilinx Answer #933 : Design Manager Report Browser editor is non-standard or missing: how to set default test editor for browser
Xilinx Answer #934 : 94 DATA BOOK 3rd: Solder pad layout for PQ160 package on page 4-2 showsan incorrect I2 dimension
Xilinx Answer #936 : Foundation: Importing Viewlogic schematic could change some bus names
Xilinx Answer #937 : Foundation: Imported schematic, pushing into macro - "Symbol is a primitive cell"
Xilinx Answer #939 : Foundation Simulator: macro outputs always 'Z' during simulation
Xilinx Answer #940 : BOUNDARY SCAN/JTAG: How to configure a XC4000 family or XC5200 device via Boundary Scan
Xilinx Answer #941 : BOUNDARY SCAN/JTAG: How to do connsecutive readbacks via the JTAG interface in the XC4K/XC5K devices in XACT 5.x, 6.x
Xilinx Answer #942 : XNFPREP error 3527: possible causes if using Foundation
Xilinx Answer #943 : Hardware Debugger 6.0.1: Verification yields "Part type "?" is not defined in 'partlist.xct'
Xilinx Answer #945 : PPR 5.20: Support for dual phase clocks in 3000A devices
Xilinx Answer #946 : WIN32S problems after installing Foundation (win32s v1.30a) - OE20.EXE, unexpected DOS error 21
Xilinx Answer #947 : CADENCE COMPOSER: Instantiating I/O (input and output) pads
Xilinx Answer #949 : XC5200: Slew rates (RISE and FALL times) for outputs with a 50 pF load
Xilinx Answer #950 : PPR issues ERROR 6105 due to incorrect FMAP for XBLOX ACCUM
Xilinx Answer #951 : Foundation: PPR error 5812 on imported Viewlogic design with CST file
Xilinx Answer #952 : PPR: Guidelines for using manually edited LCAs as PPR guide files
Xilinx Answer #954 : Foundation XVHDL, F6.x: Instantiating I/O buffers causes XNFPREP error 3530
Xilinx Answer #956 : XC9500 Fitter Error : Fatal error tnt.10049; out of stack buffers
Xilinx Answer #960 : MAKEBITS, MAKEPROM v5.2: bit file and prom file size may differ from that generated with v5.1/5.0 software.
Xilinx Answer #961 : HW-130: HW-120 adapter compatibility with HW-130
Xilinx Answer #964 : XChecker 5.2.1: Downloading a valid bitstream in DOS produces a frame error - INIT goes low
Xilinx Answer #965 : Place & Route in Flow Engine produces PPR error 5603: "Unable to open .xtf file"
Xilinx Answer #966 : Hardware Debugger 6.0.1: Error Message: Cannot find TEMP directory
Xilinx Answer #969 : XSIMMAKE: Check.exe fails while using the simulation utility in Windows.
Xilinx Answer #970 : Defining pin attributes/locations for a VHDL code using Viewsynthesis
Xilinx Answer #973 : How to specify a BUFGP vs. BUFGS using Viewsynthesis?
Xilinx Answer #974 : XNFPREP 5.20: changes "INIT=S" to lower case "init=S", which PPR 5.20 ignores
Xilinx Answer #976 : Authorized key decrements evaluation runs.
Xilinx Answer #977 : FLOORPLANNER: Unable to load file <design>.lca / FPLAN : ERROR 1576 : Error in LCA file
Xilinx Answer #978 : Why doesn't XBLOX 5.2 optimize all my flip-flops into IOBs as in previous versions?
Xilinx Answer #979 : 94 DATA BOOK 3rd: PQ100 package dimensions on page 4-10
Xilinx Answer #980 : Foundation: BTRIEVE error messages reported in Project Manager message window
Xilinx Answer #981 : Convert a jedec files to an ABEL
Xilinx Answer #982 : Error 1140: the design contains X unresolved references
Xilinx Answer #983 : XC9500: How to set FAST slew rate for 9K outputs in PLUSASM and ABEL
Xilinx Answer #984 : Foundation: VHDL entry option is not selectable
Xilinx Answer #985 : What is needed to target 4000E speed grade 4000 designs using Verilog, Foundry and Synopsys
Xilinx Answer #986 : Foundation: How to delete a component from a user library
Xilinx Answer #989 : XCHECKER 5.2.1: Files required for standalone XChecker software (PC or Workstation).
Xilinx Answer #992 : BOUNDARY SCAN/JTAG: Sample/Preload in a XC5200 appears to work like BYPASS
Xilinx Answer #993 : BOUNDARY SCAN(JTAG): TAP Instructions not available if /PROG is held lowin XC4K/XC5K
Xilinx Answer #994 : Foundation: Improper Netlist error while loading functional simulation
Xilinx Answer #997 : Using XACT 5.2.1 with Mentor Graphics' B.x release
Xilinx Answer #998 : XC7300F electrical characteristics
Xilinx Answer #1004 : HW-130: 7372 is non-functional if security bit is programmed
Xilinx Answer #1005 : When items are selected in Procapture, selected color is the opposite color.
Xilinx Answer #1006 : HW-130: "Device Manufacturer code error"
Xilinx Answer #1010 : Timsim8/PLD_DVE_BA gives "Delete operation on object failed"
Xilinx Answer #1011 : PPR issues error 9025 on 5k design; FPLAN finds no errors
Xilinx Answer #1012 : WVOffice: while printing a project, the printouts are fuzzy
Xilinx Answer #1013 : Gen_sch8 error: Bad status 79501087 from ddp__add_instance
Xilinx Answer #1014 : Design Manager/Flow Engine 6.0.1: A guide file specified in the Advancedmenu may not be picked up
Xilinx Answer #1016 : Using MakeTNM and addTNM in order to add TNMS to a .XNF file.
Xilinx Answer #1017 : Designing with the XC5200 family using synthesis
Xilinx Answer #1019 : How to describe a flip-flop with a clock enable with VHDL/Verilog
Xilinx Answer #1022 : Quicksim II: No-connects appear on Fncsim8-created schematic containing XBLOX
Xilinx Answer #1023 : PROMs: Atmel EEPROM compatibility with Xilinx 1700 series
Xilinx Answer #1024 : Selecting New Device in Design manager give Unhandled Exception Error. Message not understood
Xilinx Answer #1027 : Foundation Simulator: PRINT command described incorrectly in documentation
Xilinx Answer #1028 : Foundation HDL Editor: Compiling an ABEL file as a stand-alone CPLD design.
Xilinx Answer #1029 : PROMs, HW-130: ERROR: Reset not programmed.
Xilinx Answer #1031 : Xchecker cannot be used in place of NeoCad download cable in Foundry environment
Xilinx Answer #1033 : XC3000: Place Block syntax for APR is different than for PPR, results inAPR Error 213.
Xilinx Answer #1034 : Foundation: SC Symbols list is empty when adding a component in Schematic Capture
Xilinx Answer #1036 : XABEL-CPLD, 9500: Controlling Global Net Utilization for 9500 designs with XABEL-CPLD
Xilinx Answer #1037 : ProCapture will not open up when selecting Design Entry from Proflow
Xilinx Answer #1038 : XABEL-CPLD: Possible cause of General Prot. Faults, and being disconnected from Internet/network
Xilinx Answer #1040 : What are VCC_BUS and VSS_BUS pins
Xilinx Answer #1041 : Design Manager 6.0.x: Unhandled exception, xact raw binary interface error
Xilinx Answer #1043 : Foundation: Possible causes of XNFMERGE Warning 285
Xilinx Answer #1045 : Foundation Simulator: XC7300/XC9500 flip-flop outputs unknown
Xilinx Answer #1047 : XACT-CPLD: hi12:[Error]Keyword MC9500_PTERM_LIMIT in the CTL file is invalid.
Xilinx Answer #1050 : Designing with the XC9500 family in Mentor (XACT 5.2.x)
Xilinx Answer #1051 : XNFPREP: Error 3526: Illegally inverted pin with XBLOX SYNC_RAM symbol
Xilinx Answer #1052 : Design Manager 6.0.x: runtime 6008 not enough space for arguments
Xilinx Answer #1054 : design manager : translate general protection fault Wir2xnf TNT 11020
Xilinx Answer #1055 : Foundation: What if a user macro has same name as Xilinx library symbol?
Xilinx Answer #1056 : Foundation: How to move a project around
Xilinx Answer #1058 : XACT-CPLD, 9500: Creating Programmable Ground Pins in XC9500 Designs
Xilinx Answer #1059 : XNF Specification v6.1 is now available on ftp, including XC7000 supplement
Xilinx Answer #1061 : VERILOG-XL: Attempt made to connect to an existing Verilog Environment,connection not accepted
Xilinx Answer #1062 : Procapture: SECURITY no valid license for product: ProSeries
Xilinx Answer #1065 : XC3000/XC4000/XC5200: How to select cmos input thresholds for FPGAs
Xilinx Answer #1066 : XBLOX 5.x: ONE_HOT COUNTER with unconnected UP/DN pin results in DOWN counter
Xilinx Answer #1067 : XC2000/XC3000/XC4000/XC5200: Device/Package Marking information.
Xilinx Answer #1068 : Foundation: Importing a Viewlogic design with a user library
Xilinx Answer #1069 : How to specify TIMESPECs
Xilinx Answer #1070 : XC1700D SPROM input capacitance value
Xilinx Answer #1071 : XACTstep Libraries Guide: TS identifier in Mentor NOT limited to 01, 02,etc.
Xilinx Answer #1072 : Fast outputs versus fast slew rate outputs in Xilinx devices
Xilinx Answer #1074 : Timsim8: "return code 1" from segmentation fault under Solaris
Xilinx Answer #1075 : wir2xnf gives error 4 when using Powerview 6.0 (iwinit failure), need lsclient daemon
Xilinx Answer #1076 : Quicksim II: Obsolete-library RAMs and ROMs output X's in XACT 5.2
Xilinx Answer #1077 : CADENCE CONCEPT: Properties on pads (LOC, TNM, FAST) are not supported
Xilinx Answer #1078 : CADENCE CONCEPT (pre-M1 and M1): Adding pin lock attributes/properties to CLB maps
Xilinx Answer #1080 : EZTAG: When programming, gives message "Bad command or file name."
Xilinx Answer #1081 : EZTAG: Can't find file "other.bsd" when programming chain of 9500's
Xilinx Answer #1082 : EZTAG: Causes of Program and Erase problems
Xilinx Answer #1083 : Xchecker cable is not connected correctly - Invalid port name
Xilinx Answer #1085 : LCA2XNF may use unit delays (functional) in timing simulation flow
Xilinx Answer #1088 : Exemplar: Valid 7300 part type not found in library xi73
Xilinx Answer #1089 : VERILOG-XL: Specifying multiple libraries in a Verilog simulation
Xilinx Answer #1090 : Foundation: What is the Service Pack and where can I get it?
Xilinx Answer #1091 : CONCEPT, COMPOSER, VERILOG (pre-M1 only): XC4000 ILD latch primitives are renamed in the pre-M1 Unified libraries
Xilinx Answer #1092 : PQ44 package dimensions incorrect in 1994 Data Book
Xilinx Answer #1093 : COMPOSER: Incorrect SCHNM property on ILD1 causes XNF2CDS "no corresponding entry" error
Xilinx Answer #1095 : Xchecker Cable: Can the Xchecker cable be used to program an XC9500 CPLD?
Xilinx Answer #1097 : The DOS based XCHECKER software may not run over a NOVELL network.
Xilinx Answer #1098 : M1: Powerview: User-owned directory/files may be created in Xilinx tree
Xilinx Answer #1100 : XC4000E: What is state of RAMs upon power-up/configuration?
Xilinx Answer #1101 : Men2XNF8/ENWrite error: "Pin does not map to a net in model" due to incorrect COMPMC16 macro
Xilinx Answer #1102 : How to use PROflow with the 4000e family.
Xilinx Answer #1104 : MAKEBITS TIE--Should all designs be tied?
Xilinx Answer #1107 : ES-Verilog 2k, 3k, 4k, 4KE, 5k and 7k libraries and interface are available on XACT v5.2.1 CD and ftp site
Xilinx Answer #1109 : 96 DATA BOOK: 4025ehq208 not found in partlist.xct
Xilinx Answer #1111 : XC5200: Dynamic power consumption values (most up-to-date)
Xilinx Answer #1112 : XC5200: Typo reads "50-kW to 100-kW pull-up resistor" in 'The Programmable Logic Data Book', 7/96
Xilinx Answer #1113 : EZTAG Errors 1020, 1019: While programming 9500 device with Xchecker cable
Xilinx Answer #1115 : VERILOG: Location of ES-Verilog v5.2.1 on XACTstep v5.2.1 CD for workstations
Xilinx Answer #1117 : XC4000: XACT 5.2- MEMWIN / Memory Generator does not support Dual Port RAMs
Xilinx Answer #1118 : Foundation: Synthesis of VHDL causes message: No entity selected.
Xilinx Answer #1119 : PROMs: HW-112 programmer support for 1700L
Xilinx Answer #1122 : PROMs: 1736 is not available as an L (low power) part
Xilinx Answer #1124 : Viewlogic: Do NOT use $ARRAY in Xilinx designs
Xilinx Answer #1125 : Foundation install hangs at "searching for XACT environment"
Xilinx Answer #1127 : SYNOPSYS: The entity .. depends on the package std_logic_arith. Reanalyze the source
Xilinx Answer #1128 : Problems after installing Xact 6.0.1 (Win32s v1.30a) - OE20.EXE, unexpected DOS error 21
Xilinx Answer #1132 : Foundation Simulator: 'Invalid chip descriptor' error while loading netlist
Xilinx Answer #1133 : XNF2INF Error-008: An invalid parttype "52xx" was specified in the XNF file
Xilinx Answer #1134 : FLOORPLANNER 6.0.1: Unable to invoke the floorplanner from the Design Manager
Xilinx Answer #1135 : PROsim error: Could not find wir file xc5200:osc52.1
Xilinx Answer #1138 : Amount of memory that is required by XACT/XDE 5.2.1
Xilinx Answer #1139 : Workview Office 7.1.2 is the only version that is compatible with Windows 3.11
Xilinx Answer #1140 : XC9500, EZTAG: How to turn off Data Protection (DP)
Xilinx Answer #1141 : XSIMMAKE creates schematic symbols with double bounded bus pins.
Xilinx Answer #1142 : install XACT 5.2.1 on Sparc: /cdrom/scripts/check_os.csh: Permission denied.
Xilinx Answer #1144 : HW-130: Can't find programmer or system crash problem on Toshiba laptops
Xilinx Answer #1146 : 94 DATA BOOK 3rd: Error in boundary scan order for 4010 BG255 on page 2-62
Xilinx Answer #1148 : XLMCON shows two parenthesis for the HostID for the HP
Xilinx Answer #1150 : Design Manager/Flow Engine: BlackBoxes appear instead of Characters
Xilinx Answer #1152 : CONCEPT: TIMEGRP (or TIMESPEC) name could not be found.
Xilinx Answer #1153 : PPR: ERROR 1173: the file \path\dsn.lca associated with the LCA cell \path\dsn could not be found.
Xilinx Answer #1154 : PPR 5.2: Error 5814: Constraint file block name '[name]' could not be found in net list
Xilinx Answer #1155 : Foundation: Pins on Abel symbol not matched to any signal in <abel_file>.xnf
Xilinx Answer #1156 : PCI Macro: Does it support Big or Little Endians?
Xilinx Answer #1157 : Powerview 6.0 has a different default VSM option, requires new file
Xilinx Answer #1158 : CADENCE OPENBOOK: Can't type in Search window on system running Openwindows
Xilinx Answer #1159 : XEPLD 6.0.1: vm2006:Internal Error and - invalid ID] when taegine is run
Xilinx Answer #1161 : Workview Office, PCI v1.1: Simulation fails if using unit delays only.
Xilinx Answer #1162 : Where to get BSDL files for the XC4000, XC5200, and XC9500
Xilinx Answer #1163 : "Can't open display" error when invoking install and other programs withgraphical interfaces
Xilinx Answer #1165 : XPP, HW-112: XPP v5.2.0 does not recognize 4020EHQ240 .bit file
Xilinx Answer #1166 : M1.3.7, M1.4, & XSI 5.2.1 Libraries Analyzed for Synopsys 3.3b(XACT XSI only), 3.4a(XACT XSI only), 3.4b, 3.5a,1997.01, and 1997.08
Xilinx Answer #1167 : XABEL: AHDL2X will hang at "processing equations..." with wide buses.
Xilinx Answer #1168 : EZTag Error 1017: What it means and how to fix it
Xilinx Answer #1169 : Design Manager: Visual Works v2.0 Fatal Error Out of Memory
Xilinx Answer #1170 : Is it possible to run one license manager for multiple XACT s/w versions
Xilinx Answer #1171 : Why are there TDI, TCK, and TMS pins on the XChecker cable?
Xilinx Answer #1172 : BOUNDARY SCAN/JTAG: What is the bit order of the Instruction Register inXilinx FPGA's
Xilinx Answer #1173 : Are the XC4000 and XC4000E BSDL files identical?
Xilinx Answer #1174 : BOUNDARY SCAN/JTAG: Instructions defined by IEEE standard 1149.1
Xilinx Answer #1175 : XABEL: Xt Warning: ...Couldn't open file xmain.uid - MrmNOT_FOUND
Xilinx Answer #1176 : EZTag and Windows '95 and file "."
Xilinx Answer #1178 : PCI Macro v1.1: The 5.2.0 XC4000E Viewlogic libraries may cause problems.
Xilinx Answer #1179 : PROM files and programmer checksums
Xilinx Answer #1180 : XACT-CPLD : An unrecognized Symbol Type 'NOR7' was found in netlist
Xilinx Answer #1181 : Proflow : DOS error #53 : Can't open file.
Xilinx Answer #1182 : procapture dos error #75 occurred: access denied...
Xilinx Answer #1183 : Proflow : Project Verification Error
Xilinx Answer #1184 : Foundation Timing simulation : BAX file <design> does not exist XACT6 Design Manager process ?
Xilinx Answer #1185 : PPR 5.2.0: ERROR 1582: Error in writing LCA data to memory:
Xilinx Answer #1186 : XNF2WIR ERROR 217: The logical function of <component> and its Viewlogicmodel do not match.
Xilinx Answer #1187 : XNFPREP failes due to capital letters in filename
Xilinx Answer #1188 : BOUNDARY SCAN/JTAG: Timing Parameters for TMS,TCK, and TDI
Xilinx Answer #1189 : Analyzing the Synopsys Designware and Simulation Libraries for M1 and XACT 5.2.1
Xilinx Answer #1190 : XC7300 : How to force a wired-AND function into the UIM in Xabel-CPLD
Xilinx Answer #1191 : PPR 5.2.x: abnormal program termination: memory protection fault in Windows95 (Win 95)
Xilinx Answer #1192 : EZTAG: INTERNAL ERROR: condition 'returned ==....at line '4046' in file 'rcab.c'
Xilinx Answer #1193 : WIR2XNF:Error-V (version) statement not unique, out of order or missing
Xilinx Answer #1194 : Foundation : 7000 BUFE/OBUFE has incorrect active low enable
Xilinx Answer #1195 : Xchecker Cable: What is the CCLK circuitry in the Xchecker cable?
Xilinx Answer #1196 : XC3000: XACT 6.0.x/5.2.x- Unable to target 3090(A, L) or 3190(A, L) TQ144 device
Xilinx Answer #1197 : How to access the Xilinx Customer Download area on our FTP site
Xilinx Answer #1198 : How to access the Xilinx anonymous FTP site
Xilinx Answer #1199 : LCA2XNF: Warning:23 pins do not have routing delays, PPR shows 0 unroutes
Xilinx Answer #1201 : What is the latest version of XBLOXGEN?/Where to get XBLOXGEN?
Xilinx Answer #1202 : 96 DATA BOOK: The 4020EHQ240 has 192 user IOs, not 193 as shown on p4-176
Xilinx Answer #1203 : 5200 VL libs : FJKRSE or FJKSRE does not function properly
Xilinx Answer #1204 : Where can you get a listing of Synopsys XSI Library Components
Xilinx Answer #1205 : What is in the contents of /pub/swhelp/synopsys on the Xilinx FTP Site?
Xilinx Answer #1206 : NEC VersaGlide Mouse driver causes Flow Engine to crash (Fatal exceptionat 0D)
Xilinx Answer #1207 : What is the latest version of addtnm and maketnm? Where to get addtnm and maketnm?
Xilinx Answer #1210 : Possible cause of XNFPREP 3527 :"Pad connected to invalid symbol pins"
Xilinx Answer #1211 : BOUNDARY SCAN/JTAG: How to get the `Scan Educator' tool from TI's website
Xilinx Answer #1212 : Workstation Install: How to Install software for a specific platform
Xilinx Answer #1213 : WORKSTATION INSTALL: Translation table syntax errors (XkeysymDB)
Xilinx Answer #1215 : BOUNDARY SCAN/JTAG: When is Boundary Scan available for use in the XC4000 and XC5200 devices
Xilinx Answer #1217 : Viewsim: backannotation from Viewsim/Viewtrace to Viewdraw doesn't work
Xilinx Answer #1219 : BOUNDARY SCAN/JTAG: Is the routing used by the XC4K/XC5K TAP pins visible in XDE or EPIC
Xilinx Answer #1220 : BOUNDARY SCAN/JTAG: How to 'turn on' jtag circuitry via XDE and EPIC forXC4K/XC5K devices
Xilinx Answer #1221 : Timing Analyzer 6.0.1: Won't save reports to an .xrp file in Windows 95.
Xilinx Answer #1222 : XLMASU (Xilinx License Manager Auto Start Utility) can't start the license manager on a workstation
Xilinx Answer #1223 : An application (like apr or xde) can't start the license manager on a UNIX workstation.
Xilinx Answer #1224 : Reading an Ocad 386+ design into Orcad Capture 7.0 for windows
Xilinx Answer #1225 : How to re-target a different Xilinx device family with Viewlogic's Altran
Xilinx Answer #1226 : PACKAGES: Information on calculating Temperature/Thermal Characteristics(Theta-JA)
Xilinx Answer #1227 : M1 or XACT Template Manager : How to specify options not available in the options menu of Design Manager
Xilinx Answer #1229 : PCI macro: Do I set the input/output levels to TTL or CMOS?
Xilinx Answer #1230 : PCI macro: Fplan - Potential errors found in LOCs or constraints.
Xilinx Answer #1231 : PCI macro: PROsim can't correctly simulate the full PCI compliance tests
Xilinx Answer #1232 : PCI macro: Use of XSIMMAKE in timing simulation
Xilinx Answer #1233 : 9500 BSDL File pin_map_string pin description and FPGA pin_map_string description
Xilinx Answer #1235 : Design Manager: Translate hangs while reading an XNF file
Xilinx Answer #1236 : Foundation: BTRIEVE 1002 or memory allocation error on XC4000E project
Xilinx Answer #1237 : Xchecker 5.2.1: Partlist.xct from xact\data directory is used for downloading instead of xpart.def
Xilinx Answer #1238 : Logitech Mouse driver causes Translate to Hang
Xilinx Answer #1239 : Xsimmake (5.2.x) patch needed for Workview Office (Windows 95 and NT)
Xilinx Answer #1240 : XKEY 5.2 under Windows 3.11 does not see the key, but works fine under DOS.
Xilinx Answer #1241 : Foundation: How Long Can Netnames and Pin Names Be?
Xilinx Answer #1242 : Does the XC4000E meet capacitance and inductance specs for PCI?
Xilinx Answer #1243 : Flow Engine 6.0.1: DOS 16m error - protected mode requires VCPI within virtual 8086
Xilinx Answer #1244 : PROsim or ViewSim: Outputs of ROM primitives are 'x' (indeterminant state).
Xilinx Answer #1245 : Gen_sch8 fails under Mentor B.x with "Unresolved Propagate symbol"
Xilinx Answer #1246 : Fncsim8/XBLXGS fails under Mentor B.x with "Unresolved Propagate symbol"
Xilinx Answer #1247 : patch for Flex/LM errors with xsimmake/check in Workview Office 7.2 (Error 8034)
Xilinx Answer #1250 : CADENCE, VERILOG-XL, X-BLOX: Error! Port (o) not found in module definition
Xilinx Answer #1251 : CONCEPT,SYNERGY, VERILOG 4000E and 5200 libraries for XACT flow are available from Cadence ftp as patches to 9504
Xilinx Answer #1252 : CONCEPT: Adding Xilinx properties--general guidelines
Xilinx Answer #1253 : Viewlogic: How do I LOC an IPAD4/8/16 or an OPAD4/8/16 ?
Xilinx Answer #1256 : Foundation HDL Editor: "Unhandled Exception" during VHDL synthesis
Xilinx Answer #1258 : Foundry7.0 for PC runs w/ Windows NT; ssetup may yield "device not attached"
Xilinx Answer #1259 : Foundation HDL Editor: "ABL2XNF program detected parameter value errors"
Xilinx Answer #1260 : Data I/O programmers have been re-qualified to program Xilinx XC1700 serial PROMs
Xilinx Answer #1261 : Foundation: "Low resources" appears entering manager.
Xilinx Answer #1262 : Quicksim II: Could not find a registered simulation model, NULL model will be inserted
Xilinx Answer #1264 : PROcapture: "Pin/Net disassociation at location ..."
Xilinx Answer #1265 : PPR 5.x: ERROR 5812
Xilinx Answer #1266 : HW-130: Verification Failure For a 17128D and 17256D
Xilinx Answer #1267 : JTAG & XCHECKER flying lead header size.
Xilinx Answer #1268 : CADENCE LEAPFROG: Simulating VHDL designs synthesized by Synopsys (pre-M1)
Xilinx Answer #1269 : XC4000E: MEMGEN always uses the part 4005EPG156 for Synchronous Rams.
Xilinx Answer #1270 : XACT-CPLD: Using a guide (.GYD) file to define pin constraints for CPLDs
Xilinx Answer #1271 : 4000E/5200 VERILOG Libraries are included on XACT v5.2.1 Core Tools CD and ftp site
Xilinx Answer #1272 : 9500, EZTAG: How many devices can JTAG cable program in a chain?
Xilinx Answer #1273 : Check, Procapture: Schematic components cannot be found.
Xilinx Answer #1274 : CADENCE TIMENET(X), FUNCNET(X), XCDSPREP, X2VPREP compatibility with XACT 5.2.1, 4000E, 5200: XNF version 5 expected, read version 6
Xilinx Answer #1276 : PCI macro: PROseries is not supported in the PCI design.
Xilinx Answer #1277 : PCI macro: Changing an Initiator to a Target design requires extra steps
Xilinx Answer #1278 : PROMs: maximum capacities for Tektronix, Motorola EXORmacs, and Intel MCS formats
Xilinx Answer #1279 : JTAG/BOUNDARY-SCAN: TDO and DOUT during Configure through boundary scan of 4k/5k
Xilinx Answer #1280 : General EZTag Troubleshooting Hints
Xilinx Answer #1282 : XC9500: Pull-ups in IOB should pull up to VccIO, not VccINT as Data Book shows
Xilinx Answer #1283 : Viewsynthesis: Symbol precompiled_xc3000:FDPE cannot be found
Xilinx Answer #1285 : PCI Macro: Why is the clock signal on the output of a BUF, not a BUFG?
Xilinx Answer #1286 : Foundation Simulator: simulating bidirectional signals
Xilinx Answer #1287 : XBLOX 5.x: Internal error 20224: representation_error
Xilinx Answer #1289 : Synopsys : How to use OSC5, OSC52, and CK_DIV Cells from the XC5200 Synthesys Libraries
Xilinx Answer #1291 : Foundation: Keylock (Sentinel driver) must be upgraded after an upgradefrom Win3.1 to Win95
Xilinx Answer #1292 : XNF2VERILOG/TIMENETX: Missing inversion on inverted T pin of obuft
Xilinx Answer #1293 : XC5200: UserClk must be enabled in Makebits before CK_DIV will be used.
Xilinx Answer #1294 : XC5200: 5200 schematic libraries contain 'BUFGP' and 'BUFGS' symbols
Xilinx Answer #1295 : BIDIRectional IOs with Viewsynthesis
Xilinx Answer #1297 : Xchecker: How can I use it on low-power "L" 3.3V parts?
Xilinx Answer #1299 : Verilog one-hot state machine
Xilinx Answer #1301 : XC5200: Programmable keeper cells are automatically enabled when all buffers are in 3-state mode
Xilinx Answer #1302 : M1.3/M1.4 CONCEPT2XIL/HDLCONFIG/VAN/SIR2EDIF: "Architecture not found" errors
Xilinx Answer #1303 : XNFPREP 5.2.x: ERROR 3582 issued because XC5200 does not have IOB registers
Xilinx Answer #1304 : Foundation/XABEL: "Synthesis Failed" when synthesizing ABEL file.
Xilinx Answer #1305 : XC5200: BUFG - different skew between clock pin and non clock pin.
Xilinx Answer #1306 : VHDL synthesis : tristate multiplexer versus combinatorial multiplexer.
Xilinx Answer #1308 : XC9500: How many outputs can you simultaneously drive at 24 mA?
Xilinx Answer #1309 : Design Manager : Cannot find data file "xc9500.bos" in the XACT path.
Xilinx Answer #1310 : The HW-112 Programmer is also known as the PP2
Xilinx Answer #1311 : men2xnf8/enwrite: Pin mapping from part interface to superseding interface not possible
Xilinx Answer #1312 : XC3000/XC4000/XC5200: PAR ERROR 4kpl:7 - Too many TBUFs (TRISTATEs) driving longline
Xilinx Answer #1313 : Why does Flow Engine run the XBLOX program on my non-XBLOX design?
Xilinx Answer #1314 : PPR error 7019 : Qualifier "[pattern]" on [spec_type] spec doesn't matchany [direction] pad.
Xilinx Answer #1315 : XDRAW/Xsimmake: Invalid KeyWord 'WINDOW_BACKGROUND'
Xilinx Answer #1316 : VHDL VITAL Library Support for XACT
Xilinx Answer #1317 : Foundation 6.x : Saving simulation probes and I/O signals
Xilinx Answer #1318 : PROMS: 1700 and 1700D/L package marking interpretation (duplicate)
Xilinx Answer #1319 : M1: EDIF2NGD doesn't recognize the parttype from a Viewlogic EDIF file.
Xilinx Answer #1320 : M1: EDIF2NGD: WARNING:0 - GLOBAL property on a net other than power or ground
Xilinx Answer #1321 : Design Manager reports: xmake is inaccessable
Xilinx Answer #1322 : Hardware debugger: Incorrect cable specification given.
Xilinx Answer #1323 : FPGA Express: What Xilinx software is needed if FPGA Express is the design entry tool
Xilinx Answer #1327 : XSI 5.2.1 4000e-4 are now available
Xilinx Answer #1330 : PROM FILE FORMATTER: Formatting large daisy-chained bitstreams for XChecker
Xilinx Answer #1331 : How to add XACT-Performance (Timespec) constraints to my CST file
Xilinx Answer #1332 : How to access the Xilinx anonymous FTP site with the IP address
Xilinx Answer #1333 : PCI macro: How to instantiate the macro using Verilog or VHDL
Xilinx Answer #1334 : ProCapture displays CB4CLED.1 symbol pins 'D0' and 'Q0' as diagonals
Xilinx Answer #1335 : XNFPREP Error 4717 when instantiating OSC5, OSC52, or CK_DIV in Synopsys.
Xilinx Answer #1337 : VERILOG-XL: Unconnected CE pin on register causes output to go unknown ("X")
Xilinx Answer #1338 : FOUNDRY, 4000E: Is the XC4000E architecture supported by Foundry 7.0?
Xilinx Answer #1339 : XNF2VERILOG/XNF2CDS may produce a net name that overlaps or conflicts with the name of another design element
Xilinx Answer #1340 : Foundation: using XNF files as macros
Xilinx Answer #1342 : Foundation: XC4000 CD4CLE macro counts independent of clock enable
Xilinx Answer #1343 : OrCAD Capture 6.x: How to import an ABEL file in Capture?
Xilinx Answer #1344 : XC4000: XDE- editlca: find RxCx returns the wrong block in 4013(E) - 4025(E)
Xilinx Answer #1346 : XNFMERGE: Warning Unrecognized Property 'HDL_SOURCE' on symbol 'sym_name'
Xilinx Answer #1347 : Can Xilinx Devices be wave soldered or immersed in solder?
Xilinx Answer #1349 : XABEL: How to assign preload value to registers in an EPLD
Xilinx Answer #1350 : XABEL: How to assign set/reset preload values to registers in an FPGA
Xilinx Answer #1351 : XC4000/E: How to install the 4025 and 4025E data files for the XACT 5.2.1/6.0.1 software from the CD-ROM (workstation and PC)
Xilinx Answer #1353 : Design Manager: Rhdexec.dat does not exist
Xilinx Answer #1354 : My CBxxx counter is not fast enough for my design
Xilinx Answer #1355 : Foundation: Can't print schematics to network printer under Windows 95
Xilinx Answer #1356 : BOUNDARY SCAN/JTAG: Can TDI, TCK, TMS and TDO be connected to a user signal and BSCAN?
Xilinx Answer #1358 : BOUNDARY SCAN/JTAG: How to attach a Pullup/Pulldown on the 4K TDO pin?
Xilinx Answer #1359 : BOUNDARY SCAN/JTAG: Pullup/Pulldown Availability in 5k TDO
Xilinx Answer #1360 : Error message when running XACT 6.0 on a network when translating
Xilinx Answer #1361 : XDM, XDE: Cannot select XDE from XDM with a XC5200 part
Xilinx Answer #1362 : Foundation XVHDL, JTAG: How to instantiate the BSCAN symbol for BoundaryScan
Xilinx Answer #1363 : Will a Pentium Pro or MMX instruction (P6) speed up Xilinx software?
Xilinx Answer #1366 : Foundation XVHDL: Using pullups and pulldowns
Xilinx Answer #1367 : JTAG/Boundary Scan:What is the app note is being refered to on page 3-14of the 7/96 Databook?
Xilinx Answer #1368 : How to submit a file on the Xilinx Customer Upload area on our FTP site
Xilinx Answer #1369 : PCI macro: Information on pipelining signals in PCI designs
Xilinx Answer #1370 : How do I set the graphics mode in XDE (editLCA) for DOS?
Xilinx Answer #1372 : Foundation XVHDL: How to lock down I/O pins
Xilinx Answer #1373 : Foundation XVHDL: How to use I/O Flip-Flops
Xilinx Answer #1374 : Foundation XVHDL: How to use Bidirectional I/O
Xilinx Answer #1375 : Foundation XVHDL: Using Global Buffers
Xilinx Answer #1376 : Foundation XVHDL: Using Global Set/Reset and STARTUP
Xilinx Answer #1377 : Foundation XVHDL: How to specify FAST Slew rate
Xilinx Answer #1379 : OrCAD Capture 7.0: Error CAP0044 empty pin number has been created for pin xx
Xilinx Answer #1380 : Configuration takes a long time.
Xilinx Answer #1381 : Workview Office: use VCD format with ViewTrace; fixes bad clock pulses in simulation
Xilinx Answer #1382 : PPR/Foundation: Duplicate name errors when guiding designs entered in Foundation
Xilinx Answer #1385 : XCHECKER SOFTWARE 5.2.1: Error 264 : Done signal did not go high, Error 265 : Init still low
Xilinx Answer #1386 : W/S License Manager: Why is there a feature line for VIEWLOGIC?
Xilinx Answer #1388 : XABEL/FOUNDATION: What is needed to compile a design containing XABEL blocks
Xilinx Answer #1389 : Xsimmake, Workview Office: Using Workview Office 7.1.2 or 7.2 with XACTstep 6.0.1 (Xsimmake failed)
Xilinx Answer #1390 : Operational level of voltage/current on FPGA inputs
Xilinx Answer #1391 : INSTALL: Hard Drive missing in the drive Status of the Set Path windows
Xilinx Answer #1393 : XEPLD Optimize: Unexpected error: epldinst.cc:40
Xilinx Answer #1394 : Workview Office: License exclusive restriction errors (1055, 8031, 8051)
Xilinx Answer #1396 : Foundation: Can you put LOCs on IPAD4/8/16 or OPAD4/8/16?
Xilinx Answer #1397 : CONCEPT: How to attach LOC properties to IPAD4/8/16 & OPAD4/8/16 macors
Xilinx Answer #1399 : XC5200: Recommended maximum sink and source currents
Xilinx Answer #1400 : XC9536: Does not have local feedback paths
Xilinx Answer #1402 : XChecker: "Done did not go high" for 5200 download.
Xilinx Answer #1403 : XC9500/XC7000: Translate warning 295: The LOC parameter 'LOC=FB1_16' on the macro symbol $1I1 is not supported for XC7000 designs
Xilinx Answer #1405 : DATABOOK 1996 Edition: Ambiguity regarding PG299 pins E5, E16, T5 and T16
Xilinx Answer #1408 : XC9500: What should be done with unused JTAG pins in the XC9500?
Xilinx Answer #1410 : SDT2XNF: Does it support Windows 95 and NT?
Xilinx Answer #1411 : OSC4.vli is not included in the XC4000E unified library.
Xilinx Answer #1412 : Foundation: Graphics toolbox buttons grayed out, graphics on sheet are gone
Xilinx Answer #1413 : Using Quicksim to simulation Synopsys synthesized design.
Xilinx Answer #1415 : HW-130, PROLINK/HW-120: Manufacturer and product code / product i.d. errors on 7300 devices
Xilinx Answer #1416 : CHECK or XNFPREP fail because of invalid characters in signal names
Xilinx Answer #1417 : HW-130: HW-112 (PP2) adapter compatibility with HW-130
Xilinx Answer #1418 : FLOORPLANNER: ATI video driver may cause general protection fault
Xilinx Answer #1419 : PPR error 5812 - Constraint file error
Xilinx Answer #1420 : PROMs: Can the VPP/VCC pin be tied through a resistor to +5V?
Xilinx Answer #1421 : Proseries: Design Manager: CPLD Fitter trims pins (IOPADs) when designing Bidir bus
Xilinx Answer #1422 : SDT2XNF: XC7000 design yields "Warning 003: Unknown primitive or macro FDCE "
Xilinx Answer #1423 : XC3000/XC4000: Are the internal tri-state busses(3k,4k) PULLED Up by default?
Xilinx Answer #1426 : Orcad VST all outputs are undefined
Xilinx Answer #1427 : Synopsys vhdldbx: internal system error, due to old library compile
Xilinx Answer #1428 : Configuration fails: CCLK does not toggle in master mode
Xilinx Answer #1429 : Workview Office: What Workview Office products should I install for a Xilinx restricted license? (OEM1/OEM2)
Xilinx Answer #1430 : ORCAD: DS32-VST-ERROR-030, symbol has incomplete pin information.
Xilinx Answer #1431 : ORCAD: Xnfprep trims ground and power signals from Orcad Capture
Xilinx Answer #1432 : HARDWARE DEBUGGER: Many internal signals cannot be selected
Xilinx Answer #1435 : Invoking XDM requires to be logged in as root
Xilinx Answer #1437 : OrCAD Capture 7.0: Fails to create xnf file
Xilinx Answer #1439 : XC73144: How to configure programmable ground option
Xilinx Answer #1440 : PROCapture 6.1: Can I print entire design and change fonts before printing?
Xilinx Answer #1441 : Timsim8 ends with return code 100 (XNFBA error 256) on non-Mentor XBLOX design
Xilinx Answer #1442 : XEPLD 6.x: Unexpected error detected, please report to Xilinx with reference "epldinst.cc40."
Xilinx Answer #1444 : Workview Office gives "Error" but no error message. (WVOinstall info)
Xilinx Answer #1445 : Viewsynthesis: STARTUP instantiation
Xilinx Answer #1447 : xnf2wir/xsimmake: General Protection Fault on Windows95.
Xilinx Answer #1448 : Fncsim8/XBLXGS: bad status 79501083 from ddp__create_sheet
Xilinx Answer #1449 : Possible Solution for Unexpected Error Detected. Reference writepif.cc:871
Xilinx Answer #1451 : How to run Viewsynthesis from DOS
Xilinx Answer #1453 : XC7336/XC7318: "Drive Unused IO Pads on Chip" option not available for 7336, 7318
Xilinx Answer #1454 : XC5200: LCA2XNF v5.2.1 writes out 5-input logic gates for XC5200
Xilinx Answer #1455 : XSI 5.2.1 .db files for synthesizing 5210-4, 5215-5, and 5215-6
Xilinx Answer #1456 : HardWire: XNFRPT -I
Xilinx Answer #1458 : Synopsys: Where can I get a list of all components I am able to instantiate? How can I get a listing of all library cell names in a XSI Library?
Xilinx Answer #1459 : How to get the pin order of a XSI Library Cell in Synopsys or How to getthe pins names for a XSI library cell
Xilinx Answer #1461 : XDE: Why is the INIT value shown for RAM/ROM different than what I specified?
Xilinx Answer #1463 : Foundation: Importing Viewlogic designs with multi-page macros
Xilinx Answer #1466 : Timing Analyzer 6.0.1: Cannot print .XRP from Timing Analyzer when running Windows 95
Xilinx Answer #1469 : FPGA Configuration: Xchecker - stand alone "ERROR 264: DONE signal did not go high"
Xilinx Answer #1471 : CADENCE: minimum install to support Verilog simulation of Xilinx designs
Xilinx Answer #1472 : XC3000: I/O Slew Rates and other AC parameters (rise/fall times)
Xilinx Answer #1473 : Foundation XVHDL: How to control the # of BUFGs which are automaticallyinserted.
Xilinx Answer #1475 : Download Cables: Difference between DLC-5 and DLC-4
Xilinx Answer #1476 : PRE-UNIFIED CARRY symbol: Not supported
Xilinx Answer #1477 : FPGA Express/Compiler: Possible Incorrect Logic with downto Range Integer Comparison in VHDL
Xilinx Answer #1478 : XC9500: Does Vccint have to be powered up before Vccio?
Xilinx Answer #1479 : CADENCE GXILINX: FAST property not translated to XNF file / adding support for user properties
Xilinx Answer #1480 : XC9500: Power consumption/dissipation information
Xilinx Answer #1481 : FGPA Express: How do you use pullups or pulldowns?
Xilinx Answer #1482 : Workview Office: Viewsynthesis SML semantic errors during synthesis: %PIN_LOAD
Xilinx Answer #1483 : FPGA Express 1.2, 2.0: How do you specify slew rate in FPGA Express
Xilinx Answer #1484 : Foundation XVHDL: Using XBLOX
Xilinx Answer #1485 : Foundation XVHDL: Using RAM and ROM in XC4000 devices
Xilinx Answer #1486 : Foundation XVHDL: Using CLB Latches
Xilinx Answer #1487 : Foundation XVHDL: Using Timespecs
Xilinx Answer #1488 : PCI macro: Target state machine goes into an invalid state after reset.
Xilinx Answer #1489 : M1 9500: How to use global clock nets
Xilinx Answer #1490 : XC9500: Device Slew Rates (Rise/Fall times) with capacitive loads
Xilinx Answer #1493 : PROFlow 3.0: About "PSFM !No resume"
Xilinx Answer #1494 : XC4000E/EX/XL/XV/XLT: Duty Cycle
Xilinx Answer #1495 : M1 and Workview Office: How do I set up concurrent licensing?
Xilinx Answer #1497 : XC3000: Must enable Crystal Oscillator Option in Makebits so OSC can be used.
Xilinx Answer #1498 : Foundation XVHDL: How to access a user-created VHDL library
Xilinx Answer #1500 : FPGA Express: Does FPGA Express have any 'scripting' capability?
Xilinx Answer #1501 : Foundation: Connecting a symbol bus pin to a bus of different width
Xilinx Answer #1502 : Foundation: BTRIEVE error 11: specified file name is invalid.
Xilinx Answer #1504 : Need two Project.lst files if using both XACT and XACT-CPLD and PROflow
Xilinx Answer #1506 : XACT: How to LOC (lock) pins and reserve/restrict pins via a constraintsfile
Xilinx Answer #1507 : Foundation: Adding parts and speed grades to the selection menus
Xilinx Answer #1509 : Foundation XVHDL: Win32s Error, Unhandled Exception Detected
Xilinx Answer #1510 : SYNERGY v4.4: Multiple source errors from XNFPREP because XNFOUT writesout OBUFT's instead of BUFT
Xilinx Answer #1512 : Foundation Install Error: VXD driver Daikon.386 missing
Xilinx Answer #1514 : 96 DATA BOOK: Missing dimension for HQ304 lead thickness 'c' on p11-37
Xilinx Answer #1516 : PPR error 6103: Possible Cause of "The EQN symbol ... has an invalid pin... "
Xilinx Answer #1518 : Foundation: Changing title block information or date on schematics
Xilinx Answer #1520 : XC2000L/XC3000L/XC4000L: Estimating power consumption for 3.3V Devices (2000L, 3000L, 4000L)
Xilinx Answer #1521 : syn2xnf : ERROR 220: Can't open file '__ffgen__.xnf'
Xilinx Answer #1522 : Differences between 4000ex and 5200 express mode?
Xilinx Answer #1523 : X9500: Using Local Feedback Paths
Xilinx Answer #1524 : ES-VERILOG 5.20 documentation is available on the Xilinx ftp site for the 5.20 Verilog-XL interface and Libraries
Xilinx Answer #1525 : Foundation Install: Hangs or give Fatal Exception while "Attaching Libraries"
Xilinx Answer #1527 : PRE-M1: CONCEPT, SYNERGY, VERILOG 4000E and 5200 libraries are availablefrom Cadence ftp as patches to 9504
Xilinx Answer #1529 : Cadence CONCEPT, VERILOG: Interim solution for doing 9500 designs beforeM1.0 release
Xilinx Answer #1531 : Viewsim: vsec error 1026 Required license not found for product Viewsim
Xilinx Answer #1532 : Workstation install: How to find a particular file on the Sun/HP 5.2.1 CD
Xilinx Answer #1533 : FUNCNET 9404: May create bad bidirectional pins
Xilinx Answer #1535 : Verilog naming rules for user-specified identifiers in Xilinx designs
Xilinx Answer #1536 : XC9500: How are unused I/O pins handled?
Xilinx Answer #1538 : PROMs: XC1736A Reset Polarity is not programmable
Xilinx Answer #1541 : ES-VERILOG/VERILOG-XL: Extraneous 4000E setup/hold violations on WCLK
Xilinx Answer #1542 : Foundation Install: shadow caused segment load failure lm_acs.dll
Xilinx Answer #1543 : Hardware Debugger: Parallel download cable will not work in Hardware Debugger.
Xilinx Answer #1544 : Design Manager 6.0.1: Translate in Win 95 produces a DOSGRAB "DOS mode" message
Xilinx Answer #1545 : Foundation Schematic: How to quickly locate nets in a schematic
Xilinx Answer #1546 : WIR2XNF ERROR: SEC: HOST is not in the HOSTS file. ERROR 4: IWINIT Failure.
Xilinx Answer #1547 : Foundation: Trying to open Project Manager exits Windows
Xilinx Answer #1548 : M1 V-System: VHDL/VITAL RAMs do not simulate properly or respond to stimuli on HP-UX
Xilinx Answer #1549 : Foundation: Selecting Using Help gives "not enough memory"
Xilinx Answer #1550 : PROsim: Simulation with OSC4.1: could not find WIR file xc4000:osc4.1
Xilinx Answer #1553 : OrCAD Capture 7.0: How to add the net attributes?
Xilinx Answer #1554 : EDIF 2.0.0 naming conventions and translation of escaped Verilog names to EDIF
Xilinx Answer #1555 : VERILOG-XL: warning! Cannot annotate PORT delay to MIPD for port
Xilinx Answer #1556 : Foundation XVHDL: how to use the OSC4 oscillator
Xilinx Answer #1557 : XNFBA error 301: Possible workaround
Xilinx Answer #1558 : Windows 95: help fails with three programs within XACTstep 6.0 program group
Xilinx Answer #1559 : "error #83 buffer too small" is given when starting PROcapture
Xilinx Answer #1560 : XC5200: CRC checking must be disabled in order to ensure INIT=HIGH during configuration in Express Mode
Xilinx Answer #1561 : ES-VERILOG: How to verify that it has been installed
Xilinx Answer #1562 : QuickSim: MODEL property expected but not found, NULL model will be inserted
Xilinx Answer #1564 : PCI macro: Possible simulation problem in Verilog XL due to net rename
Xilinx Answer #1565 : OrCAD Capture 7.0: xnfmerge error 20 caused by invalid pin record with TIMESPEC symbol
Xilinx Answer #1566 : FLOORPLANNER: Printing Problems in Windows 95
Xilinx Answer #1567 : XC3000/XC4000/XC52000: XACT 5.2- XNFMERGE: S attribute attached to OBUF output at top level gets dropped
Xilinx Answer #1568 : XNFMERGE 5.2.0: FAST, MEDFAST, MEDSLOW properties dropped when attachedto OFD/OUTFF/OBUF/OBUFT macros
Xilinx Answer #1570 : ABEL//PLD to XNF Translator: Pin not declared as output pin / No Equation outputs
Xilinx Answer #1571 : XEPLD/XABEL: xr2: [Error] Ignoring symbol with same name as previous symbol.
Xilinx Answer #1572 : XC9572: JEDEC file generation and JTAG programming support
Xilinx Answer #1574 : XChecker Cable: The order part number for xchecker cable.
Xilinx Answer #1575 : XC4000XL: 1996 DATA BOOK: Page 4-24 table 10.Supported Source for XC4000-Series Device Inputs is incorrect
Xilinx Answer #1576 : XDE issues messages on non-applicable TNM and Timespecs
Xilinx Answer #1577 : BOUNDARY SCAN/JTAG: Are there pullups/pulldowns in the TAP pins(XC4000, XC4000e, XC5200, XC4000EX)
Xilinx Answer #1583 : Foundation Schematic: Viewlogic Import error - cannot connect wire to symbol
Xilinx Answer #1585 : XACTstep 5.2.0 is shipped with Cadence releases 9404 through 9504 only
Xilinx Answer #1586 : Foundation: How to generate a schematic from an XNF file
Xilinx Answer #1590 : Viewsynthesis - vhdl error: the name "pfalling"/"prising" is undefined
Xilinx Answer #1594 : XACT-CPLD: rg37:[Warning] Programming output for device type 95144160 isnot supported
Xilinx Answer #1599 : M1 WS INSTALL : HP system requirement : HP unix 10.x
Xilinx Answer #1600 : LICENSING: How to check the version of the lmgrd license manager and XXACTD license daemons
Xilinx Answer #1601 : Foundation: Importing OrCAD Schematics to Foundation
Xilinx Answer #1602 : HW-130: What adapters do I need to program a 9500?
Xilinx Answer #1603 : XC9500: When can the XC9500 internal IOB pullups be accessed?
Xilinx Answer #1604 : M1: Pin Locking, I/O Constraints in UCF file
Xilinx Answer #1605 : EZTag Cable: May have problems programming 9500's from computers with EPP port
Xilinx Answer #1606 : Viewsynthesis: Unexpected Heap Error 6000
Xilinx Answer #1607 : M1 Constraints: How do I specify Timespec and Timegroup constraints in aUCF file
Xilinx Answer #1609 : 96 DATA BOOK: pps. 4-113 to 4-116 4025E / 4028EX/XL pinout shows 21 address pins
Xilinx Answer #1610 : Report Browser 6.0: File extensions for each report file and their locations.
Xilinx Answer #1611 : Foundation: Additional/Supplemental documentation is available on the FTP and BBS sites.
Xilinx Answer #1612 : Foundation VHDL: Can I use a testbench for VHDL-file simulation?
Xilinx Answer #1613 : Design Manager 6.0.1: Out of memory errors with Windows95
Xilinx Answer #1615 : XCHECKER SOFTWARE 5.2.1: What are the system memory requirement in orderto run?
Xilinx Answer #1616 : Xchecker Software and HARDWARE: Troubleshooting Guide. Warnings and Error messages explained
Xilinx Answer #1617 : XCHECKER SOFTWARE: What is the difference between xck88.exe and xchecker.exe?
Xilinx Answer #1618 : XC5200: How to use Direct Connect routing resources?
Xilinx Answer #1619 : Esperan VHDL Tutorial: Who to contact for more information.
Xilinx Answer #1620 : Esperan VHDL tutorial: Where are the example VHDL labs/files?
Xilinx Answer #1621 : PPR, XDELAY: Why timing/performance results differ in the two report files.
Xilinx Answer #1622 : Xaltran: How to install and use with Workview Office.
Xilinx Answer #1623 : Foundation Simulator: How to assign a value to a bus using Formulas
Xilinx Answer #1624 : JTAG/BOUNDARY SCAN: Does the XC4000/XC5200 require a special bitstream for JTAG Config?
Xilinx Answer #1625 : XC9500: Quiescent Supply Currents
Xilinx Answer #1626 : Foundation Simulator: Unknown outputs on 3K VHDL/ABEL/schematic design
Xilinx Answer #1629 : 9500 EZTAG: Patches/Updates are availible on Xilinx BBS/FTP site
Xilinx Answer #1630 : How to manually edit a prowave waveform
Xilinx Answer #1631 : XABEL-CPLD v6.1.2: JEDEC to ABEL Conversion not available under Win95
Xilinx Answer #1632 : XEPLD, XC7318, XC7336: nd100:[Error] (nd104, hi317) Could not map '<instance>' into a fast function block. (Fast Clocks)
Xilinx Answer #1633 : XEPLD, XC7318, XC7336: nd100:[Error] (nd105, hi317) Could not map '<instance>' into a fast function block. (Fast Output Enables, FOE)
Xilinx Answer #1634 : Printed Circuit Board (PCB) considerations of Xilinx devices
Xilinx Answer #1636 : M1 : Invoking LogiBLOX Graphical User Interface (GUI)
Xilinx Answer #1637 : M1-Pre: How to get MAP to report number of flip-flops, LUTs used
Xilinx Answer #1638 : XABEL,XACT-CPLD: Only one product term allowed for OE, Set, Reset, Clk (9500, 7300)
Xilinx Answer #1639 : OrCAD Capture 7.0: design rule check gives warning message:[DRC0014] forBUFT components
Xilinx Answer #1640 : XC9500: Where to find svf2xsvf.exe for ISP using the 8051 microcontroller
Xilinx Answer #1641 : XABEL-CPLD: Some hints on the error 'Done: failed with exit code: 0001'
Xilinx Answer #1642 : M1 : Examples of Timing Specification in the User Constraint File (.ucf)
Xilinx Answer #1643 : WIR2XNF 5.2.x: Check program failed, symbol for ___ is newer than WIR file
Xilinx Answer #1644 : M1.4: How to setup and debug Multi-Pass Place and Route/Turns Engine/Networked PAR
Xilinx Answer #1645 : 96 DATA BOOK: 4000E prom size (bits) page 4-57
Xilinx Answer #1646 : 96 DATA BOOK: XC4000EX Program Data and Prom size (bits), p. 4-58
Xilinx Answer #1649 : Design Manager 6.0.1: Translate--> XMAKE: ERROR: Failed to find part type <part> in 'partlist.xct'.
Xilinx Answer #1651 : XC3000/XC4000/XC5200: Can device I/Os be configured as an open-drain (open-collector)?
Xilinx Answer #1654 : XC5200: programmable weak keeper cells.
Xilinx Answer #1655 : CONCEPT: Sample CONCEPT2XNF.PROP file from 9504 Cadence release
Xilinx Answer #1657 : Foundation: How to use a library macro as a template for a user-defined macro
Xilinx Answer #1659 : XC4000E/EX/XL/XLT/XV: M1- TBUF net Delay 4000EX - Effect of the Pullup.
Xilinx Answer #1661 : 4000 device bitstream compatibility
Xilinx Answer #1663 : Foundation Base Package: After entering the password what will xkey -r show?
Xilinx Answer #1664 : Design Manager 6.0.1: PPR - "Error XLM:KEY_NOT_FOUND" (LPT Conflict). Using Win 95.
Xilinx Answer #1666 : XABEL,XACT-CPLD: What Xilinx packages come with XABEL(DS371) and XACT-CPLD(DS560)?
Xilinx Answer #1668 : Xilinx online documentation available on FTP site
Xilinx Answer #1669 : XABEL-CPLD: Out Of Memory error or long compile times (@CARRY directive)
Xilinx Answer #1670 : SYNOPSYS : The output of replace_fpga still contains CLB element/write command fails in FPGA Compiler
Xilinx Answer #1671 : XDM 5.2: The Translate Menu does not have XEMAKE underneath it
Xilinx Answer #1672 : What is the purpose of DONEIN, Q1Q4, Q3, Q2 on STARTUP macro?
Xilinx Answer #1673 : M1 : HDL flow with LogiBLOX, implementation and simulation files.
Xilinx Answer #1675 : XC5200/XC4000E/EX/XL/XV: How flip-flop initial states are determined forFPGAs.
Xilinx Answer #1676 : PPR 5.2.1: Hangs the machine, doesn't respond
Xilinx Answer #1677 : M1.5 EPIC has no Printing Capability
Xilinx Answer #1678 : IBIS Models are now availible on the Xilinx Anonymous FTP site
Xilinx Answer #1679 : Checking the Hardware and software requirement on Workstation and PC.
Xilinx Answer #1680 : XNFPREP 5.2.1: Error 7859:'C2P' type TS attribute 'TSxx' need an associated TS flag attached to a net or pin.
Xilinx Answer #1681 : How do I specify a bidirectional I/O in my schematic?
Xilinx Answer #1682 : Design Manager 6.0.1: Unfamiliarly named filesystem, ParcPlace Systems, FATFilename
Xilinx Answer #1683 : TIMING ANALYZER 6.0.1: Discrepancy between Timing Analyzer and Xdelay
Xilinx Answer #1684 : XACT-CPLD, Foundation: How to switch between XC9500 software and XACTStep w/o rebooting
Xilinx Answer #1685 : Install: How to install XACT 5.2.1 on a HP ver 10.20
Xilinx Answer #1686 : Old part works on board, but the new Xilinx part does not! --Asynchronous design.
Xilinx Answer #1687 : XC3000/XC2000: Makebits- CRC checking does not exist for configuration in 2K and 3K devices
Xilinx Answer #1688 : XACT-CPLD, 9500: What do my environment settings need to be?
Xilinx Answer #1689 : Foundation XVHDL: missing TNM attribute will cause XNFPREP Error 7845
Xilinx Answer #1691 : EZTAG: Can FPGAs be mixed in with 9500 devices when using the JTAG cable?
Xilinx Answer #1692 : 17256D PROM recall--device ID errors (two lot codes only)
Xilinx Answer #1693 : Foundation HDL Editor: Performing a text search causes PC to lock up.
Xilinx Answer #1694 : VERILOG-XL: How to specify libraries for different family devices in a multi-chip simulation
Xilinx Answer #1695 : 96 DATA BOOK:page 4-358 commercial voltage range for 3100A
Xilinx Answer #1696 : 96 DATA BOOK: Solder time for Maximum soldering temperature is incorrectfor 9500 parts
Xilinx Answer #1697 : XC1765DPD8C PROM: "Selected algorithm (1765D) is not correct for the device in the socket (1736D)"
Xilinx Answer #1699 : XACT Timing Analyzer: Cannot open file C:\\con<num>.<num> (Win95 only)
Xilinx Answer #1700 : XC9500: Test process of devices before shipment
Xilinx Answer #1701 : XC9500: "Single Cell Charge Loss" (SCCL) or "Single Bit Charge Loss" (SBCL)
Xilinx Answer #1703 : XC7300: Can I use a product term Output Enable in a Fast Function Block (FFB)
Xilinx Answer #1704 : Prom File Formatter 6.0.1: Where does the concatenated file go for a daisy-chained prom file?
Xilinx Answer #1706 : XABEL: How to get test vectors (.TMV file) into an XC9500 JEDEC file
Xilinx Answer #1707 : XC9500: Minimum RESET signal pulse width
Xilinx Answer #1708 : XC4000E Synopsys Libraries: XC4000E -2 .db files available for users of XSI 5.2.1 & Synopsys 3.3b and above
Xilinx Answer #1709 : XC3000 Synopsys Libraries: XC3100A -1 and -09 .db files available for users of XSI 5.2.1 & Synopsys 3.3b and above
Xilinx Answer #1710 : XNF2WIR Error 13: Unsupported XNF netlist version '6'.
Xilinx Answer #1711 : XABEL-CPLD 6.1.2: Is this an automatic upgrade to v6.1.1?
Xilinx Answer #1712 : 7300: Fast clock driver is connected to non-fast clock pin
Xilinx Answer #1713 : win 95: Simulation Utility fails with "Path/File access error"
Xilinx Answer #1715 : TNM attached to net between PAD and IBUF/BUFG not forward traced
Xilinx Answer #1716 : CADENCE/GXILINX: Using pre-5.0 (9403 or earlier) Cadence interface withXACT 5.x
Xilinx Answer #1717 : XABEL-CPLD: Does it run under Windows 95?
Xilinx Answer #1718 : Diamond Speed Star 64: Translate or Design Manager hanging
Xilinx Answer #1719 : The 4025E does not have address pins A18:A21, these are on EX/XL devicesonly.
Xilinx Answer #1720 : M1: Solaris install from HP mounted CD gives "Could not write directory"
Xilinx Answer #1722 : CONCEPT2XIL Error #169: Port modes are not the same. The entity declaration needs to be updated
Xilinx Answer #1723 : XC5200: Use of DI pin to a flipflop in a Logic Cell (LC)
Xilinx Answer #1724 : vhdlan/vhdldbx:Limits of VHDL/Verilog Simulation in the Current XSI Flow
Xilinx Answer #1725 : xnf2vss: What is the purpose of the .vxnf file produced by xnf2vss?
Xilinx Answer #1726 : Why isn't there a PCB footprint for any of Ceramic BRAZED CQFP package(CB100,CB164,CB196,CB228)
Xilinx Answer #1727 : CONCEPT2XIL/HDLCONFIG: Warning: No acceptable view exists for cell AND2 in library <path_to_library>
Xilinx Answer #1728 : CONCEPT2XIL: Warning! verilog.v in calc_lib.glbl is not a link - leavingit [Van-LIBSRC]
Xilinx Answer #1729 : Workview Office: Error 8031: Flex/LM Error: Cannot find license file[-1,73:2]
Xilinx Answer #1730 : Foundation: Esperan Master Class Lite workbook, where can I get it?
Xilinx Answer #1732 : Design Manager 6.0.1: Error - "Cannot find input design. Please specify an existing design"
Xilinx Answer #1735 : Change->LogiBLOX does not reliably update symbol in Workview Office
Xilinx Answer #1736 : Kernel Limitations May Cause Out of Memory Problems on the HP Platform
Xilinx Answer #1738 : Control C Does Not Abort the Installation Procedure
Xilinx Answer #1743 : The -p Option of XNF2NGD Does Not Override the PART Statement in the XNFFile
Xilinx Answer #1744 : Parameterized Attributes in the Viewlogic Viewdraw Schematic Editor Are Not Supported by Xilinx Tools
Xilinx Answer #1745 : ILDFFDX and ILDFLDX Library Components Have Been Renamed
Xilinx Answer #1746 : EDIF2NGD Uses a Special Property Filtering Mechanism for a Mentor Designthat Requires the Mentor PM to Be Installed (Mentor Graphics)
Xilinx Answer #1751 : ViewDraw Symbols May Not Be Updated Properly After Entering a Change LogiBLOX Command
Xilinx Answer #1752 : Invoking the LogiBLOX GUI the First Time Could Take More Than 15 Seconds
Xilinx Answer #1757 : FPGA Compiler: Pullup/Pulldown Resistors are Deleted From Synopsys Design
Xilinx Answer #1758 : XCHECKER 5.2.1: Xchecker standalone files are available on the FTP site
Xilinx Answer #1759 : DC2NCF Requires libC.sl Library on the HP Platform
Xilinx Answer #1763 : M1 - RLOCs May Not Be Attached to Hard Macros
Xilinx Answer #1769 : TNT.41400: INITEMULATOR:FLOATING POINT EMULATOR (EMUTNT.DLL) IS REQUIRED
Xilinx Answer #1771 : Can a 4000E or 5200 lead a 4000EX in a daisy chain?
Xilinx Answer #1772 : Makeprom: Where can I find a Workstation version of psplit?
Xilinx Answer #1773 : xc4000e: dp-ram:xnfprep gives segmentation fault, core dump
Xilinx Answer #1777 : Problems with Back-Annotation of Designs Containing Single CLB Replication Groups which are Not Eliminated by MAP
Xilinx Answer #1778 : Design Summary is Located at the End of the MRP (Map Report) File
Xilinx Answer #1784 : Synopsys/Design Compiler: Insert_pads->"This site is not licensed for FPGA compiler"
Xilinx Answer #1785 : SYNOPSYS: How to force a IOB NODELAY latch or flip-flop?
Xilinx Answer #1786 : bitgen 7.0: Does bitgen 7.0 do a length count alignment of the bitstream?
Xilinx Answer #1787 : 4000EX/XL: Can I use both the Output FF (OFD) and the Output MUX (OMUX2)of an IOB at the same time?
Xilinx Answer #1788 : 4000EX: Can I use a tri-state buffer (OBUFT) with the Output MUX (OMUX2)?
Xilinx Answer #1789 : xmake 6.0.1: l.s01.1: /usr/xilinx/bin/sparc/xsifix: fatal: relocation error: symbol not found
Xilinx Answer #1790 : 96 DATA BOOK: 95108 PQ160 does not have No Connects listed.
Xilinx Answer #1791 : XC9500F: Does it support JTAG functionality?
Xilinx Answer #1792 : Foundation Schematic: How to control output slew rate
Xilinx Answer #1794 : Design Manager 6.0.1: Translate issues "cannot copy translated netlist"
Xilinx Answer #1795 : 4000E/EX: Can the BUFGLS, BUFGE, and BUFFCLK (4000X) and BUFGP and BUFGS (4000E) be driven with Internal Logic?
Xilinx Answer #1797 : Foundation Install: Where can I find XABEL program to install it?
Xilinx Answer #1798 : Foundation Simulator: Where are custom Formulas stored?
Xilinx Answer #1799 : XABEL-CPLD: "Done: failed with exit code: 0003" when running Fitter
Xilinx Answer #1800 : fpga compiler: Wire load not found "parttype-s_wc"
Xilinx Answer #1801 : XC7300: MR (Master Reset) Pin can optionally be used as an input
Xilinx Answer #1802 : Synopsys FPGA Compiler: Error OPT-101: The target library does not contain inverter.
Xilinx Answer #1810 : M1.3 MAP: BLKNM, HBLKNM, RLOC and LOC Properties May Not be Respected byMAP in Some Instances
Xilinx Answer #1815 : ppi2040:[Error] The instance '$1I1/O' of component type 'OBUFT' is not supported or...
Xilinx Answer #1818 : M1.2/M1.3/M1.4 MAP: Exact Guide Mode May Not Recreate All COMPs from Initial Design Even When the Source Design Has Not Changed
Xilinx Answer #1821 : DATA I/O v5.3 algorithm 1700D programming failures: Device will not program, fails low voltage verify, CEO fails to assert
Xilinx Answer #1824 : HW-130: Programming 73144 yields "Warning! Programming Error at Address XXXX"
Xilinx Answer #1826 : XNFPREP Error 3649: Possible cause if using CC8CLED with Orcad Capture 7.0
Xilinx Answer #1827 : VERILOG: Support for XNF to Verilog translation on the PC
Xilinx Answer #1828 : HW-112 ALERT: 17256D and 17256 verification problems
Xilinx Answer #1829 : Bitstream compatability of the 3000, 3000A, 3000L, 3100 and 3100A devices.
Xilinx Answer #1832 : M1: Getting XACT and M1 License Files to use same license manager.
Xilinx Answer #1833 : UART design available as part of RS-232 interface application note
Xilinx Answer #1835 : Foundation: After unzipping archived project, errors updating xnf netlist
Xilinx Answer #1836 : The oscillator in the 4000 FPGA is disabled (if OSC4 unused) after configuration.
Xilinx Answer #1837 : What is the absolute junction temperature Tj for plastic and cermaic parts?
Xilinx Answer #1838 : Foundation: Netlist Conversion Error Missing pin <pin> of <symbol> or library error
Xilinx Answer #1839 : Foundation XVHDL: How to use Wide-Edge Decoders
Xilinx Answer #1840 : Foundation XVHDL: Setting NODELAY property on inputs
Xilinx Answer #1842 : XC7336: Programming gives product ID error
Xilinx Answer #1843 : QuickSim: Mode pins (MDO, MD1, MD2) cannot be used in board-level simulation.
Xilinx Answer #1844 : Mentor schematic: Adding an INIT property to a CPLD flip-flop
Xilinx Answer #1845 : Cables: Xchecker, Parallel, and JTAG Cables what do they do and how do Iidentify them?
Xilinx Answer #1846 : XABEL-CPLD: Controlling optimization using 'keep' and 'LOGIC_OPT'
Xilinx Answer #1861 : M1.3/M1.4 PAR/MAP: TBUFs with RLOC Constraint Must be Part of RPM with RLOC_ORIGIN Constraint
Xilinx Answer #1863 : Back-Annotation Timing Data May Contain Overly Conservative Values for the Setup Requirements of Some IOB Input Flip-Flops and Latches. Physical Post-lay out Simulation Occurs When NGDAnno Is Called Without a Reference to the NGM File .
Xilinx Answer #1864 : M1.1.1a NGD2VER Writes Out a Verilog Output File with a `uselib Line Indicating the Location of the Simprim Libraries
Xilinx Answer #1867 : M1.5 TRCE: IOB register to PAD paths (and vice-versa) are not reported or controlled
Xilinx Answer #1868 : Guaranteed External Setup and Hold Times Are Not Reflected in the Software
Xilinx Answer #1869 : Long Runtimes for Some Designs
Xilinx Answer #1870 : Logical Resources Are Not Listed in Timing Reports
Xilinx Answer #1871 : M1 TRCE: Reports May Contain Preliminary Timing Values
Xilinx Answer #1872 : Clock Skew Not Accounted for in Path Analysis
Xilinx Answer #1873 : Hardware Debugger Cannot Communicate With HP-10.x OS Serial Port
Xilinx Answer #1883 : M1: ERROR:basnb - SECURITY ERROR --Unable to lock license for ngdbuild: license file syntax (-2,134:2) No such file or directory
Xilinx Answer #1884 : XC9500: What is the guaranteed spec for Data Retention?
Xilinx Answer #1885 : M1Security is Based on FLEXlm, and Requires Lmgrd v4_1 and Xilinxd
Xilinx Answer #1890 : Moisture sensitivity level: Where to find this information??
Xilinx Answer #1891 : XABEL-CPLD6.1.2: problem with OLE server registration
Xilinx Answer #1893 : M1, Workview Office: Viewlogic library description file (LIBS.LST) for Workview Office/M1
Xilinx Answer #1894 : PPR 5.2.1: Execution on PC is slow on Windows 3.11?
Xilinx Answer #1895 : VERILOG-XL board level simulation SDFA Error: Type of INSTANCE xxxx doesnot match CELLTYPE <cell_name> in Verilog-XL.
Xilinx Answer #1896 : M1 QuickSim: GSR (global set/reset) port removed from XC4000EX library
Xilinx Answer #1897 : XC3000/XC3000/XC4000/XC5200: Logic cells and the FPGA Density Cross Reference Guide
Xilinx Answer #1898 : MAP M1.1.1a: -os speed causes BITGEN-DRC ERROR:0 - netcheck: no source pins found on signal
Xilinx Answer #1899 : XC9500: Using Timespecs for tSU (setup time must include GCK delay)
Xilinx Answer #1900 : NGDBUILD (csttrans) M1.1.1A: ERROR:0 - Could not find INST(S) <signal name> in design
Xilinx Answer #1901 : PCI User's Guide: BHx_DEC, BHx_OE equations have incorrect terms
Xilinx Answer #1902 : Check issues warnings on ASHEETP, ASHEETL, BSHEETL, etc
Xilinx Answer #1903 : Foundation Simulator: Unknown outputs on XBLOX or VHDL design
Xilinx Answer #1904 : FLow Engine 6.0.1: Error - Command line exceeds allowable limit
Xilinx Answer #1905 : Foundation HDL Editor: Code isn't highlighted with different colors properly.
Xilinx Answer #1907 : 2000L,3000L,3100L,4000L,4000XL: How do these 3.3V parts differ from their 5V counterparts?
Xilinx Answer #1908 : Global reset polarity in 2K, 3K, 4K/E/EX, 5K, 7K, and 9K devices
Xilinx Answer #1909 : OrCAD Simulate: How to use Xilinx's global reset and tri-state signals for functional simulation?
Xilinx Answer #1910 : 5.2.1: HP install Fatal Error 6015 cannot open file to write cdrom ...
Xilinx Answer #1912 : 4000E: Bare die, what should the backside (substrate) connected to?
Xilinx Answer #1913 : Available patches for M1.1.1a 4KEX Pre-release...
Xilinx Answer #1915 : Merging license files for M1 and XACT-Step on WorkStations...
Xilinx Answer #1916 : NGDBUILD m1.1.1a: error 0:Unable to lock license for ngdbuild, no such feature exists.
Xilinx Answer #1918 : 7336, PROMs: Using the 7336 as a virtual SPROM
Xilinx Answer #1921 : PROsim: Out of Memory when loading a VSM file
Xilinx Answer #1923 : M1 and MTI: How to compile the HDL simprim, LogiBLOX, Unisim, and Coregen libraries (VHDL and Verilog)
Xilinx Answer #1924 : Prowave: Sharing violation error
Xilinx Answer #1925 : XC5200: XACT 5.2.1- xnfprep: Error 4708
Xilinx Answer #1928 : 96 DATA BOOK: No pinout for the XC4036EX in a HQ240 package
Xilinx Answer #1929 : Xc9500: The fitter report pinout does not match that of the data book
Xilinx Answer #1931 : Flow Engine 6.0.1: Message "Could not find 2018.spd" during compilation of XC4000 design
Xilinx Answer #1932 : XNFPREP 6.0.1: Error 3525:Symbol `name' (type = INFF, output signal = WS0) has invalid pin CE
Xilinx Answer #1934 : Foundation Simulator: Can I prevent my design from being flattened for functional simulation?
Xilinx Answer #1935 : XC5200: What is the T(TSHZ) spec for 5200?
Xilinx Answer #1937 : PPR 5.2.1: Possible Cause of PPR error 9016 if using Floorplanner
Xilinx Answer #1938 : Foundation Schematic: Adding Attributes - LOC, X, etc.
Xilinx Answer #1939 : Timing Analyzer 6.0.1: Error - ctl3d32.dll This is not the correct version
Xilinx Answer #1940 : XNFMERGE : Warning 285. Net names and symbol pin names do not match.
Xilinx Answer #1941 : In BYTE-WIDE parallel configuration which is the MSB D7 or D0?
Xilinx Answer #1942 : XC4000XL: VTT connections on 4000XL pinouts...
Xilinx Answer #1943 : CONCEPT: CAPSLOCK_OFF and its effect on translation of lower-cased pin name properties
Xilinx Answer #1944 : dsgnmgr M1.1.1a: "Cannot find tool definition file..."
Xilinx Answer #1947 : FPGA Express v1.xx: App note available on FPGA Express XACT 5.2.x flow and M1 flow
Xilinx Answer #1948 : xc4000EX cclk maximum frequency specification
Xilinx Answer #1949 : Are M1 BIT files compatible with XCHECKER 5.x?
Xilinx Answer #1950 : Foundation: "File specified in $FILE parameter is missing" when pushing into macro
Xilinx Answer #1952 : Foundation: Service Pack Install - Setup will not run
Xilinx Answer #1954 : XNFMERGE: how does it recognize what is a primitive vs. what is a macroin an XNF file?
Xilinx Answer #1956 : XACT-CPLD, XC9500: Assertion failed: ia.RetSize()==1 && ia[0]->RetInputInstance(), file outinst.cc
Xilinx Answer #1958 : Flow Engine 6.0.1: How to speed up the Translate step (wir2xnf) in XACT 6.
Xilinx Answer #1959 : Prowave: Can't load .wfm file into Prowave
Xilinx Answer #1960 : OrCAD Capture 7.0: XMAKE 5.2.0 fails to find user defined subhierarchy for 4kE design
Xilinx Answer #1962 : OrCAD Capture 7.0: How to access 9500 libraries for schematic capture?
Xilinx Answer #1963 : PPR: Design not routing (unroutes) because placement is to tightly packed.
Xilinx Answer #1964 : XNF specification: Naming Conventions for nets, buses, components and pins
Xilinx Answer #1965 : Hardwire: Power consumption?
Xilinx Answer #1966 : Viewsynthesis: BSCAN and Mode pin instantiation
Xilinx Answer #1967 : Viewsynthesis: PULLUP/PULLDOWN instantiation
Xilinx Answer #1969 : XNFPREP: ERROR 3525: Symbol 'U117' (type = INV, output signal = BCLOCk-)has an invalid pin 'O-'.
Xilinx Answer #1970 : XMAKE 5.x: File beltypes.dat not found
Xilinx Answer #1972 : Foundation Express 2.0.x: multiple modules in Foundation schematic can cause RLOC error:x4kma:312 in MAP
Xilinx Answer #1974 : Protel support for Xilinx libraries?
Xilinx Answer #1975 : How to lock down I/O pins in Exemplar
Xilinx Answer #1976 : EZTAG: WARNING: Part type "XC95xxx" is supported only in BYPASS mode.
Xilinx Answer #1978 : Foundation XABEL: "XABEL is not installed" error when synthesizing ABELcode
Xilinx Answer #1980 : PPR 5.2.x: Relaxing PPR timespecs in xactinit.dat
Xilinx Answer #1981 : For PQ100 package, how to identify pin 1 since there are 2 holes on the package
Xilinx Answer #1982 : ngdbuild m1.1.1a: Prohibit pin locations in ucf file.
Xilinx Answer #1983 : NGDBUILD M1.1.1a: Invalid UCF/NCF file entry value detected while searching for PART
Xilinx Answer #1984 : bitgen m1.2.11: Configuration Address Pins A18 - A21 are optional; xc4000EX only
Xilinx Answer #1985 : M1.3/M1.4,Workview Office : Adding custom functions to ViewDraw (EDIFNETO/EDIFNETI/LogiBLOX)
Xilinx Answer #1986 : Foundation: After copying a project, some files are missing
Xilinx Answer #1987 : XC9500/XC7300: How to preserve/keep/save or prohibit software from using certain pins
Xilinx Answer #1988 : XC4000E: Creating Synchronous or Dual port RAM for MemGen
Xilinx Answer #1989 : FPGA: Input/Output pin levels on various family of devices.
Xilinx Answer #1991 : M1.3/M1.4 CONCEPT/HDL DIRECT--Iterated Instance methodology replaces SIZE property
Xilinx Answer #1992 : CONCEPT HDL DIRECT: *ERROR* - CLA internal error - Invalid Parameter
Xilinx Answer #1994 : SDT2XNF: What is the latest version of inf2xnf ?
Xilinx Answer #1996 : SDT2XNF,INF2XNF 5.2.1: DECODE4.XNF missing DECODE property
Xilinx Answer #1997 : Design Manager M1: Fails to start (hangs/core dumps) on UNIX machines
Xilinx Answer #1998 : XC5200: What is the value of the weak pull-up on an I/O?
Xilinx Answer #1999 : XC5200: What level are the I/O pins on an unprogrammed 5k device?
Xilinx Answer #2000 : OrCAD Capture 7.0 : How to create a symbol to represent an XNF file?
Xilinx Answer #2001 : M1: What are the differences between node-locked and floating licenses?
Xilinx Answer #2003 : M1: Win95/NT Release: Overall Installation and License issues
Xilinx Answer #2004 : XABEL-CPLD (DS-571-PC1):How to print the on-line help
Xilinx Answer #2005 : CONCEPT2XIL/HDLCONFIG on HPPA 9.05: crt0: ERROR couldn't open /usr/lib/dld.sl errno:000000002
Xilinx Answer #2006 : 96 DATA BOOK: XC5210 and XC5215 BG225 pinout has an error for pins H9 and H6:
Xilinx Answer #2010 : Foundation XVHDL: message "No entity bound to this instance"
Xilinx Answer #2011 : XSimmake 5.2.1, Workview Office 7.3.0 or newer: check/vsm_ngui fail under XSimmake script
Xilinx Answer #2012 : Input and Output parameters (i.e. setup times) from XDELAY don't match those listed in Data Book.
Xilinx Answer #2013 : Running lmgrd brings up network to be logged in
Xilinx Answer #2015 : Dynatext Browser: dtext quits with bus error when executed from Solaris CDE.
Xilinx Answer #2017 : xc4000E/EX/XL and 5200: Difference between the preamble/length count of XC4000/E/EX and the XC5200
Xilinx Answer #2018 : XNFMERGE, CONCEPT 9402: ERROR: Cannot find PWR.XNF or GND.XNF / How to connect a pin to VCC
Xilinx Answer #2019 : XNF Specification: What is difference between T and B direction in an EXT record?
Xilinx Answer #2026 : Configuration: APM - Can RDY/BSY be used to signal start of configuration instead of INIT?
Xilinx Answer #2027 : What does abreviation "BSC" mean in package dimensions
Xilinx Answer #2029 : XC9500: Programming an XC9500 CPLD with a microcontroller (ISP)
Xilinx Answer #2033 : 4000XL: Inputs are 5V compatible
Xilinx Answer #2034 : Flow Engine 6.0.1: xnfprep error 7804: CST file doesn't exist
Xilinx Answer #2037 : M1/XSI v1.1.1a: Template runscripts in $XILINX/synopsys/examples are incorrect
Xilinx Answer #2039 : NG2VER, NGD2XNF: Unable to copy temporary file ...
Xilinx Answer #2040 : Packaging: Test Clip Manufacturers
Xilinx Answer #2042 : CONCEPT2XIL/LOGIBLOX: "Unknown child port declaration" / "Architecture not found errors"
Xilinx Answer #2043 : FLOORPLANNER 6.x: Driver problem (macxw4.drv) with Win95
Xilinx Answer #2044 : PC Hangs: Some S3-based video card Drivers are incompatible with WIN32S
Xilinx Answer #2046 : Bad Workview Office 7.2 CDs have been sent out by Xilinx
Xilinx Answer #2047 : XC9500: Are XC9500 CPLD devices PCI compliant?
Xilinx Answer #2050 : XNFMERGE 5.2.1: INTERNAL ERROR: 293
Xilinx Answer #2051 : XNFPREP 5.2.1: Errors 7822, 7854 from constraints file TIMESPEC
Xilinx Answer #2052 : M1: C vol serial # starting with zero: ERROR:basnb - SECURITY ERROR --Unable to lock license for ngdbuild
Xilinx Answer #2053 : CADENCE CONCEPT2XNF, XNFOUT: Support for Concept/Composer interface license generation
Xilinx Answer #2054 : CADENCE VERILOGLINK, VHDLLINK, FET-Concept, Framework missing in 51021 licenses
Xilinx Answer #2055 : M1.0 CADENCE XIL2CDS: XIL2CDS hangs on HP-UX v10.20
Xilinx Answer #2056 : CONCEPT2XIL/SIR2EDF: " Error! Cell name not specified" errors
Xilinx Answer #2058 : BP MICROSYSTEMS, 9572: 9572 support missing in current v3.23 algorithm
Xilinx Answer #2059 : xc4000EX/XL: Asynchronous Peripheral Configuration from MCS file causes INIT to go low.
Xilinx Answer #2060 : Workview Office: Project Manager issues "unexpected file format" and "invalid page fault"
Xilinx Answer #2062 : XBLOX: Running XBLOX on remote Solaris machine gives "UNIX error ENOENT"after loading defaults.qofRunning XBLOX for Sun4 on Solaris on remote machine gi ves "UNIX error ENOENT" after loading defaults.qof
Xilinx Answer #2063 : PROMS: XC17128L and XC17256L Data I/O programming support now available
Xilinx Answer #2064 : Design Manager 6.0.1: Error "unhandled exception, invalid file name" onstartup
Xilinx Answer #2065 : HW-130/XC95216: Product code errors when programming a device
Xilinx Answer #2066 : Foundation Schematic: PPR ERROR 9028 when using COMPMC8 macro in 5200 design
Xilinx Answer #2068 : 96 DATA BOOK: Inconsistency in Pinout for 4025E PG299 package
Xilinx Answer #2069 : QuickSim II: Output of XBLOX BUS_IFxx component is X
Xilinx Answer #2071 : CB228, CB196, CB164, CB100: Where do customer get the pins formed?
Xilinx Answer #2072 : map m1.1.1a: A parsing error has occurred at line 2, token 'P124'.
Xilinx Answer #2074 : LCA2XNF 5.2.1: Outputs an Inaccurate .xnf file
Xilinx Answer #2075 : Viewsynthesis: How to disable automatic XBLOX insertion
Xilinx Answer #2076 : Problem with pin mismatch, macro in Workview Office, xnf from Synplicityor FPGA Express
Xilinx Answer #2077 : DATA I/O: "ERROR: Incompatible user data for device selected" when programming 9536 with a JEDEC file / Notes on JEDEC file format
Xilinx Answer #2078 : Cadence Concept XC4000E: ofdtxi flip-flop powers-up reset instead of setin Hardware.
Xilinx Answer #2079 : 7336 part programmed by BP Micro programmer works, but HW-130 programmedpart does not--LOWPWR problem
Xilinx Answer #2080 : SYNOPSYS 3.x: Set_max_delay attribute is not passed on to .sxnf
Xilinx Answer #2081 : Foundation Schematic: How to replace a symbol without deleting nets
Xilinx Answer #2082 : ngdbuild m1.1.1a: Parameter 'SLEW' is not allowed on symbol '$1I1' of type 'OFDX'.
Xilinx Answer #2083 : XDM: XC4025E part is not displayed, even though partlist.xct is correct
Xilinx Answer #2084 : XEPLD 6.0: hi604: [Warning] Unexpected TIMESPEC string ignored
Xilinx Answer #2085 : 3000L: speed files and TQ144 package file
Xilinx Answer #2087 : FPGA Compiler: Synopsys design yields XNFPREP 1303; multiple hierg-records
Xilinx Answer #2089 : M1/FPGA Compiler: Sometimes set_false_path/set_max_delay not translated by write_script
Xilinx Answer #2090 : XNFPREP 5.2.1: error 4572 and error 4573
Xilinx Answer #2091 : Makebits 5.2.1: XDE, XDM and commandline differences in Default options for a 4000e and a 5200 part
Xilinx Answer #2092 : Design Manager 6.0.1: OE20 Caused an Invalid Page Fault (Illegal Operation) in Windows 95
Xilinx Answer #2093 : XC7000: Device Slew Rates (Rise/Fall times)
Xilinx Answer #2094 : PPR 5.2.x: XC5200 design with Readback gives ERROR 9905: NET "$I417/CLK"has no source
Xilinx Answer #2095 : Workview Office: Viewsynthesis support is available for XC9500 family.
Xilinx Answer #2097 : Foundation Simulator: Greek fonts appear in the Waveform Editor
Xilinx Answer #2098 : What are the Thresholds for the Configuration Pins of the xc4000/E/L/EX/XL Families?
Xilinx Answer #2099 : M1: NGDBUILD fails with Multiple Driver errors. EDIFNETO option missing
Xilinx Answer #2100 : M1 PLD_EDIF2TIM: Error: Cannot find library specified "SIMPRIMS"
Xilinx Answer #2103 : PRE-M1.0 CADENCE CONCEPT: Invisible property SIG_NAME="GSR \G": Illegal HDL name: illegal character after signal or port
Xilinx Answer #2105 : 96 DATA BOOK/ISP APPLICATION GUIDE: Inconsistency in High-drive output current
Xilinx Answer #2106 : CADENCE/GXILINX: Netnames can be created that contain a "#" sign (xnfprep 3517)
Xilinx Answer #2108 : HW-130, XC1700/D/L: Device FAILED Low Vcc or Low Voltage Verify
Xilinx Answer #2109 : 9500 Fitter Report Equation Syntax
Xilinx Answer #2110 : Foundation HDL Editor: ABEL state diagram template gives grounded outputs.
Xilinx Answer #2116 : COREGEN: SYNOPSYS VHDL FLOW
Xilinx Answer #2118 : V1.4.0, V1.5.0 COREGEN, JAVA: This program has performed an illegal operation /page fault in module WINAWT.DLL on Windows (display settings problem)
Xilinx Answer #2121 : CONCEPT XC5200: <COMPERR> ERROR(195): Cannot open specified attributes file, File name=/tmp/property.dat4291
Xilinx Answer #2122 : M1.3/M1.4: CONCEPT2XIL, NGD2VER, VERILOG-XL: Error! Instance specific item not found in `uselib path. Directory : <path_to_library>
Xilinx Answer #2126 : 9500 ESD information
Xilinx Answer #2128 : NGDBUILD issues basgb error : Memfile cannot be found
Xilinx Answer #2129 : HW-130: programmer displays "HW-133-PG84" when TQ100 adapter is used.
Xilinx Answer #2130 : M1 Licensing: Using a workstation as a server for PC and workstation applications
Xilinx Answer #2132 : 96 DATA BOOK: 3064APQ160/3164APQ160 pinouts pin 2 and pin 3 should be N.C. pins
Xilinx Answer #2133 : 9500: xchecker rcab error 4059
Xilinx Answer #2135 : Xmake fails during OrCAD Annotate: program does not support incremental annotation
Xilinx Answer #2136 : HW-130: Installation tips for SunOS workstation platforms
Xilinx Answer #2137 : SYNOPSYS: Analyzing SIM yields "VHDL syntactic or semantic error detected"
Xilinx Answer #2138 : M1/XACT: How do I add comments to my constraints file?
Xilinx Answer #2139 : Are 9500 Inputs 5 volt tollerant when Vccio is 3.3 volts?
Xilinx Answer #2140 : Foundation: Difference between I/O Pads and I/O Terminals
Xilinx Answer #2141 : M1.3/M1.4: Design Manager: "illegal command line for invoking the Flow Engine"
Xilinx Answer #2142 : Hardware Debugger 6.0.1: .ll file not found
Xilinx Answer #2144 : XC9500: How long does it take to carry out various JTAG instructions in 9500 CPLDs?
Xilinx Answer #2145 : SYNPLIFY: How to instantiate PULLUP/PULLDOWN in HDL (Verilog/VHDL)?
Xilinx Answer #2146 : XC9500: How to place a macrocell/signal in low power mode (LOWPWR or PWR_MODE)
Xilinx Answer #2147 : XACT_CPLD: Hitop - This program has performed an ilegal operation.....
Xilinx Answer #2148 : Where to get the FPGA Demo Board Schematic?
Xilinx Answer #2149 : JTAG Programmer: M1.1.1a - JTAG programming software gives error:0
Xilinx Answer #2150 : XC9500: The high level output voltage of an 9500 CPLD is ~4 volts
Xilinx Answer #2152 : Foundation: BTRIEVE error 88 - incompatible mode error
Xilinx Answer #2153 : FLOORPLANNER 6.x: Cannot see STARTUP, READBACK, of BSCAN symbols in my foorplanner.
Xilinx Answer #2155 : Definition of a "gate", when defining number of logic gates in a FPGA
Xilinx Answer #2157 : bitgen m1.2-WS: TIE option may cause incorrect functionality.
Xilinx Answer #2162 : Exemplar Galileo 3.2.5: Known issues with Galileo-generated XNF files
Xilinx Answer #2163 : M1.2.11 HITOP: Hitop Exception error (WinNT), PROGRAM ABNORMALLY TERMINATED (Win95)
Xilinx Answer #2165 : Hardware Debugger 6.0.1: Message - Cannot get the startup directory.
Xilinx Answer #2166 : Cable not recognized: Eztag hangs when execute is pressed
Xilinx Answer #2171 : M1 NT Pre-Release: Patch for TRCE and PAR "Memory Allocation Error"
Xilinx Answer #2172 : XDM, Design Manager 5.2.1: Returns " <speed grade> is not a valid speed grade"
Xilinx Answer #2173 : PPR: FATAL ERROR: The msg set for "msg" does not exist
Xilinx Answer #2174 : XC9500: Hitop.exe fails erroneously saying too many pins are used on 9500 design
Xilinx Answer #2177 : OrCAD Capture: Design rule check gives "no matching pin" error for OFD16component
Xilinx Answer #2178 : CPLD/EPLD Quality Assurance: How are Xilinx xc9500/xc7300 parts tested?
Xilinx Answer #2181 : M1: ERROR: basnb - SECURITY ERROR -- Unable to lock license for ngdbuild: Cannot find license file (-1,73:2) No such file or directory
Xilinx Answer #2183 : 4000XL/4000EX switching characteristics (rise/fall)
Xilinx Answer #2185 : CADENCE Verilog-XL Error! (SHM) Database locked by another client
Xilinx Answer #2187 : M1.5 EPIC: How do I change the default display colors and fonts?
Xilinx Answer #2189 : M1.3 VERILOG-XL: Toggling global reset and tri-state using M1 mixed modeUnified simulation libraries.
Xilinx Answer #2190 : XDELAY 5.2.1: Doesn't IGNORE the path specify by the TIMESPEC IGNORE attribute
Xilinx Answer #2191 : map m1.2-ws: FATAL_ERROR:baste:bastetspec.c:2317:1.62 - NET OFFSET...
Xilinx Answer #2193 : MAP Warning:baste:102 - Logic enclosed by Fmap symbol '..' has too many inputs
Xilinx Answer #2195 : BOUNDARY SCAN/JTAG: Do Update Latches and Data Registers get reset in Test Logic Reset State?
Xilinx Answer #2196 : 5200: Readback with xchecker on 5202 devices
Xilinx Answer #2197 : What are the differences between Synopsys FPGA Compiler and Design Compiler?
Xilinx Answer #2199 : ngdbuild: Unexpanded blocks. Design from Exemplar Leonardo.
Xilinx Answer #2200 : HDL Synthesis guide pp 1-8 & 1-9: Location of design files is wrong.
Xilinx Answer #2201 : ppr Error 9004: The IOPAD must be placed in a dedicated pad location.
Xilinx Answer #2202 : M1.4: CADENCE LEAPFROG--Simulating VHDL designs in the Xilinx M1 release
Xilinx Answer #2203 : Xsimmake reports no license for schematic in Pro Series
Xilinx Answer #2205 : PPR 5.x: Possible cause of ERROR 9929
Xilinx Answer #2207 : M1 map: What are the rules for merging FFs into an IOB with the MAP -pr b switch?
Xilinx Answer #2208 : EZTAG: EZTAG.EXE cannot be run as a DOS application under Windows NT
Xilinx Answer #2209 : V1.4.0 CORE Generator: Foundation Schematic Flow
Xilinx Answer #2210 : Bitgen M1.2 - Bitgen/PAR patch available on FTP site.
Xilinx Answer #2211 : XC4036EX/XL: HQ240 package list is missing information
Xilinx Answer #2212 : VERILOG-XL Environment Error: Parent node XXXXX not found
Xilinx Answer #2213 : M1.5 EPIC: How to read the CLB carry mode
Xilinx Answer #2214 : Workstation Install: Invalid License Key (inconsistent encryption code for....
Xilinx Answer #2215 : CPLD: OPT=MERGE
Xilinx Answer #2216 : CONCEPT HDL Direct Error: Invisible property SIG_NAME="GR \G": Illegal HDL name: illegal character after signal or port name
Xilinx Answer #2217 : What do the Xs and @s mean in the Fitter report?
Xilinx Answer #2218 : M1.2.11 - Speed file patch for xc4000xl and xc4000ex
Xilinx Answer #2220 : Foundation Express: Edit Constraints option greyed out; cannot access Constraints GUI
Xilinx Answer #2221 : Map M1.2.11 - Patch available on the FTP site for several issues.
Xilinx Answer #2222 : M1: install over Novell network gets "can't find license file" error.
Xilinx Answer #2223 : M1.4 Cadence Concept interface: Frequently asked questions
Xilinx Answer #2226 : M1: Difference between FEATURE and INCREMENT line in license.dat file
Xilinx Answer #2227 : M1: Design Manager help ->ld.so.1:hyperhelp:fatal:libXmu.so.4:can't openfile: errno=2
Xilinx Answer #2229 : PROM File Formatter 6.0.1: Page Fault (illegal operation) during Save PROM Operation
Xilinx Answer #2230 : FPGA Express: Using RLOC_ORIGIN with Express RPMs
Xilinx Answer #2231 : M1.2.11: JTAG program gives 'Communications with the cable could not be established'
Xilinx Answer #2232 : M1.2.11 MAP: FATAL_ERROR:x4kma:x4kmabel.c:161:1.37 - Didn't find out signal on bel G
Xilinx Answer #2234 : M1 MAP/NGDBUILD, LogiBLOX: Pin mismatch between block ... at pin ....
Xilinx Answer #2235 : M1: LogiBLOX Memfile will not accept all Memgen conventions
Xilinx Answer #2236 : PROMS: Differences between XC1700 and XC1700D PROMs
Xilinx Answer #2237 : M1: LogiBLOX core dumps with Illegal Instruction on a HP-UX 9.07
Xilinx Answer #2238 : M1: LogiBLOX "Simple Gates" options have invalid Styles in menu
Xilinx Answer #2239 : M1: LogiBLOX will not always "Stop on Warning"
Xilinx Answer #2240 : M1: LogiBLOX warnings are not indicated in NGDBUILD summary
Xilinx Answer #2241 : M1: LogiBLOX will not save vendor information for vendor "Other"
Xilinx Answer #2242 : M1: LogiBLOX will not accept a memfile without a file extension of ".mem"
Xilinx Answer #2243 : M1.3/M1.4/M1.5 CPLD: Fitter takes more than 200 Megs of RAM while fitting a design
Xilinx Answer #2244 : NGD2EDIF M1.3: WARNING:basnu - This design contains the undriven net "<net name>"
Xilinx Answer #2245 : M1.3(FPGA Compiler): Versions of Synopsys compatible with M1.3 XSI
Xilinx Answer #2246 : M1.3 JTAG Programmer: Doesn't check to make sure proper 9500 device package is used
Xilinx Answer #2247 : NGDBUILD/MAP: WARNING:basnu - Parameter "SLEW" is not allowed on symbol
Xilinx Answer #2248 : Design Manager M1: Configuration Template does not contain option for creating MASK file
Xilinx Answer #2249 : M1.3/M1.4 MAP, XC4000EX CCxxCLE counter library macros: WARNING:x4kma - Signal xxx on pin G4 of CY4 symbol is not required by carry mode INC-F-CI
Xilinx Answer #2250 : M1.3/M1.4 JTAG Programmer: Unnamed device added to chain if you Cancel from Add Device
Xilinx Answer #2251 : M1: LogiBLOX invoked from Solaris 5.4 may give "_ex_keylock" error
Xilinx Answer #2252 : M1.3: Failure to program a 9500 device on Windows NT using the JTAG cable
Xilinx Answer #2253 : M1.3(VITAL): Where are the VITAL libraries in the M1.3 release?
Xilinx Answer #2254 : FPGA Express: Instantiating OFDIs gives warning message, "'xxx/GS' is not connect to any net..."
Xilinx Answer #2255 : M1: Concept HDL Direct gives "Error#171: Port exists in entity declaration..."
Xilinx Answer #2256 : NGDBUILD: WARNING:basnu:11 - Ignoring unexpected data value "true" on "FAST" property
Xilinx Answer #2257 : Design Manager M1: The User Constraint File (design.ucf) is used even ifnot specified
Xilinx Answer #2258 : M1.3(FPGA Compiler)-Common issues/solns when re-compiling M1.3 XSI XDW libraries
Xilinx Answer #2259 : M1: Concept XC7000 ifdx1 input register will preload to "0" in Verilog Unified Library functional simulation
Xilinx Answer #2260 : M1.3/M1.4 MAP: Running map with -os area may yield a larger implementation than with -oe normal
Xilinx Answer #2261 : M1.3/M1.4 JTAG Programmer: Only Parallel cable seen if both Xchecker and Parallel cables connected
Xilinx Answer #2262 : Design Manager: The difference between "Version" and "Revision"
Xilinx Answer #2264 : NGDBUILD: Launcher: NOT compiling module.ngo because its source was not found
Xilinx Answer #2266 : Flow Engine M1: Text in status window flickers during compile
Xilinx Answer #2267 : FPGA Express: Deleting Multiple Files from the Express Project Window
Xilinx Answer #2268 : M1.3/M1l4: Concept2xil causes NGDBUILD to issue "ERROR:based:48-..Duplicate port a in cell "alias_bit".
Xilinx Answer #2270 : FPGA Express v1.1: Does not allow Verilog parameters used as indices forarrays
Xilinx Answer #2271 : Hardware Debugger M1.3: Verify Bitstream finds bits mistched.
Xilinx Answer #2272 : Flow Engine M1: Flow Engine log area is truncated at the top
Xilinx Answer #2273 : M1.3/M1.4 JTAG Programmer: Files are "missing" when programming across platforms
Xilinx Answer #2274 : M1.3 MAP: Designs which fit a target XC4000/E/L device in XACT may not fit when mapped with the M1 Mapper due to register ordering
Xilinx Answer #2275 : FPGA Express v1.1: Cannot pass INIT attribute on RAM to the .xnf file
Xilinx Answer #2276 : M1: Concept->MAP: WARNING:basnu - RAM symbol .. of type "ram32x1s" with INIT value "0000": INITSTATE string shorter than width of the ROM
Xilinx Answer #2277 : Design Manager M1: How to change background colors from grey to white onworkstations
Xilinx Answer #2278 : Cadence board-level simulation M1: The -pf option not supported in Design Manager
Xilinx Answer #2280 : M1.3/M1.4 Map: Map fails to pack RLOC'd carry logic in RPMs (Relationally Placed Macros) with LOC'd DFFs.
Xilinx Answer #2281 : M1.3 MAP: Automatic insertion of GSR/GR is not supported in M1.
Xilinx Answer #2282 : FPGA Express: Does not accept or output EDIF files.
Xilinx Answer #2283 : HDL timing simulation: compiling testbench reveals port mismatches
Xilinx Answer #2284 : Design Manager M1: Design Manager does not start when I double click theicon (PC)
Xilinx Answer #2286 : Hardware Debugger M1.3: Download, Verify, and Debug menu commands are not executed.
Xilinx Answer #2287 : FPGA Express: Opening up Express to an Existing to a User Default Location
Xilinx Answer #2288 : M1.3 MAP: BEL-level PROHIBIT constraints are not supported
Xilinx Answer #2289 : M1.3 MAP, XC4000E/L/EX/XL: Map cannot use the DI input to source an HMAP(xc4000e/ex/xl)
Xilinx Answer #2290 : M1.3 MAP, PAR: ERROR - Resolved that macro M12X12/BR5/hset is unable to be placed due to other locked logic or prohibited sites.
Xilinx Answer #2291 : M1.3 MAP: Unable to pack CLB driven by 2 external signals with DFFs sharing an SR signal.
Xilinx Answer #2292 : NGDBUILD: Core dump when trying to translate XNF files for 7K devices
Xilinx Answer #2293 : Hardware Debugger M1.3: Cannot print Macro files.
Xilinx Answer #2294 : M1.3 MAP: where is the report summary?
Xilinx Answer #2295 : M1.3 MAP: Version number of Mapper is not reported in the .MRP report file
Xilinx Answer #2296 : M1.3/M1.4 JTAG Programmer: ERROR:basut - no functional test vectors in JEDEC file
Xilinx Answer #2297 : Flow Engine M1: Aborted Place & Route, limitations on saving intermediate results
Xilinx Answer #2298 : M1.3/M1.4 MAP may generate Wide Decoder groups that cannot be placed/routed.
Xilinx Answer #2299 : Flow Engine M1: Constraints in UCF file not read
Xilinx Answer #2300 : Hardware Debugger M1.3: DEBUG menu commands not executing.
Xilinx Answer #2301 : M1.3 MAP: ERROR:x4kma:312 - Unable to obey design constraints which require the combination...
Xilinx Answer #2302 : M1: How to find the C Vol Serial Number and ethernet address?
Xilinx Answer #2303 : M1.3/M1.4 JTAG Programmer: Software will allow Verify of Read-Protected device in SVF mode
Xilinx Answer #2304 : MAP: Logic attached to EQNs may be left dangling
Xilinx Answer #2305 : Design Manager M1: Error when selecting help on help.
Xilinx Answer #2307 : M1.3/M1.4 CPLD: Fitter issues spurious nd14 warnings
Xilinx Answer #2308 : M1.3 MAP: Map doesn't validate PROHIBIT constraints before writing themout.
Xilinx Answer #2309 : M1.3 MAP does not report which TIMESPEC is used when there are duplicateTIMESPECs
Xilinx Answer #2310 : Hardware Debugger M1.3: Debug operations do not affect target board.
Xilinx Answer #2311 : M1.3(vhdlan): Common issues/solutions re-compiling the M1.3/M1.4 XSI simulation libraries
Xilinx Answer #2312 : M1.3, M1.4 MAP: 'ERROR: baste:125 - The RLOC value of "R62C2.FFY" on CLB .... in RPM ....'. The design is too large for the given device and package (c an't fit design).
Xilinx Answer #2313 : Hardware Debugger M1.3: Waveform Signal Display window scrolls do not function properly.
Xilinx Answer #2315 : Flow Engine M1: Using a user-modified PCF file
Xilinx Answer #2316 : Template Manager M1: Error "For the Report limit value, please enter integer.."
Xilinx Answer #2317 : M1.3 MAP: The design summary section of the map report file (.mrp) is ambiguous.
Xilinx Answer #2319 : M1.3 MAP gives misleading error: ERROR:0 - BLKNM parameter not supportedon WAND symbol
Xilinx Answer #2320 : M1.3/M1.4 CPLD: Ngdbuild does not accept xtf files created by previous versions of xact - abnormally terminated
Xilinx Answer #2321 : Design Manager M1: Configuration Template does not support 4kex & 4kxl higher-order addresses
Xilinx Answer #2322 : Hardware Debugger M1.3: Display Signals window displays all "tied" signals.
Xilinx Answer #2323 : Hardware Debugger M1.3: Uppercase MACRO commands are invalid.
Xilinx Answer #2325 : Design Manager/Flow Engine M1: Crashes during cut and paste
Xilinx Answer #2326 : Flow Engine M1: Can not generate back-annotated XNF files for XC7000 or XC9000 devices
Xilinx Answer #2327 : M1 CPL: PWR_MODE attribute cannot be placed on non-logic symbols
Xilinx Answer #2328 : Configuration: Enabling Express Mode through the Design Manager
Xilinx Answer #2329 : M1 Xilinx Design Manager - Abel is not a valid file entry format
Xilinx Answer #2330 : Design Manager M1: EPIC loads the placed & routed design though in mapped state
Xilinx Answer #2331 : M1 NGDBUILD: ERROR:basts:68 - NET...which has a NET OFFSET...not pad-related...
Xilinx Answer #2332 : M1.3/M1.4 Map: How to ignore RLOCs / Map does not have a built-in ability to ignore RLOCs completely (or, the meaning of the MAP "-ir" option)
Xilinx Answer #2333 : Design Manager M1: How to change the default report browser/editor/viewer
Xilinx Answer #2334 : M1.3/M1.4 CPLD: Fitter warning xr5100 - Inserting an output buffer
Xilinx Answer #2335 : Hardware Debugger M1.3: Cable Self Check fails or doesn't run specified number of cycles.
Xilinx Answer #2336 : M1.3/M1.4 CPLD: Fitter warning xr5049 - invalid 'BUFG' parameter
Xilinx Answer #2337 : M1.2/M1.3/M1.4 MAP: "place instance *" constraint causes ERROR:x4kma:148 - IBUF symbol cannot be merged, incompatible site types
Xilinx Answer #2338 : EZtag: SVF file generation mode does not work when data security is enable.
Xilinx Answer #2339 : M1.3/M1.4 CPLD: TIG (Ignore Timing) timing constraint not supported
Xilinx Answer #2340 : Hardware Debugger M1: No popup-menu for the console window.
Xilinx Answer #2341 : M1.3/M1.4 CPLD: Fitter does not recognize the vcc labelled net as a special net name
Xilinx Answer #2342 : M1.3 JTAG Programmer: Output -> Cable Setup breaks cable connection
Xilinx Answer #2343 : DATA I/O / Synario: SUPPORTS XC9500 family devices
Xilinx Answer #2344 : Design Manager M1: Can not read configuration specified in CONFIG symbol
Xilinx Answer #2345 : M1.3 MAP: "Unable to obey design constraints" errors / Unsupported CLB combinations involving dual output logical components (DPRAM, RAM16x2)
Xilinx Answer #2346 : Hardware Debugger M1.3: "Signal List is Empty" when Displaying signals from Console.
Xilinx Answer #2347 : Hardware Debugger M1: Missing newline charactor when reading UNIX macrosin Win95 or WinNT4.0
Xilinx Answer #2348 : Design Manager M1: Report Browser cant open reports after Design Implement
Xilinx Answer #2349 : NGDBUILD: NCF file not considered in determining file-generation dependencies
Xilinx Answer #2350 : Hardware Debugger M1: Changing the color of the wavforms in the waveformwindow
Xilinx Answer #2351 : Hardware Debugger M1.3: "Need to define some signals to display" from Pulse RESET.
Xilinx Answer #2352 : M1.3: JTAG Programmer Error Message when downloading with device in bypass mode
Xilinx Answer #2353 : Hardware Debugger M1.3:Hardware debugger features, eg download, not available on command line
Xilinx Answer #2354 : Design Manager M1: Design Manager claims tools are running although theyare not
Xilinx Answer #2355 : Hardware Debugger M1.3: Available signals list do not follow bit order.
Xilinx Answer #2356 : Hardware Debugger M1: Can not communicate with non-standard port names
Xilinx Answer #2357 : Hardware Debugger M1.3: Console command "port auto" doesn't work on win95 and NT4.0
Xilinx Answer #2358 : Design Manager/Flow Engine M1: Report Browser shows wrong translation report
Xilinx Answer #2359 : Flow Engine M1.3: Multi-Pass Place & Route summary report not shown until completion
Xilinx Answer #2360 : Flow Engine M1: ERROR: basut -switch "-l" is excluded or already used
Xilinx Answer #2361 : Flow Engine M1: ERROR: basut -Argument"../xc4000ex.ngd" has an invalid extension.
Xilinx Answer #2362 : M1.3 MAP: What do "Clock IOBs" mean in the MAP report ?
Xilinx Answer #2363 : M1.3 MAP: How can I estimate the total number of packed CLBs in my design?
Xilinx Answer #2364 : M1.3/M1.4 MAP: "ERROR 0 - FMAP symbol - RLOC parameter suffix doesn't match block type" on single-flip-flop macros
Xilinx Answer #2366 : M1.3 MAP: ERROR: BLKNM parameter not supported on WAND symbol (4K family)
Xilinx Answer #2367 : M1.3 MAP: MAP DRC does not check the validity of RLOC and LOC location constraints on fast carry logic
Xilinx Answer #2370 : GTS (on the STARTUP block) must be held low if unused in Verilog designs
Xilinx Answer #2371 : A schematic may be written despite error from reserved names used in design
Xilinx Answer #2372 : xc3000/XC4000E/EX/XL/XC5200: Output capacitance is same as input capacitance.
Xilinx Answer #2373 : NGD2VHDL and NGD2VER will not write out a netlist with no top-level ports
Xilinx Answer #2374 : Timing error reported for both flop and RAM, but only applies to RAM
Xilinx Answer #2375 : NGDANNO uses the max value only when different drivers drive the same net
Xilinx Answer #2376 : NGDBUILD skips other constraints in .ucf after finding an invalid one
Xilinx Answer #2377 : NGDBUILD is case sensitive with respect to TNM's and TIMESPEC's
Xilinx Answer #2378 : A file with a .XTF extension may be picked up when a .EDN file is specified
Xilinx Answer #2379 : SYNPLIFY: How to lock down I/O pins in HDL (Verilog/VHDL)?
Xilinx Answer #2380 : M1.3 JTAG Programmer: Programming a 9500 device fails intermittently on a Solaris machine
Xilinx Answer #2381 : Timing Analyzer: Sun - Using middle mouse button to copy & paste closes application
Xilinx Answer #2382 : Timing Analyzer: Using arrow keys to execute previous commands does not work
Xilinx Answer #2383 : Timing Analyzer: "Macro /tmp/xil_922 failed" - what does this mean?
Xilinx Answer #2384 : Timing Analyzer: Can I insert comments into macros?
Xilinx Answer #2385 : Timing Analyzer: Expected one number greater than or equal to 0.000000
Xilinx Answer #2386 : FPGA/CPLD: Do FPGA and CPLD inputs have Hysteresis?
Xilinx Answer #2387 : vhdldbx: Error vhdlsim, 259 sdf file line ##: instance xsim4 not found.
Xilinx Answer #2388 : M1.2-WS: Why doesn't the M1 license.dat list the xc9500 in the Components section?
Xilinx Answer #2389 : Timing Analyzer: TIMINGAN caused an invalid page fault in module LIBBASTW.DLL
Xilinx Answer #2390 : Foundation: Btrieve 12 : Lmacs, cannot find the specified file (*.HDR)
Xilinx Answer #2391 : Timing Analyzer: When selecting sources/destinations, everything is grayed out
Xilinx Answer #2393 : Timing Analyzer: Using Shift F8 to select items in dialogs does not work
Xilinx Answer #2394 : Timing Analyzer: After applying a filter in a dialog, how do I un-apply it?
Xilinx Answer #2395 : Timing Analyzer: What does "Filter for <items> Not to be Selected" mean?
Xilinx Answer #2396 : Timing Analyzer: Keyboard shortcut for File -> Open Physical Constraintschanges
Xilinx Answer #2397 : M1.3 MAP: User-defined TIMESPEC constraints added outside the "SCHEMATIC" section of the .PCF file are commented out by MAP
Xilinx Answer #2398 : PAR M1.3 - PAR appears to ignore soft range constraints
Xilinx Answer #2399 : PAR M1.3 - PAR placement rules are too strict for comps driven by BUFGE.
Xilinx Answer #2401 : PAR M1.3 - PAR may crash using -p switch (no placement) on partially placed design.
Xilinx Answer #2402 : PAR M1.3 - PAR may crash with page fault saving 4000e design. WIN95 only.
Xilinx Answer #2403 : PAR M1.3 - PAR may fail if an RLOC_RANGE overlaps an RLOC.
Xilinx Answer #2404 : PAR M1.3 - PAR fails to list boundry scan components in .pad report.
Xilinx Answer #2405 : PAR M1.3 - PAR may fail with segmentation fault processing offset constraints.
Xilinx Answer #2406 : PAR M1.3 - PAR may crash if there are more than four pullups on a net.
Xilinx Answer #2407 : PAR M1.3 - PAR may crash if guided place and route is mixed with re-entrant routing.
Xilinx Answer #2408 : PAR M1.3 - XC4000E designs ported to XC4000XL may have unroutable carry chains.
Xilinx Answer #2413 : M1/ Synplicity: MAP gives "ERROR:x4kma-Unable to obey design constraints"
Xilinx Answer #2415 : FPGA Express v1.2: LogiBLOX in the FPGA Express v1.2 Verilog or VHDL M1.3 Flow
Xilinx Answer #2416 : M1.4: How to auto-start a floating license on the PC?
Xilinx Answer #2417 : SYNOPSYS: Logical Library does not map to a host directory.
Xilinx Answer #2418 : M1: MAP->"FATAL_ERROR:baste:bastetspec.c:908:1.64 - No pins of NC_SIGNAL... NC_BEL
Xilinx Answer #2419 : Design Manager/Flow Engine M1: Screen turns black when Flow Engine is invoked
Xilinx Answer #2423 : XC5200: What is the delay setting for the IOB when driving logic insteadregisters?
Xilinx Answer #2424 : Readback: Performing microprocessor based Readback for Verification or internal probing
Xilinx Answer #2426 : Foundation Simulator: high impedence on output of OSC4
Xilinx Answer #2427 : Hardware Debugger: Polarity of Reset signal is active low
Xilinx Answer #2428 : What is HMGEN?
Xilinx Answer #2430 : Design Manager 6.0.1: Screen goes black during Translate. (DOSGRAB in Win95)
Xilinx Answer #2431 : M1: Powerview/Viewdraw->"vscript: Error 4307: logiblox.vs: Unbound variable-RequireFac"
Xilinx Answer #2432 : M1, VERILOG: What is needed to support Verilog simulation of Synopsys and other third party platform designs
Xilinx Answer #2435 : M1.5 TRCE/Timing Analyzer: 0 paths analyzed for a TIMESPEC which should have paths
Xilinx Answer #2436 : PPR 5.2.1: error 11221: design name 12345 is illegal
Xilinx Answer #2438 : Bitgen M1.2.11 - Incorrect bitstream for wrapped carry configuration on XC4000E
Xilinx Answer #2439 : M1.3 XIL2CDS: ERROR : get_pwr_pin_name -- invalid pin # - '24' on targetBGA package
Xilinx Answer #2443 : TRCE M1.3: Paths that include RAMs deeper than 16 address cells not analyzed.
Xilinx Answer #2444 : Hardware Debugger 6.0.1/M1: What points can I probe during in-circuit debugging/readback?
Xilinx Answer #2445 : M1: Win95/NT license, lmutil lmhostid returns hostid of 0 or FFFFFFFF
Xilinx Answer #2446 : Configuration: Async Periph mode, RDY/BSY state when DONE is held low
Xilinx Answer #2448 : Foundation M1 Beta 2: Incorrectly uses MYXILINX environment variable
Xilinx Answer #2449 : M1.5: Basic UCF Syntax Examples for Design Placement and Timing Constraints
Xilinx Answer #2450 : 5.2.1 : How to import a Synopsys submodule into a Viewlogic Schematic
Xilinx Answer #2452 : M1.2.11 95288 report file contains additional pins as GND not listed in the databook
Xilinx Answer #2459 : PPR error 1476 :error in mxn file:Illegal mxn name on line <> of file <>in data high.pb
Xilinx Answer #2461 : Does makeprom have the s-records file format?
Xilinx Answer #2462 : HITOP M1.2.11: nd7331 - Input 'sclk_int' assigned to FCLK1 is used in logic.
Xilinx Answer #2463 : Replacement for the 1700DDD8R (Obsolete) is the 1700DDD8B
Xilinx Answer #2464 : XC4000E, ES-VERILOG library OFDTX simulation model: Z at output generates an X, which propagates to output through feedback path
Xilinx Answer #2469 : 9500 EZtag download gives error 126: unsupported command
Xilinx Answer #2471 : 9500: What is PRLD in the CPLD simulation?
Xilinx Answer #2472 : Hardware Debugger: Setting up printer on Unix Workstations
Xilinx Answer #2473 : Hardware Debugger: Printing and Print Preview causes Illegal Instructionor Application Error
Xilinx Answer #2474 : LogiBLOX M1.x-WS: How to estimate CLB/area utilization for logiblox modules with map.
Xilinx Answer #2476 : CONCEPT2XIL/SIR2EDF: "Error! Invalid command-line option -instlib"
Xilinx Answer #2477 : MAP:ERROR:x4kma:243 - The suffix "FFX" is illegal for dff symbol
Xilinx Answer #2478 : M1 QuickHDL: How to compile the HDL simprim, LogiBLOX, and Unisim libraries
Xilinx Answer #2479 : M1.3 install: cp: cannot create /tmp/xilinx/./perl.sol: Permission denied
Xilinx Answer #2480 : M1.3: NODELAY Attribute may be ignored in .ucf file without warnings or errors.
Xilinx Answer #2482 : M1.3 MAP, Design Manager: PROGRAM ABNORMALLY TERMINATED / seg fault in Design Manager may be due to numerical net or block names
Xilinx Answer #2483 : M1.2/M1.3/M1.4 MAP: Refsite is unavailable / Constraining overlapping RPMs to the same CLB range (RPM "zippering") is not supported
Xilinx Answer #2484 : Foundaton Simulator: 'assign' in command file gives incorrect state value.
Xilinx Answer #2485 : M1 QVHCOM: Could not open library simprim/logiblox/unisim, unknown identifier
Xilinx Answer #2492 : MAP Error: ld.so.1: map: fatal: relocation error: symbol not found:
Xilinx Answer #2493 : M1: Using the MYXILINX environment variable, correcting ld.so errors
Xilinx Answer #2494 : M1: Debugging problems while using Install Shield
Xilinx Answer #2496 : MAKEBITS 5.2.1: Problem with xc5200 devices when Makebits -t option is used.
Xilinx Answer #2498 : HW-130: Cannot reconfigure programmer
Xilinx Answer #2499 : M1.3/A1.4: UNIX environment setup for SunOS, Solaris, and HP using C-shell (csh) or KornShell (ksh).
Xilinx Answer #2500 : VERILOG, SYNOPSYS: How to constrain I/O pins in Verilog designs (I/O pin locking)
Xilinx Answer #2501 : M1: NOCLIP, S, NOMERGE, X and KEEP properties
Xilinx Answer #2502 : XC5200: 5206- Incorrect pinouts for any parts with daycode earlier than 9620
Xilinx Answer #2503 : PG475 - 475 pin ceramic PGA physical dimension drawing
Xilinx Answer #2504 : PAR: WARNING:basdp - The SITE "pin-out" specified in the .PCF file was not found in desgin
Xilinx Answer #2505 : Mixed Voltage Systems: Interfacing 3.3 Volt and 5 Volt devices.
Xilinx Answer #2506 : M1.3: Ngdbuild - FATAL_ERROR:baspm:baspmdlm.c:99:1.17 - dll library <x4xxb> does not exist
Xilinx Answer #2508 : VERILOG-XL, Solaris, 97A: "ld.so.1: verilog: fatal: libXm.so.3: can't open file: errno=2"
Xilinx Answer #2509 : Foundation XVHDL: Cannot instantiate the XBlox TRISTATE component without pullups.
Xilinx Answer #2510 : Flow Engine M1: "object disconnected from client" in Flow Engine
Xilinx Answer #2511 : Workview Office: How to label incrementing/decrementing bus signals
Xilinx Answer #2512 : M1.3/M1.4 CPLD: Ngdbuild does not accept some XNF files created by Previous versions of XACT
Xilinx Answer #2513 : M1.2.11 Bitgen - Warning:basbs - Can't find an arc connecting ...
Xilinx Answer #2514 : M1.2.11 Bitgen - The top right bufgp of 4000E parts may not be configured correctly.
Xilinx Answer #2515 : M1.2.11 Bitgen - An incorrect bitstream is generated for all 4005XL designs.
Xilinx Answer #2516 : Exemplar Galileo/Leonardo EDIF files prior to version 4.1.3 are not M1 compatible
Xilinx Answer #2517 : Exemplar: How to instantiate a pullup or pulldown (Galileo and Leonardo)in VHDL
Xilinx Answer #2519 : hw-130 Adapters and supported devices.
Xilinx Answer #2520 : Bitgen 1.2: BUFGP sourced from internal logic may produce incorrect bitfile.
Xilinx Answer #2522 : M1.2.11 Ngdanno - FATAL_ERROR:basna:basnaphysmodel.c:721:1.21 -
Xilinx Answer #2523 : M1.2.11 and M1.3.7 - 4010L-TQ176 Package file is incorrect. Patch available.
Xilinx Answer #2524 : M1.2.11 NGDANNO, 4000XL, Speeds files: "Unable to resolve programmable delay property PROGINTDELAY"
Xilinx Answer #2525 : M1.2/M1.3 Design Manager: Object has disconnected from its client
Xilinx Answer #2526 : What are the differences between C,I, M and B products in a package?
Xilinx Answer #2527 : XC4000E: Clarification about the IOB diagram specified on the data book
Xilinx Answer #2529 : XC4000E/EX/XL: The 4KE devices are not bitstream compatible to their equivalent 4KEX/XL devices
Xilinx Answer #2530 : XC4000EX/XL: The 4000EX devices are bitstream compatible to their equivalent 4000XL devices
Xilinx Answer #2531 : Workview Office Viewdraw: "file is locked" while editing schematic.
Xilinx Answer #2532 : Hardware Debugger: Current design does not have RDBACK block connected.
Xilinx Answer #2533 : NGD2VER M1.2/M1.3/M1.4: ERROR (245) Verilog file parsing failed / Erroron or before token ',' /Escaped names (names prefixed with "\") in Verilog netli sts generated by NGD2VER
Xilinx Answer #2536 : M1.2, Workview Office: EDIFNETI reports unconnected ports reading TIME_SIM.EDN
Xilinx Answer #2537 : Foundation: Can not load/open Foundation after renaming drive, susie.ini
Xilinx Answer #2538 : 9500 - How to invert the global set/reset pin
Xilinx Answer #2539 : M1.3 Installation: Operating System, Memory (RAM), Swap Space and Disk Space Requirements for Targeting Xilinx Devices
Xilinx Answer #2542 : M1: FATAL ERROR BASUT: cname.c:102:1.6 reference count overflow
Xilinx Answer #2544 : bitgen: WARNING:x4kdr - netcheck: no load pins found on signal
Xilinx Answer #2545 : M1.3.7 EPIC - Converting an M1.2.11 hard macro (.nmc file) to M1.3.7 using EPIC.
Xilinx Answer #2546 : V1.4.0 CORE Generator: Viewlogic Synthesis Flow (VHDL only)
Xilinx Answer #2547 : M1.x: license.dat - basic basnb security errors: (-1,73:2), (-5,116:2), (-2,134:2), (-15,10:10061), (-9,57:2), (-8,130:2), (-15,12:146), (-31,34:2) , (-3 4,147), (-15,9:1)
Xilinx Answer #2549 : CONFIGURATION IN EXPRESS MODE IS NOT SUPPORTED IN THE 4000EX/XL FAMILY
Xilinx Answer #2551 : What are the SMD numbers for 1700d family.
Xilinx Answer #2552 : Eztag: Error 203 Syntax error in bit file
Xilinx Answer #2554 : CADENCE/M1: Licensing for CONCEPT2XIL and XIL2CDS-related executables
Xilinx Answer #2556 : M1 Install - Installing M1 software for use with multiple work station platforms.
Xilinx Answer #2558 : M1 VERILOG/VHDL: CLB Flip-flops and latches may have zero setup delay inan SDF netlist for a routed design
Xilinx Answer #2559 : Design Manager M1: fatal relocation error: symbol not found: _ex_keylock
Xilinx Answer #2560 : M1: Board-level schematic simulation methodology for QuickSim
Xilinx Answer #2561 : VERILOG-XL / ES-VERILOG v 5.2.1: Warning! Delay value is negative or too large: set to 0 [Verilog-SVTL] "/products/esv522/verilog4000e"
Xilinx Answer #2565 : M1 DESIGN MANAGER: Wind/U Error (188): Cannot load font set from specification: -adobe-helvetica-medium-r-normal-*-14-*
Xilinx Answer #2566 : Hardware User Guide M1: Incorrectly refers to litefpga design.
Xilinx Answer #2568 : M1 Design Manager - Using a User Rules File to add command line switch to netlist reader.
Xilinx Answer #2569 : M1.2/M1.3/M1.4 PAR (MAP): CLB Pin locking is not supported
Xilinx Answer #2570 : M1 : How to specify SAVESIG ("S"), "KEEP", or "X" constraints on nets using a UCF file.
Xilinx Answer #2571 : XC1700/PROMs: What is the unprogrammed/default state of each byte address in an XC1700 PROM?
Xilinx Answer #2573 : M1, NGD2VER: How to retain design hierarchy in a Verilog simulation netlist generated by NGD2VER
Xilinx Answer #2574 : Foundation XVHDL: How to use READBACK in a VHDL design
Xilinx Answer #2575 : EZtag: "Input passed end of file" message when programming 9572 CPLD
Xilinx Answer #2576 : JTAG/Xchecker Cable: specs for lead connectors and posts
Xilinx Answer #2578 : PAR/FOUNDATION Beta2/Win95: PAR gives "ERROR: FATAL:basut: basutdtime.c:60:1.5 time failure:
Xilinx Answer #2579 : 9500: How to utilize the wired-AND in the UIM
Xilinx Answer #2580 : Epic M1.4,M1.5: Page Fault in Module LIBBASTW.DLL, Illegal operation, Kernel32 error
Xilinx Answer #2581 : Design Architect: Can the generic libraries (gen_lib) be used to in Xilinx schematics?
Xilinx Answer #2583 : PAR 1.4: ERROR: x52ap:111 5200 Design uses to many TBUF's or BUFT's
Xilinx Answer #2584 : Hitop: hi12:[Error]Keyword PIN_FREEZE:servo_cpu_decoder.gyd in the CTL file is invalid.
Xilinx Answer #2585 : XC1700D: Driving inputs when VCC is down should be avoided
Xilinx Answer #2590 : What is the M1 Messaging Update and how do I get it?
Xilinx Answer #2591 : Foundation XVHDL, F1.3/F1.4: Bidirectional pins must be described in top-level entity
Xilinx Answer #2593 : Foundation XVHDL, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers
Xilinx Answer #2594 : Foundation XVHDL, F1.3/F1.4: Do not use 'Macrocell' attribute when instantiating Logiblox
Xilinx Answer #2595 : Foundation XVHDL, F1.3/F1.4: How to instantiate Logiblox components
Xilinx Answer #2596 : Foundation XVHDL, F1.3/F1.4: Hardware key required for XVHDL feature (Programmable C Key)
Xilinx Answer #2599 : Foundation: How to use both XACT6-based and M1-based flows with Foundation
Xilinx Answer #2600 : Foundation F1.3: Where to find old Foundation 6.x libraries
Xilinx Answer #2602 : Foundation F1.3/F1.4: Bus pin names are not visible on Logiblox components
Xilinx Answer #2603 : Foundation F1.3/F1.4, Logiblox: Do not change Logiblox symbol parameters on schematic
Xilinx Answer #2605 : M1.3 dc2ncf: FROM:TO timespec edited incorrectly
Xilinx Answer #2606 : Foundation XVHDL F1.3/F1.4: VHDL compiler synthesizes design twice
Xilinx Answer #2609 : XC4000XL: some devices have a higher VCC pin to GND pin ratio
Xilinx Answer #2610 : Hardware Debugger M1.2: FATAL_ERROR:baspm:baspmdlm.c:174:1.17
Xilinx Answer #2617 : FATAL_ERROR:basnc:basnccomp.c:3221:1.90.14.3 - Cannot find other bel forunconnected pin on bel BEL_CTLR/DB12.RAMBB:D0 of comp CTLR/DB12.
Xilinx Answer #2620 : Foundation Simulator: How can I use a Formula to assign Z to a bus?
Xilinx Answer #2621 : Foundation State Editor: E:#002 Syntax error near "<="
Xilinx Answer #2625 : How to calculate sample rate for SDA filters.
Xilinx Answer #2628 : Prom File Formatter M1.3:Adding 3000, 5200, 4000 devices to daisy chain or prom
Xilinx Answer #2630 : M1 : How to change speed grades (faster or slower) of your placed and routed design? How to recreate simulation and static timing models?
Xilinx Answer #2631 : M1 LOGIBLOX/XBLOX: Naming of RAM Address and Data pins differs in LogiBLOX And X-BLOX
Xilinx Answer #2632 : XC3000A/XC4000: How to implement flip-flops with both asynchronous preset and clear/reset inputs
Xilinx Answer #2633 : PROM FILES: M1 bit mirroring and XACT bit mirroring
Xilinx Answer #2634 : OBSOLETE!!!:3000 family: Bare die, what should the backside (substrate) be connected to?
Xilinx Answer #2636 : M1 - All GUIs (except EPIC) will core dump on HP 9.05 systems at a certain patch level.
Xilinx Answer #2639 : Mentor Graphics Library for XACTstep 5.2.1: DECODE16, DECODE8, and DECODE4 library macros are missing DECODE attribute
Xilinx Answer #2640 : M1.3 General - A device representation problem has been found affecting XL/EX parts.
Xilinx Answer #2641 : M1.2 MAP: Problems with map3_nt.zip patch when installed in MYXILINX directory on Windows NT and Win95 systems: FATAL_ERROR:baspm:baspmdlm.c fail to ope n libx4kma.dll
Xilinx Answer #2642 : M1.2/M1.3 Design Manager: Where is preference and project information stored?
Xilinx Answer #2644 : M1 CONCEPT/CONCEPT2XIL: generating a symbol body for a non-schematic block, using a Verilog .v file as input
Xilinx Answer #2645 : Configuration/Reprogram fails: INIT goes low timely unrelated to frames
Xilinx Answer #2646 : Workview Office: VSM Error 222. Could not find wir file XC9000 AND2B1.1
Xilinx Answer #2647 : MAP, PAR, PPR: Constraining signals to unbonded pads in M1 and XACT (naming convention is different)
Xilinx Answer #2648 : Can I run M1 and XACTstep 6.0 software on the same machine?
Xilinx Answer #2650 : VERILOG-XL: How to specify the SDF file to the Verilog-XL simulator as acommand line option
Xilinx Answer #2653 : Power estimation for the 9500 family devices
Xilinx Answer #2654 : M1.3 CPLD: Synopsys set_pad_type -slewrate command causes disconnected OBUF in CPLD.
Xilinx Answer #2655 : M1 CPLD: Synopsys SCAN tutorial test bench does not initialize registers.
Xilinx Answer #2656 : M1.3.7 - XC4000XL package file patch adds new packages.
Xilinx Answer #2657 : Synopsys FPGA/Design Compiler: Error: The entity 'add_sub_ub' depends onthe package 'std_logic_arith' which has been analyzed more recently.
Xilinx Answer #2658 : PROMS: Can you use a 1736A as a master to program a 1736D part?
Xilinx Answer #2660 : M1.3/M1.4 CPLD: Exemplar netlists use IOBUFE which is not expanded by 9klibrary.
Xilinx Answer #2661 : M1.3 CPLD: Synopsys I/O ports cause xr5100 and nd201 warnings and pin name changes.
Xilinx Answer #2662 : XABEL6, Foundation F1.3/F1.4: OLE server errors when ABEL from other vendor installed (registry).
Xilinx Answer #2663 : XABEL6, Foundation F1.3/F1.4: EDIF netlists from XABEL in M1/F1 are encrypted.
Xilinx Answer #2666 : MAP: The meaning of the Map packing strategy options
Xilinx Answer #2669 : M1 and XACT: How to determine device utilization of a design without placement and routing
Xilinx Answer #2672 : M1.3.7 Map - Patch file contains 36 map, par, ngdbuild and xnf2ngd fixesas of 12-8-97.
Xilinx Answer #2673 : M1.3/M1.4: TIMING ANALYZER, XILINX DESIGN MANAGER, LBGUI, PROMFMTR, on Solaris: core dumps may be due to 97A Verilog XNLSPATH settings
Xilinx Answer #2674 : CPLD chipviewer: error msg: A required .DLL file, MSVCRT.DLL, was not found
Xilinx Answer #2675 : ChipViewer: 9500 floorPlanner tool that allows user to assign MCs and FBs
Xilinx Answer #2676 : TERADYNE Z1800 ATE SUPPORT FOR XC9500
Xilinx Answer #2678 : M1 NGDBUILD: ERROR:basnu - logical net "signal" has multiple drivers.
Xilinx Answer #2680 : M1.3/M1.4: MAP -os and -oe optimization options: When to use them (XABEL, Metamor designs), why results may not improve
Xilinx Answer #2683 : PROMGEN M1.3: M1 vs XACT 6.0.x bit swapping in HEX files.
Xilinx Answer #2684 : VERILOG, NGD2VER: How to initialize RAM in Verilog functional and timing simulation
Xilinx Answer #2686 : M1, ViewSynthesis: SpeedWave may have difficulty analyzing large models
Xilinx Answer #2687 : M1, ViewSynthesis: Analyzing Simprims and Unified libraries with SpeedWave
Xilinx Answer #2688 : M1, ViewSynthesis: Bus Naming and Post-place-and-route Bus Reconstruction
Xilinx Answer #2689 : ViewSynthesis: Flow for black box instantiation
Xilinx Answer #2690 : M1.3.7 Ngdbuild - Patch available for problem with Synopsys interface.
Xilinx Answer #2691 : M1.3.7 Timing - XC4000E speed file patch available that correct three problems
Xilinx Answer #2692 : Error: unable to open symbol template file. Logiblox: /sim/datareg0.1
Xilinx Answer #2697 : Bitgen M1.3.7: Device correctly configures but some I/O's do not oscillate.
Xilinx Answer #2699 : Workview Office: How to install Sentinel driver for Windows NT 4.0 (error 8037)
Xilinx Answer #2703 : How to create simulation files using M1 FPGA Implementation Software
Xilinx Answer #2704 : M1 CPLD: How does the CPLD Auto Device Selection Work
Xilinx Answer #2706 : CPLD DATA BOOK: Jan. 97 edition: The pinout for the 95144 PQ160 package is incorrect
Xilinx Answer #2707 : Is there a generic BSDL file that can used to bypass non-9500 devices with EZTAG?
Xilinx Answer #2709 : DTEXT: Error in file Dynatext.ini. full.lic cannot be located
Xilinx Answer #2710 : How to find the amount of on chip resources used by M1 Implementation software.
Xilinx Answer #2711 : XC4000XL: he pin C8 of xc4044XL BG352 can't be mapped by m1.3.7,
Xilinx Answer #2712 : How to analyze the resources a module or partially completed design consumes?
Xilinx Answer #2713 : SYNPLIFY: How to instantiate a pre-optimized netlist (XNF, EDIF, NGO) file in HDL (Verilog/VHDL)?
Xilinx Answer #2714 : M1.3.7-pc: map FATAL_ERROR:basnc:basncsignal.c:262:1.61 - could not finda bel for a signal on pin G2
Xilinx Answer #2715 : CADENCE COMPOSER, 97A: Where to find a sample cds.lib setup for the FPGA Designer for Composer flow in 97A / "penTable" error
Xilinx Answer #2716 : M1.3/M1.4 CPLD: How to create timing simulation netlist in the XNF format
Xilinx Answer #2717 : M1 CPLD: How to control Power Consumption in a CPLD
Xilinx Answer #2719 : M1 CPLD: How to lock the pins on a CPLD (7300/9500)?
Xilinx Answer #2720 : PAR M1.3: baspl:291,292 - pullup could not be placed
Xilinx Answer #2721 : Workview Office 7.31: ViewDraw not installed; license-based installer does not work
Xilinx Answer #2722 : Foundation F1.3/F1.4, XVHDL: I/O flip-flops not inferred by VHDL synthesizer
Xilinx Answer #2723 : FPGA Express: Program does not start after double-clicking on icon
Xilinx Answer #2724 : M1.3: FATAL_ERROR:baspm.baspmdlm.c:99:1.17 - dll library <mtrne> does not exist.
Xilinx Answer #2726 : XBLOX: ACCUM - effects of LOAD on C_OUT and OVFL
Xilinx Answer #2727 : M1.3.7 Hitop error: Hitop caused an invalid page fault in module HITOP.EXE at 0137-00436952
Xilinx Answer #2728 : M1 TRCE: How to analyze overall timing constraint performance
Xilinx Answer #2729 : M1 CPLD: How to control Logic Optimization in a CPLD
Xilinx Answer #2730 : How to connect unused 9500 outputs to known levels
Xilinx Answer #2731 : M1.3 CPLD: taengine - Assertion failed: !i->RetOutput(iot,ZeroIfNew)
Xilinx Answer #2732 : M1 CPLD: How to control Timing in a CPLD
Xilinx Answer #2734 : FPGA Express/M1.3: HDL Simulation of HDL only designs synthesized with FPGA Express
Xilinx Answer #2735 : M1.3/FPGA Express: M1 Constraints, LogiBLOX, and modules within FPGA Express
Xilinx Answer #2736 : Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc.
Xilinx Answer #2737 : Foundation F1.3/F1.4, XVHDL: How to simulate VHDL designs with instantiated XNF files
Xilinx Answer #2738 : M1.3/FPGA Express v1.2: Modular (Black-Box) Instantiation in Express
Xilinx Answer #2739 : XCHECKER: What should the RST pin be connected to in XC4000 or XC5200 devices?
Xilinx Answer #2740 : M1 TRCE: How to analyze (the longest) nets/paths in timing constraints
Xilinx Answer #2741 : M1.3 4kex Timing - Long delays are calculated for TBUFs driving long lines with Pullups.
Xilinx Answer #2742 : How to analyze the delays for a specific path using M1 software?
Xilinx Answer #2744 : Can the Copper Heatsink on the HQ packages be grounded?
Xilinx Answer #2745 : Packages: Some BG256 packages have the (4 x 4) Ground ball matrix.
Xilinx Answer #2746 : Foundation XVHDL: Synthesis error "Wrong number of fields bus on line #__ in .xas file"
Xilinx Answer #2747 : Foundation Schematic: Can I add my own company logo to a Foundation schematic onto the border or table?
Xilinx Answer #2749 : M1 ngdbuild error: ngdbuild.exe -entrypoint not found
Xilinx Answer #2750 : VERILOG-XL: SDF Annotator gives "SDFA Error: Could not find path IN to OUT"
Xilinx Answer #2752 : M1.3.7 - CPLD patch available for several issues
Xilinx Answer #2753 : M1.3 MAP: On a bidirectional I/O, the INFF and pad are also trimmed eventhough only the OUTFF is dangling
Xilinx Answer #2754 : Design Manager M1.3/M1.4/M1.5: How to open multiple instances of the Design Manager
Xilinx Answer #2755 : Hardware Debugger 1.4: ld.so.1: hwdebugr: fatal: libbascd.so: can't openfile: errno=2
Xilinx Answer #2756 : Foundation XVHDL: How to keep internal signal name so it appears in simulator
Xilinx Answer #2757 : M1.3 JTAG Programmer: Can not print on NT 4.0 parallel port printer after installing the software
Xilinx Answer #2758 : M1.3/M1.4 MAP: unclear messages about FDCEs being "covered by optimization" in the MAP .mrp file when the -os option is specified
Xilinx Answer #2759 : Foundation F1.3/F1.4, Logiblox: Invalid Vendor 'fndtn' on command line. Unable to continue execution
Xilinx Answer #2760 : Are 4000XL/XV I/O Thresholds Programable to TTL or CMOS Compatibility?
Xilinx Answer #2763 : ngdbuild m1.3: ERROR:basnb:48 - Cannot find or build NGO from "filename.edn"
Xilinx Answer #2765 : Considerations for choosing external PULLDOWN resistor values for FPGA pins.
Xilinx Answer #2766 : A1.5/1.4: CONCEPT2XIL: How to obtain the M1 Concept netlister
Xilinx Answer #2770 : M1, CONCEPT2XIL, HDL DIRECT, CADENCE 97A: Problem with CONFIG, PART, TIMESPEC AND TNM properties not being translated to the EDIF file.
Xilinx Answer #2772 : FATAL_ERROR:basnc:basncsignal.c:262:1.61 mapping with -k switch
Xilinx Answer #2773 : CONCEPT2XIL/SIR2EDF: Error! Cannot open property file
Xilinx Answer #2774 : Installing M1.3 on a Solaris 2.4 machine may not complete sucessfully
Xilinx Answer #2776 : Foundation F1.3/F1.4 XABEL: How to generate .PLD (Plusasm) file from XABEL
Xilinx Answer #2777 : PAR/EPIC M1.5: Both say that BEL doesn't exist in the NCD, but it does.
Xilinx Answer #2778 : XC3000/XC4000/XC5200: impedance IOBs pullups for different devices
Xilinx Answer #2780 : XC9500: Logic erroneously trimmed away when using HDL macros in 9k schematic design
Xilinx Answer #2781 : M1 NGDBUILD: ERROR:bascp:69 and/or WARNING:basts:19 on Mentor TIMEGRPs
Xilinx Answer #2782 : M1.3.7, M1.4.12 LOGIBLOX: rloc_orgin on Logiblox ADD/SUBis ignored by place and route tool.
Xilinx Answer #2783 : M1.3/M1.4 PAR: The signal "GLOBAL_LOGIC0" is not completely routed--messages about unrouted nets that are not in the input design
Xilinx Answer #2784 : How can the 4000XL/XV device talk to a 5V CMOS level device?
Xilinx Answer #2786 : M1.3 Install (Win95 CD): "Windows cannot find file setup.exe" or "Setup is unable to locate script file d:\setup.ins", error 107
Xilinx Answer #2787 : M1.3.7 - Timing Analyzer - Number of analyzed paths changes with report paths not covered filter
Xilinx Answer #2788 : M1.3.7 Speed Files - New speed files are available for M1.3.7 XC4000XL and XC4000EX.
Xilinx Answer #2789 : M1.3.7 Timing Analyzer - "Report Paths not Covered by Timing Constraints" feature does not work.
Xilinx Answer #2790 : M1.3.7 TRCE - Doing a TIG in the UCF file on a signal which is the output of a tristate buffer does not work.
Xilinx Answer #2792 : Model Tech: Error can not read output when compiling backannotated 9500 VHDL
Xilinx Answer #2794 : M1: Taengine -> abnormal program termination
Xilinx Answer #2795 : M1 License :FLEXlm error message: Invalid returned data from license server(-12,122)
Xilinx Answer #2796 : M1.3.7 Lab Install: invoke hwdebugr returns "ld.so.1 fatal: libbasfc.so can not open file errno=2"
Xilinx Answer #2798 : M1.3/1.4 LogiBLOX: Bus order reversed on LogiBlox mux macros symbols
Xilinx Answer #2799 : EDIF2NGD: Application Error EDIF2NGD caused an invalid page fault in module EDIF2NGD.exe
Xilinx Answer #2800 : XC3000: XNFPREP 5.2.1: Segmentation Fault(core dumped)
Xilinx Answer #2801 : M1.3 GUIs: "Warning: Can't load Codeset file 'c', using internal fallback" while loading
Xilinx Answer #2802 : How to obtain pfs code for HP for mounting CD-ROMS with pfs_mount?
Xilinx Answer #2803 : M1.3.7 Hardware Debugger fails during Readback/Verify on PC.
Xilinx Answer #2805 : SYNPLIFY: How to instantiate BSCAN in HDL (Verilog/VHDL)?
Xilinx Answer #2806 : Foundation F1.3: Lmacs cannot find <project_name>.id file -- SC: LM_Put_Symbol - error #702
Xilinx Answer #2807 : Foundation F1.3: Lmacs: the record has a key field containing a duplicate key value -- Sc: LM_Put_Symbol - error #5
Xilinx Answer #2808 : M1.3.7 Map - Inverter is incorrectly pushed into a closed FMAP.
Xilinx Answer #2809 : M1.3.7 Map - Wrong LUT is connected to FF resulting in corrupt logic.
Xilinx Answer #2810 : M1.3.7 Map - FATAL_ERROR:baste:bastetspec.c:946:1.64 - No NC_SIGNAL for TECHMAP_SIG on BEL...
Xilinx Answer #2811 : M1.3.7 Map - Map fails with seg fault on a particular design
Xilinx Answer #2812 : Map M1.3.7 - Map fails with page fault when run from Design Manager for a paticular design
Xilinx Answer #2813 : M1.3.7 Map - Map incorrectly complains about .FFX RLOC property in coregen multiplier
Xilinx Answer #2814 : M1.3.7 Map - FATAL_ERROR:x4kma:x4kmamerge.c:2371:1.120 Too many signals to move...
Xilinx Answer #2815 : M1.3.7 Map - Map incorrectly configures a CIN net.
Xilinx Answer #2816 : M1.3.7 Map - Map incorrectly optimizes FDC to VCC.
Xilinx Answer #2817 : M1.3 Map - Map incorrectly handles CLB latches from Logiblox
Xilinx Answer #2818 : M1.3.7 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2456:1.96 - Illegal call to swap.
Xilinx Answer #2819 : M1.3.7 Map - Map doesn't preserve the logic for Logiblox 4-bit binary down counter.
Xilinx Answer #2820 : M1.3.7 - Map swaps two bits of a bus corrupting logic
Xilinx Answer #2821 : M1.3.7 Map - Guided map operation fails with core dump
Xilinx Answer #2822 : M1.3.7 Map - FATAL_ERROR:basnc:basnccomp.c:3221:1.90.14.3 - Cannot find other bel...
Xilinx Answer #2823 : M1.3.7 Ngdbuild - Ngdbuild core dumps when trying to load a hard macro (.nmc)
Xilinx Answer #2824 : M1.3.7 Map - Map seg faults on a particular design
Xilinx Answer #2825 : M1.3.7 Map - Map doesn't pass a TPTHRU consraint to .pcf file to relax constraint
Xilinx Answer #2826 : M1.3.7 Map - Map writes bad data to .ngm file corupting simulation results
Xilinx Answer #2827 : M1.3.7 Map - Map incorrectly trims an INFF that is combined with unused OFDT
Xilinx Answer #2828 : M1.3.7 TRCE - Timing constraint does not relax period constraint
Xilinx Answer #2830 : M1.3.7 Timing Analyzer - Patch available for four issues
Xilinx Answer #2831 : SYNPLIFY: How to force a IOB NODELAY latch or flip-flop in HDL (Verilog/VHDL)?
Xilinx Answer #2832 : M1.3: Warning: basdp: 52 / basdp: 48
Xilinx Answer #2834 : XABEL, Foundation F1.3: Internal Error 0001: assert event at line 274 in file Z:\fit\blif2net\TSOINTER.CXX
Xilinx Answer #2837 : COREGEN: FFT and DFT Data Sheets
Xilinx Answer #2839 : Dynatext: How to contact Dynatext technical support?
Xilinx Answer #2842 : Workview Office: License platform restriction errors (1055, 8031, 8052)
Xilinx Answer #2843 : FPGA Express v1.2: Script to convert EXT records to SIG records for module generation
Xilinx Answer #2844 : M1.3 and M1.4: Flexlm - all the files that is associated with flexlm 5.0
Xilinx Answer #2845 : Foundation F1.3: Quickstart Guide and Release Notes available on FTP/Web site in Acrobat Format
Xilinx Answer #2847 : M1 QuickHDL: VHDL/VITAL RAMs do not simulate properly or respond to stimuli on HP-UX
Xilinx Answer #2849 : Timing Analyzer: How to save path filters for automatic processing?
Xilinx Answer #2850 : M1.3/M1.4: Instructions on how to install and run the license manager standalone on win95/winNT4.0
Xilinx Answer #2851 : M1.4: Instructions on how to install and run the license manager standalone on sun/solaris/hp workstations
Xilinx Answer #2855 : Design Manager M1: Segmentation Fault / Bus Error (core dump) when invoked
Xilinx Answer #2858 : XC5200: New Speed files are now available on the web
Xilinx Answer #2863 : FATAL_ERROR:basbd:basbdbool.c:393:1.5 - Signal unassigned to variable encountered. Process will terminate. Please call Xilinx support.
Xilinx Answer #2864 : M1.3 LogiBLOX and NGDBUILD/MAP: Warning/Error:basnu - logical block "<instance_name>" of type "<logiblox_module>" is unexpanded
Xilinx Answer #2865 : FPGA/Design Compiler: How to instantiate LogiBLOX in the Synopsys VHDL or Verilog Flow
Xilinx Answer #2866 : GSR and GTS pads don't work in SXNF netlists from Synopsys for CPLDs.
Xilinx Answer #2870 : M1 NGDBUILD: ERRORS: basnu - logical net...has multiple drivers, illegalconnection, no legal driver, no driver...
Xilinx Answer #2871 : Foundation F1.x, XABEL: Error:hi301 - cannot fit the design into any ofthe specified devices
Xilinx Answer #2872 : WARNING:baspl:291 - The TBUF component "XXX" could not be placed. (How to count the number of TBUF driven nets in a design.)
Xilinx Answer #2873 : Foundation simulator does not properly simulate the CK_DIV or OSC52 symbols
Xilinx Answer #2874 : XACTstep wir2xnf 5.2.1 may fail with WIR files created by Powerview 6.1
Xilinx Answer #2875 : XC9500: Maximum Icc by package type
Xilinx Answer #2876 : XC9500: What type of drivers does the 9500 output buffers use?
Xilinx Answer #2877 : Viewsim/Viewtrace: vector is specified in command file and wfm statementbut shows up as XXXX in Viewtrace
Xilinx Answer #2879 : M1.3: Windows95 Install: Installing software to run from a network drive
Xilinx Answer #2880 : WorkView Office: Viewdraw error vipc -e -1347 unable to connect to vnsd and vipc init()
Xilinx Answer #2881 : M1.3/M1.4 JTAG Programmer: Possible cause of Boundary Scan Chain Integrity error
Xilinx Answer #2883 : Viewlogic Pre-Unified Libraries (hm4000, mx3000, mx4000) available on the WEB/FTP site
Xilinx Answer #2884 : M1.3: Map removes IBUF along with unused OBUFT in a bidirectional I/O
Xilinx Answer #2886 : M1 Design Architect: LogiBLOX fails with "newer symbol database version has been encountered"
Xilinx Answer #2887 : Design Manager M1.3/M1.4/M1.5: FPGA Multi-Pass Place and Route (MPPR) greyed out
Xilinx Answer #2888 : FPGA Express 1.2, 2.0: XC4000 Global Buffer constraints: ERROR:baste:263
Xilinx Answer #2889 : PAR: Routing pwr/gnd nets takes an extremely long time to complete
Xilinx Answer #2890 : Foundation F1.3 Schematic: Symbols are removed or disappear after addingsymbols. PM message symbol not added, not enough memory to complete this operati on
Xilinx Answer #2891 : PAR: Error: rpc server is unavailable
Xilinx Answer #2892 : M1.4: TIMESPEC paths originating from .NMC macros (physical macros) do not get written by Map to the .PCF file
Xilinx Answer #2893 : M1.4 Map: DROP_SPEC property takes priority over other TIMESPECs regardless of where it is specified in the flow
Xilinx Answer #2894 : M1.2/M1.3/M1.4: MAP "ERROR: x4kma:312 - Unable to obey design constraints" RAM16x1D and two flipflops
Xilinx Answer #2895 : Foundation F1.3/F1.4 Schematic: How to lock down I/O pins for IPAD4/8/16, OPAD4/8/16, IOPAD/4/8/16
Xilinx Answer #2896 : M1.4: TRCE reports large delay on net driven by TBUFs with PULLUP
Xilinx Answer #2897 : The detail timing report contains some signals with a .Q extension.
Xilinx Answer #2898 : How to ignore/remove LOC constraints on PADS?
Xilinx Answer #2899 : M1: QuickSim functional simulation of a Mentor schematic with instantiated XNF
Xilinx Answer #2900 : M1.4: FATAL_ERROR:basut:basutarray.c Element out of range
Xilinx Answer #2901 : Foundation F1.3 Schematic will not let me add anymore components. symbolnot added, not enough memory to complete this operation
Xilinx Answer #2906 : M1.4 CPLD: How to reserve a pin or a macrocell for future use?
Xilinx Answer #2908 : ** DUPLICATE of 2249 ** M1.4 MAP: WARNING x4kma - signal on pin G4 of CY4 symbol is not required by carry mode INC-F-CI
Xilinx Answer #2909 : M1.3/M1.4: No option in Design Manager or NGDBUILD to ignore a .ucf file
Xilinx Answer #2910 : M1.4 CPLD: Some designs which used to fit in M1.3 failed with M1.4.
Xilinx Answer #2911 : M1.3/M1.4 Design Manager/NGDBUILD: DC2NCF is not invoked automatically for .sedif and .sxnf files
Xilinx Answer #2912 : M1.3/M1.4 NGDBUILD: ERROR:basxn:68 - The XNF file does not contain a valid PART
Xilinx Answer #2913 : M1.4 CPLD: The OFFSET timing constraint does not force the fitter to useglobal clocks
Xilinx Answer #2914 : ** DUPLICATE of 2337 ** M1.2/M1.3/M1.4 MAP: Map complains about incompatible site types when expanding wildcard constraints--ERROR:x4kma - IBUF symbol `$ 1I89' is unable to combine with IO RESET
Xilinx Answer #2915 : M1.4 MAP/PAR: PAR ERROR:baspr - SSLex0105e: Invalid token, Line 13, Offset 38, ,
Xilinx Answer #2916 : M1.5: EPIC - ERROR: baspr - A parsing error has occured at line 6, token";"
Xilinx Answer #2917 : M1.5: EPIC - scripts->playback, ERROR:basep - Site "CLB_R1C8" is occupied.
Xilinx Answer #2921 : MAP: BUFG net attached to a BUF with an X attribute gets distributed using local routing instead of being driven directly by a BUFG
Xilinx Answer #2922 : Workview Office 7.3x: The symbol wizard in viewdraw gives a Dr. Watson vsec: Error 8002(vseccode.vmb)
Xilinx Answer #2923 : Powerview 6.0, Edif Netlist Reader V2.3: BNF Parser Error Internal stackoverflow
Xilinx Answer #2924 : M1.3/M1.4: Solaris, Powerview/logiblox: lbgui process is left running after exiting ViewDraw
Xilinx Answer #2926 : ViewSim and M1.2: Loading func_sim.xmm gives error that none of the RAM instances are found.
Xilinx Answer #2930 : MAP M1.3/M1.4: "MAP = PUO" is ignored on HMAPs (HMAPs are always closed)
Xilinx Answer #2931 : M1.4: NGD2VER writes out the GR pin as a port in XC3000A netlists
Xilinx Answer #2932 : What is an IBIS model, (as opposed to a SPICE model)?
Xilinx Answer #2933 : NGDBUILD: ERROR:basnb - SECURITY ERROR -- Unable to lock license for ngdbuild: No such feature exists (-5,116:2) No such file or directory.
Xilinx Answer #2934 : M1.3/M1.4 : NGDBUILD while running xnf2ngd gives error: basxn:51 - Line number <actual line number> : Attribute value exceeds maximum length! - XNF2NGD c ould not parse the input file.
Xilinx Answer #2935 : Converting pre-Unified library schematic designs to Unified libraries
Xilinx Answer #2937 : Foundation F1.3/F1.4, XABEL 6: XABEL cannot be run from the network
Xilinx Answer #2938 : A1.4/A1.5: logical block reported as 'unexpanded' by ngdbuild
Xilinx Answer #2939 : EZTAG: Basic debugging techniques for downloading design
Xilinx Answer #2941 : FUNCNET/FUNCNETX, TIMENET/TIMENETX: What is the difference?
Xilinx Answer #2942 : Design Manager M1.4/M1.5: How do you move projects?
Xilinx Answer #2943 : A1.5/1.4: Cadence XIL2CDS availability / how to obtain XIL2CDS
Xilinx Answer #2944 : XC9500: Can I Hot Sync my XC9500 device
Xilinx Answer #2945 : M1 TRCE: How does TRCE calculate worst case timing values if it is unaware of the temperature grade for a part?
Xilinx Answer #2946 : M1.4: XC4000X schematic libraries must be used to target XC4000EX, XC4000XL, or XC4000XV designs
Xilinx Answer #2947 : VIEWLOGIC: Converting pre-Unified library schematic designs to Unified libraries
Xilinx Answer #2948 : M1.3 CPLD: Fitter patch causing timespecs to dissappear
Xilinx Answer #2951 : XABEL/Foundation F1.3/Alliance: Using F1.3's XABEL with Alliance packages (mentor, viewlogic)
Xilinx Answer #2952 : XC9500: Can I use an external pullup to increase the output drive strength?
Xilinx Answer #2953 : BOUNDARY SCAN/JTAG: Latched instruction in the Test-Logic-Reset state ofXC4K/XC5K/XC9K parts
Xilinx Answer #2954 : Foundation F1.3/F1.4 XVHDL : I/O flip-flops (IFDX1) instantiation
Xilinx Answer #2956 : M1.4 CPLD: Interactive Timing Analyzer gives unhelpful messages when invoked on a 7K design
Xilinx Answer #2958 : Foundation F1.3/F1.4, XABEL: DIOEDA errors involving abl2edif
Xilinx Answer #2959 : Foundation Project Manager: Hierarchical, Error xr57 - Input signal drives more than one input buffer.
Xilinx Answer #2960 : M1.3 JTAG Programmer: Communications with the cable could not be established
Xilinx Answer #2961 : XABEL should support Xilinx property 'LOC=FBnn'
Xilinx Answer #2962 : Foundation F1.3/F1.4 XVHDL: Using Input/Output latches
Xilinx Answer #2963 : M1.5 TRCE: How to find the signals not covered by TIMESPECs?
Xilinx Answer #2964 : m1.3 ngdbuild. ERROR basut - Problem parsing '_'.
Xilinx Answer #2965 : Foundation F1.3, XABEL: Online Help shows incorrect syntax for XABEL LOC = FBnn property.
Xilinx Answer #2966 : XC2000/XC3000/XC4000/XC5200: Tying two output pins to enhance current drive
Xilinx Answer #2968 : FPGA Express 1.2, 2.0: Where the IEEE and SYNOPSYS VHDL Libraries are located
Xilinx Answer #2972 : Design Manager M1.4: Place & Route Effort Level in Place & Route TAB remains unchanged
Xilinx Answer #2975 : XC95108: Are Programmable grounds supported?
Xilinx Answer #2977 : M1.3: How to include -ul option in NGD2VER within Design Manager
Xilinx Answer #2979 : EPIC: How to add a probe or route out a signal
Xilinx Answer #2983 : M1.4 Timing Analyzer: Failed to open document (Win95)
Xilinx Answer #2984 : Foundation F1.3, XC5200: Incorrect polarity of pins in AND2B1, etc components
Xilinx Answer #2985 : Ngdbuild - WARNING:basnu - logical block "SIM/U150/U1" of type "DFF" is unexpanded.
Xilinx Answer #2988 : Foundation F1.3/F1.4 XABEL: XEPLD/Plusasm 'Partition' property not supported
Xilinx Answer #2989 : Foundation F1.3, XVHDL 3.0.2: Error L20/CO: The Xilinx 4ke library doesnot contain a latch (#480 Constraint)
Xilinx Answer #2991 : M1: Synopsys XBLOX libraries have been renamed
Xilinx Answer #2992 : Are there counter modules in the xdw (xblox designware) libraries?
Xilinx Answer #2993 : M1.3 MAP: OPTX error -- ERROR: x4kdr: 7 (Foundation F1.3 specific)
Xilinx Answer #2994 : M1.3.7 EPIC crashes on xc4062xl when trying to add opads.
Xilinx Answer #2995 : Workview Office 7.31: Cannot open Project Manager.
Xilinx Answer #2996 : dc2ncf: How do you use the set_max_delay as a substitute for the set_multicycle_path command?
Xilinx Answer #2997 : XC9500: Corrected model from LMG now available
Xilinx Answer #2998 : M1.3 Ngdbuild of Pre-Unified Lib netlist - WARNING:basnu - logical block"XXX" of type "DFF" is unexpanded.
Xilinx Answer #3000 : XC9500: Why do the XC9500 libraries have pull-up elements?
Xilinx Answer #3001 : Foundation F1.3, XVHDL: XVHDL (Metamor) v3.0.3 Upgrade available on WebAnswers page
Xilinx Answer #3002 : Foundation F1.3/F1.4 Project Manager: Very slow when launching under Win95
Xilinx Answer #3003 : Synopsys FPGA Compiler: Error code "VE-0" from analyze command in dc_shell
Xilinx Answer #3006 : M1.3/M1.4 CPLD: How to calculate the timing accross a latch in a 9K device
Xilinx Answer #3007 : XABEL, Foundation F1.3/F1.4: BLIFOPT step runs indefinitely during ABL2EDIF
Xilinx Answer #3008 : CPLD: CPLD command-line does not support reading PART attribute from netlist.
Xilinx Answer #3009 : dsgnmgr: Core dumps using Exceed/W
Xilinx Answer #3010 : FPGA Express: Instantiating an EDIF from a Foundation Schematic into a top-level FPGA Express Verilog or VHDL Design
Xilinx Answer #3011 : M1.5 NGDBUILD: UCF constraint on element with special char. gives "ERROR:baspr - SSLex0105e: Invalid token"
Xilinx Answer #3012 : NGDANNO 1.3: Mode pin MD1 always outputs "z" in timing simulation
Xilinx Answer #3013 : FPGA Express 1.2/Foundation 1.3: Creating HDL Macros with FPGA Express 1.2 for Placement on a Foundation 1.3 Top-Level Schematic
Xilinx Answer #3014 : M1.5 TRCE: "HIGH" or "LOW" keyword for PERIOD may not work as expected with OFFSET
Xilinx Answer #3015 : M1.5: PERIOD placed on net between PAD and IBUF not analyzed
Xilinx Answer #3016 : M1.5: TNM placed on net between PAD and BUFG/IBUF not forward traced
Xilinx Answer #3017 : Configuration: Dynamic Re-ordering of Daisy-Chain configurations.
Xilinx Answer #3018 : FPGA Express v1.2/Foundation 1.3: Simulating with FPGA Express v1.2 HDL and F1.3 Logic Simulator
Xilinx Answer #3019 : What is Dr. Watson?
Xilinx Answer #3020 : Foundation F1.3/F1.4, XABEL: Supported 'Xilinx Property' for CPLDs withXABEL6
Xilinx Answer #3021 : Foundation F1.3/F1.4 XABEL: XEPLD/Plusasm Properties not supported withEDIF-based Abel flow
Xilinx Answer #3022 : M1.3 JTAG Programmer: How to read 3rd party BSDL files
Xilinx Answer #3023 : Foundation F1.3/F1.4, State Editor: How to modify encoding scheme for State Machines (ie, one-hot)?
Xilinx Answer #3024 : DATA BOOK: Timing data applied to Commercial, Industrial, and Military devices
Xilinx Answer #3026 : 9500: Usage of internal pullup in IOB
Xilinx Answer #3027 : XABEL6, Foundation F1.3/F1.4, NGDBUILD: Warning- logical net VCC_net (or GND_net) has no load
Xilinx Answer #3030 : Foundation XVHDL, XC9500: How to set an output to high impedance (Hi-Z)
Xilinx Answer #3031 : COREGEN, WORKVIEW OFFICE, M1: Implemented module has much higher CLB counts than specified in the datasheet
Xilinx Answer #3032 : NGDBUILD (F1.3) caused an invalid page fault in module LMGR325A.DLL
Xilinx Answer #3034 : Foundation Simulator: How to print a specific range of the simulation waveform
Xilinx Answer #3036 : M1.3 Map - Map will not push buffer (or logic optimized to buffer) forward into closed FMAP (MAP=PUC or PLC)
Xilinx Answer #3037 : M1 PLD_EDIF2SIM/XNF2SIM/EDIF2TIM: Error: Could Not find the External part "$SIMPRIMS/___"
Xilinx Answer #3040 : V1.4.0 COREGEN: sample COREGen .COE coefficient files.
Xilinx Answer #3041 : Foundation F1.3, F1.4: How to add Generic Project Type for Board Level Simulation
Xilinx Answer #3043 : Foundation F1.3, Logiblox: TNM attributes on Logiblox in schematic do not pass to EDIF file
Xilinx Answer #3046 : M1: QuickSim functional simulation of a Mentor schematic with instantiated EDIF (without XNF)
Xilinx Answer #3048 : Foundation F1.3/F1.4, Design Manager, XABEL: DM doesn't read PLD (Plusasm) or EDN file if flow is changed
Xilinx Answer #3050 : M1.3/M1.4: Verilog and VHDL SIMPRIM models for X_RAMD16 have only one output port
Xilinx Answer #3051 : Translating lattice LDF file to Xilinx XABEL format
Xilinx Answer #3052 : Hardware Debugger M1_3.7: XCHECKER Self Check Fails in Windows 95 & NT...
Xilinx Answer #3055 : M1.3/M1.4 CPLD: Fitter incorrectly trimming pin from macro which is driving multiple outputs
Xilinx Answer #3059 : LogiBLOX, ngd2edif: ERROR:basut - Unexpected argument[7] "module_name" found.
Xilinx Answer #3060 : LogiBLOX, ngd2edif: ERROR:basxb:41 - Cannot open temporary output file "C:/TEMP /module_name.ngd"
Xilinx Answer #3061 : Hardware Debugger M1_3.7: Stand alone download and readback software.
Xilinx Answer #3062 : M1.3/1.4 - Fatal Error:basnp:basnpdevice.c:533.1.17 bad nph file (from map and other applications)
Xilinx Answer #3064 : M1.3 Translate: OPTX error:x4kdr: 7 ---netcheck: Macros instantiated inABEL.
Xilinx Answer #3066 : 96 DATA BOOK: XC3064A/L, XC3164A/L, XC3O90A/L, XC3190A/L I/O pins misprint
Xilinx Answer #3067 : Migrating XBLOX designs to M1: XBLOX2M1 archive now exists on ftp site
Xilinx Answer #3068 : Hardware Debugger M1.4: Readback Capture displays wrong data.
Xilinx Answer #3070 : Modifying path of the dynatext.ini file
Xilinx Answer #3074 : A1.5/1.4: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic
Xilinx Answer #3076 : Foundation F1.3/F1.4, XC9500, XVHDL: Macro pass-through signals trimmed away or tied to VCC/GND.
Xilinx Answer #3077 : XC4000XL/XLT: Differences between the 4000XL and 4000XLT
Xilinx Answer #3078 : M1.4,Powerview 6: vanlibcreate gives linker error compiling Logiblox VHDL library
Xilinx Answer #3079 : M1.3/M1.4: ViewDraw Check Project: "Could not load schematic sheet" error for LogiBLOX or COREGen module
Xilinx Answer #3080 : M1.3/M1.4: Viewlogic board level simulation methodology
Xilinx Answer #3081 : M1: Workview Office EDIFNETI 7.4: viewbase error 413: Pin not on symbol error
Xilinx Answer #3083 : M1.3/M1.4 Map - ERROR - No more route-throughs available
Xilinx Answer #3085 : M1.3: TIMING: Page Fault in Win95, FATAL_ERROR:baspp:basppphys on Workstations
Xilinx Answer #3086 : M1.3 MAP:x4kma:x4kmagrclapse.c illegal situation for H1 pack:<block>
Xilinx Answer #3090 : Xilinx (FPGA/CPLD) configuration run times (configuration rates/programming times)?
Xilinx Answer #3091 : Foundation F1.3, Timing Simulator: Same bus name with different indices gives 'X' outputs
Xilinx Answer #3092 : Foundation F1.3 State Editor: when selecting HOLD for Unsatisfied Conditions, selection not kept.
Xilinx Answer #3094 : V1.4.0, V1.5.0 COREGEN: Warning: Your directory path <directory_path> should not contain any directory names longer than 8 characters.
Xilinx Answer #3096 : M1: How to convert an existing XACTstep 5.x design to use the M1.x tools
Xilinx Answer #3098 : XABEL: Does Foundation F1.3 need to be installed to use XABEL with Alliance software?
Xilinx Answer #3099 : PCI Core Generator 2.0: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler v1997.08, VerilogXL v2.5, and M1.3.7
Xilinx Answer #3100 : Foundation F1.3 Project Manager, WinNT: "Library access error" and "lmacs: ...unable to access transaction control file" in WINNT
Xilinx Answer #3101 : XABEL 6: Feedback signals interpreted differently in M1 (EDIF) than XACT(PLD)
Xilinx Answer #3102 : M1.3 EPIC - How to use EPIC commands to globally lock components.
Xilinx Answer #3103 : PCI Core Generator 2.0: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Compiler & VSS v1997.08, and M1.3.7
Xilinx Answer #3105 : PCI Core Generator 2.0: Verilog synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v1.2, & M1.3.7
Xilinx Answer #3106 : Hardware Debugger M1_3.7: Is XC5200 supported?
Xilinx Answer #3107 : M1.3 LogiBLOX: WinNT w/ Numer Nine video card may crash when component is created; N9I128V2.dll
Xilinx Answer #3108 : PCI Core Generator 2.0: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v1.2, & M1.3.7
Xilinx Answer #3109 : Viewlogic: ViewDraw 7.31 is missing BAF2VL.EXE, cannot run XREF
Xilinx Answer #3111 : M1.4 PAR - Turns engine requires explicit use of -pl and -rl switches towork.
Xilinx Answer #3113 : M1.4 Ngdbuild - Schematic DRIVE property for 4KXV devices is not being passed to map and is lost.
Xilinx Answer #3114 : HardWire: Where to get speed files?
Xilinx Answer #3115 : XC2000: Considerations when Migrating an XC2000 Design to a Newer DeviceFamily
Xilinx Answer #3116 : Typical I/V Characteristics of XC9500 Outputs
Xilinx Answer #3117 : NGDANNO: Problems with timing simulation not matching functional simulation, outputs stuck at X or 0
Xilinx Answer #3119 : Is it possible to run more than one version, multiple versions of lmgrd/flexlm at one time?
Xilinx Answer #3120 : Foundation Simulation seems to hang, or takes a long time before showingthe waveform
Xilinx Answer #3121 : HITOP: xr52:[Warning]NET 'xxxx' is driven by 'yyy' and 'zzz'.
Xilinx Answer #3122 : How do the BUFGSR, BUFG, OE buffers work on the 9500 cpld?
Xilinx Answer #3123 : XC9500: How are inital states of flip-flops determined on the 9500 CPLD's?
Xilinx Answer #3124 : Foundation F1.3/F1.4 Simulator: Selective preset feature may disrupt theoperation of counters, state machines
Xilinx Answer #3125 : M1.4 CPLD: Automatic Local Feedback optimization not yet supported for XC9500
Xilinx Answer #3126 : M1.4 CPLD: A fitter crash may result from properties applied to wrong objects
Xilinx Answer #3127 : M1.4 CPLD: Possible solution for excessive run time of Bus Error problems with the fitter
Xilinx Answer #3128 : M1.4 JTAG Programmer: Long JEDEC/BSDL file names obscured in the display
Xilinx Answer #3129 : M1.4 JTAG Programmer: Context-Sensitive help does not work.
Xilinx Answer #3134 : A1.5/1.4: How to import a VHDL, Verilog, or LogiBLOX generated netlist into a Concept schematic
Xilinx Answer #3135 : M1.4 GUI: 'Optimize & Map' tab for 5k implementation template has an incorrect option
Xilinx Answer #3136 : How does the XILINX_PATHLIMIT environment variable work?
Xilinx Answer #3137 : Hardware Debugger M1.3: FATAL_ERROR:baspm:baspmdlm.c:187:1.18 - dll openfailed...
Xilinx Answer #3138 : Foundation F1.3/F1.4 Logic Simulator: ASCII test vector, cannot use u orp option for timing
Xilinx Answer #3139 : dc2ncf: ERROR [#154]: Invalid argument -max for set_input_delay constraint at line x
Xilinx Answer #3142 : TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock pin *.CLKF
Xilinx Answer #3143 : M1 TRCE: Path tracing behavior for RAMs
Xilinx Answer #3144 : M1 NGDBUILD: ERROR:basnb:79 (pin mismatch) and ERROR:basnu:93 (unexpanded) on Exemplar design with instantiated modules
Xilinx Answer #3145 : Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one or more clock loads, but is not using a dedicated clock buff er
Xilinx Answer #3149 : M1.3, M1.4 NGD2VER: "Stuck at 0" and Stuck at "X" problems in Verilog simulation
Xilinx Answer #3150 : Foundation F1.3 State Editor, XABEL: Error APP_95 "<file>.edf does not exist" when creating macro
Xilinx Answer #3151 : Foundation State Editor F1.3/F1.4, XABEL: One-hot state machine is created "Cold"
Xilinx Answer #3152 : XABEL, Foundation F1.3/F1.4: ref_2_inst: dangling port (message during synthesis)
Xilinx Answer #3153 : XABEL, Foundation F1.3: Internal Error 18911 in Blif2net (abl2edif)
Xilinx Answer #3155 : Ngdbuild: ERROR:basnu-The signal "GSR" in block "<component>" uses a Xilinx reserved global signal name
Xilinx Answer #3157 : PAR: Error: baspw: 134 Input design is empty.
Xilinx Answer #3159 : M1.3.7 LOGIBLOX: XC4000XL is missing from the device family pull-down menu
Xilinx Answer #3160 : HW130 v4.1.0, 9572: Verify failures on 9572-PC44 devices
Xilinx Answer #3161 : Foundation F1.3/F1.4 Simulator: How much memory does a simulation require?
Xilinx Answer #3162 : XC9500: What is the Maximum Junction Temperature allowed in the CPLDs
Xilinx Answer #3163 : NGD2VHDL, NGD2VER, NGD2XNF: ERROR:basut:79 - File system full!
Xilinx Answer #3164 : Can not open books in dynatext
Xilinx Answer #3165 : XC4000EX/XL: Some BUFGEs (Eearly buffers) are faster than others
Xilinx Answer #3167 : M1.4 NGD2VER: How to have M1 automatically specify the addition of the `uselib directive and path to the simulation netlist
Xilinx Answer #3168 : M1 Performance Pack: HWDEBUGR patch not installed correctly
Xilinx Answer #3169 : M1 Performance Pack: Usage of Lab Install
Xilinx Answer #3170 : M1.3 Design Manager: Fatal Exception while running M1.3 tools on NT
Xilinx Answer #3171 : XC4000EX/XL/XV/XLT: How to accurately locate BUFGLS and BUFGE components
Xilinx Answer #3173 : Boundary Scan/JTAG: How to read the Xilinx XC9500 SVF files?
Xilinx Answer #3174 : Foundation F1.3, XVHDL 3.0.2/3.0.3: Using a dedicated input pad for an instantiated global buffer (bufg)
Xilinx Answer #3175 : Foundation F1.3, Logic Simulator: Simulator will hang if status line hasbeen deselected
Xilinx Answer #3176 : Foundation F1.3, 3K/5K Early Access Libraries
Xilinx Answer #3177 : Boundary Scan/JTAG: How to co-relate the states in the XC9500 SVF files to TAP controller states?
Xilinx Answer #3178 : M1.4 ngd2edif: ERROR:basng - (NGD-internal) bFATAL_ERROR:baspp:basppres.c:828:1.15
Xilinx Answer #3181 : M1.3, Dynatext, Xilinx Books: After installing Dynatext, no books are available.
Xilinx Answer #3182 : M1.5 EPIC: EPIC may crash on some systems with the autorouter turned on
Xilinx Answer #3185 : NGD2VER: Long run times may be due to -r option for hierarchical netlist
Xilinx Answer #3186 : Foundation F1.3 XABEL: BLIF2OPT hangs or gives virtual memory overflow error
Xilinx Answer #3187 : Foundation F1.3 XABEL: Heavily constrained designs may cause fitter to core dump
Xilinx Answer #3188 : Foundation F1.3 XABEL: Ambiguous interpretation of feedback signals
Xilinx Answer #3189 : ALPHA v3.0.x COREGEN: patch to Alpha v3.0.1 available on Xilinx ftp siteinstall instructions
Xilinx Answer #3190 : Why M1 needs Admin Privilege to install on NT
Xilinx Answer #3192 : M1.3 Performance Pack: How to install
Xilinx Answer #3193 : COREGEN, VERILOG: How to do functional and backannotated timing simulation of designs with COREGen modules in M1
Xilinx Answer #3194 : XC9500: What is the default value of tri-states for CPLDs?
Xilinx Answer #3196 : MAP: What is an MDF file?
Xilinx Answer #3197 : M1.4 Logiblox: Error - Bus Conflicts during Foundation simulation
Xilinx Answer #3198 : BITGEN M1.3.7: Design does not work when tie-down feature is used.
Xilinx Answer #3200 : DRC needs to check for the shared EC/O wire used with ECMUX:0
Xilinx Answer #3202 : Foundation F1.4: Foundation Library format issues
Xilinx Answer #3203 : Boundary Scan/JTAG: Description of TAP Controller states
Xilinx Answer #3204 : M1.4, Map, 5200,-r ,-pr , basut: Error:basut - Switch "-r" is not allowed.
Xilinx Answer #3205 : Foundation F1.4. Logic simulator: Bus ordering reversed after bus has been flattened, then combined
Xilinx Answer #3206 : Foundation F1.4 Project Manager: "Update HDL Macros" option in Project Manager Document menu not found
Xilinx Answer #3207 : M1.3 Hitop - Unnecessary warning about 95108 UPGs not supported
Xilinx Answer #3208 : M1.3.7 Hitop - Hitop crashes if there are more than 20 timespecs in the .ncf file.
Xilinx Answer #3209 : M1.4 PAR - PAR does not run any cleanup passes by default in M1.4.
Xilinx Answer #3210 : M1.3 CPLD - The XC95144 pinout has changed
Xilinx Answer #3213 : M1.3 Hitop - Hitop core dumps on a specific case.
Xilinx Answer #3214 : XC9500: Difference between all the checksums for the 9500 family
Xilinx Answer #3216 : M1.3.7 PAR: UCF LOC constraint on net does not override conflicting schematic pad constraint.
Xilinx Answer #3217 : M1.3/M1.4 MAP - Map crashes due to an illegal pad configuration.
Xilinx Answer #3219 : Foundation F1.4 Simulator, XC3000: Outputs are undefined in Timing Simulation
Xilinx Answer #3221 : Foundation F1.4 Project Manager: Netlist creation error if path has a dot (.) character
Xilinx Answer #3222 : Foundation F1.3/F1.4, Timing Simulation: When bus has same label, but different indices, get X out
Xilinx Answer #3223 : Foundation F1.4 Simulator: Last line ignored inside a command/script file
Xilinx Answer #3224 : F1.4: FPGA Express 1.2/2.0: Comparators may not infer carry logic
Xilinx Answer #3225 : Foundation F1.4 Schematic Editor: Library symbol SR8RLED is different size in 3k library
Xilinx Answer #3226 : 9500: What are the recommended maximum rise times for inputs?
Xilinx Answer #3227 : Foundation F1.3/F1.4: Project cannot have same name as macro (circular reference)
Xilinx Answer #3228 : Foundation F1.3/F1.4 State Editor: Logical Error 1002: Source line length exceeds 150 character
Xilinx Answer #3231 : Foundation F1.4: Uninstall program will preserve user projects, but remove sample projects
Xilinx Answer #3232 : Hardware Debugger, M1.3 & M1.4 Lab Install, Error Baspm:Baspmdllm 174 & 187 dll open of library libx4xbs.dll
Xilinx Answer #3233 : Viewlogic: Aurora Synthesis 7.4 produces global GND and VDD instances inschematics; NGDBUILD fails
Xilinx Answer #3234 : Foundation XVHDL: Using mode pins (MD0, MD1, MD2) for general I/O
Xilinx Answer #3235 : F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work
Xilinx Answer #3236 : M1.4 Spartan - A patch is available to provide the PQ208 package for Spartan s20, s30 and s40 devices.
Xilinx Answer #3237 : M1.3 CPLD - Fitter drops inverter from Express XNF when IBUF drives OBUFT.
Xilinx Answer #3238 : M1.3 CPLD - CPLD Patch available for several issues
Xilinx Answer #3239 : M1.3 CPLD - A -6 speed grade has been added for XC9536.
Xilinx Answer #3240 : M1.3 CPLD - There have been pinout changes for the XC95144 device.
Xilinx Answer #3241 : M1.3 CPLD - Bitmap is incorrect for XC95288.
Xilinx Answer #3242 : M1.3 Hitop - Fitter fails to meet Period timespec for easy design.
Xilinx Answer #3243 : M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
Xilinx Answer #3244 : M1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:1879:1.145
Xilinx Answer #3245 : M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
Xilinx Answer #3246 : M1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:2585:1.145.12.2 - Too many signals to move..
Xilinx Answer #3247 : M1.4 Map - FATAL_ERROR:baste:bastecomp.c:564:1.72 - Moving BEL from U7451 to occupied belsite ...
Xilinx Answer #3248 : M1.4 Core Tools - All M1.4 bug fixes available in M1.4 Core Tools Patch on the Xilinx Download Area.
Xilinx Answer #3250 : M1.4 Map - FATAL_ERROR:x4kma:x4kmacarry.c:2703:1.122 - Illegal call to swap.
Xilinx Answer #3251 : M1.4 Map - Mapper fails with Application Fault on EX and XL Devices on PC only.
Xilinx Answer #3252 : XC9500: Miscellaneous programming questions
Xilinx Answer #3253 : XABEL, M1.4: Using XABEL with M1.4 Alliance software
Xilinx Answer #3254 : XC9500: How to create a single SVF file from multiple SVF files for devices in a single chain?
Xilinx Answer #3255 : XC9500: How to program mulitple devices in a single chain using the HP3070 tester?
Xilinx Answer #3256 : M1.5 NGDBUILD: OFFSET constraint gives "ERROR:basts:69 - NET CLK ... is not a pad-related net"
Xilinx Answer #3259 : Foundation/F1.3, MAP, baste Error: baste 164:components with same name...uniquifying.
Xilinx Answer #3260 : M1.3, PAR, baspw, Error: baspw:97 PAR: Not all timing constraints could be satisfied.
Xilinx Answer #3263 : M1.5 EPIC: How to select an entire net
Xilinx Answer #3265 : M1.4 LogiBLOX: Discrepancy between Dual Port RAM Simulation and DynatextDocumentation.
Xilinx Answer #3268 : PCI Core Generator 2.0: VHDL synthesis/simulation with PCI LogiCORE v2.0, FPGA Express v2.0.2, & M1.4.12
Xilinx Answer #3269 : M1.4 MAP: NMC hard macro cannot be LOC'd from the UCF file
Xilinx Answer #3271 : M1.4 General - A patch is available to add CB228 package to XC4028EX.
Xilinx Answer #3272 : M1.4: How to set up LM_LICENSE_FILE when using Veribest and WorkView Office
Xilinx Answer #3273 : SPARTAN: Explanation of speedgrades in Spartan
Xilinx Answer #3275 : CPLD M1.3(patch),M1.4: Pin location assignments for 9500 designs are notseen
Xilinx Answer #3276 : Foundation F1.3 Schematic, NGDBUILD: ERROR: basnu - logical net "net_name_int" has both active and tristate drivers
Xilinx Answer #3277 : ERROR:basnb:83 -Invalid file argument "file location.UCF"
Xilinx Answer #3278 : XABEL: how to implement a bidirectional bus in abel
Xilinx Answer #3279 : Foundation F1.4 Simulator, XC5200: Outputs are undefined in Timing Simulation
Xilinx Answer #3280 : OBSOLETE!!!!!!!!!!!!
Xilinx Answer #3281 : M1.4 General - A patch is available to add the CB228 package to XC4036XLand XC4062XL devices and BG432 to XC4085XL device..
Xilinx Answer #3283 : XC4000XL/XV: XV vs XL Architectural Differences
Xilinx Answer #3284 : XC5200: Power on delay of 4mS is too fast for power supplies
Xilinx Answer #3285 : M1.4 Timing Analyzer reports "0 items analyzed" on a period constraint.
Xilinx Answer #3289 : PROM File Formatter M1.3: basbs 189- Cannot load from an address other than 0 with a serial PROM.
Xilinx Answer #3293 : MAP terminates abnormally after successfully writing output files (.ncd and .mrp).
Xilinx Answer #3294 : M1 JTAGPGMR: Basic debugging techniques for downloading design
Xilinx Answer #3295 : M1.4 Security: How can I get the license manager to run as a service onNT?
Xilinx Answer #3296 : FPGA Express 1.2: Optimization FE-PADMAP-3 error
Xilinx Answer #3299 : F1.3: SIMUL caused a general protection fault, will shut down.
Xilinx Answer #3300 : FPGA Express 2.0: Errors/Warnings/Messages window does not always work correctly
Xilinx Answer #3301 : FPGA Express 2.0/Foundation 1.4: Creating HDL Macros with FPGA Express 2.0 for Placement on a Foundation 1.4 Top-Level Schematic
Xilinx Answer #3302 : M1, Timing, CPLD: What are negative setup times in CPLD Performance report?
Xilinx Answer #3303 : Workview Office 7.31, 7.4: Initialization Error written to viewdraw.err while starting ViewDraw
Xilinx Answer #3305 : M1.3/M1.4 ngd2xnf does not support 4000EX/XL/XV
Xilinx Answer #3306 : Design Manager M1.3/M1.4/M1.5: GUI will not start under Solaris 2.5.x/2.6
Xilinx Answer #3307 : M1.3/M1.4 hplusas6: JEDEC File generator not writing ABEL test vectors in the JED file
Xilinx Answer #3308 : FPGA Express 2.0: Turbo Mode may cause Alliance version of FPGA Express to crash
Xilinx Answer #3311 : M1.4 Map - Optimization of OFDT symbol results in dangling tri-state control pin
Xilinx Answer #3312 : M1.4 Map - ERROR:baste:262 - Bad format for LOC constraint
Xilinx Answer #3313 : XVHDL F1.3: XVHDL caused an invalid page fault in module XVHDL.EXE
Xilinx Answer #3314 : M1.4 Map - Map crashes trying to push buffer/inverter into hard macro (.nmc).
Xilinx Answer #3315 : M1.4 Ngdanno - Annotated delays for DP RAM produce sim results inconsistent with TRCE.
Xilinx Answer #3316 : M1.4 PAR - PAR fails with Arithmetic Exception on a hard maco design.
Xilinx Answer #3317 : M1.4 PAR - PAR core dumps during Initial Timing Analysis.
Xilinx Answer #3319 : M1 Logiblox: Security, Error:basne-security error-unable to lock license...
Xilinx Answer #3320 : ViewSim - "Error: Could not find memory component U1" when loading XMM file
Xilinx Answer #3321 : XC9500:Is there a reset or a done pin for CPLDs to determine if the device runs correctly?
Xilinx Answer #3322 : CPLD: Can the 9500 output buffer drive the load of several 9500s?
Xilinx Answer #3323 : SYNPLIFY: How to instantiate the STARTUP for a XC5200?
Xilinx Answer #3325 : V1.5.0, V1.4.0 COREGEN: java.lang.OutOfMemoryError "Out of memory" errors on very large cores
Xilinx Answer #3327 : COREGEN: When are TBUFs used for muxing in single and dual port RAMs?
Xilinx Answer #3328 : 98 DATA BOOK: BGA352/BGA432 package outline error on page 10-34
Xilinx Answer #3329 : ngd2vhdl M1.3/M1.4: Why does ngd2vhdl create a data type called std_logic_vector2?
Xilinx Answer #3330 : Foundation F1.3, FPGA Express: Functionality incorrect for Express modules on Schematics
Xilinx Answer #3331 : Xilinx Software YEAR 2000 compliance
Xilinx Answer #3332 : M1.3/1.4 TRACE: A DPRAM DPO to destination FROM:TO constraint is not analyzed
Xilinx Answer #3333 : M1.5 TRACE: What to do about tilded values (~46ns) in the report
Xilinx Answer #3339 : Foundation XVHDL: Instantiating OSC52 in a 5200 design
Xilinx Answer #3342 : M1.4 PAR - Mode pins and TDO do not show up in pad report for FPGAs
Xilinx Answer #3343 : M1.3/1.4: ERROR: basnb:83(in PC) or basut( in WS): complains about invalid file argument "<design>.UCF"
Xilinx Answer #3344 : M1.4 Turns Engine: ERROR - PING cannot reach node 'node_name'
Xilinx Answer #3345 : A1.4: What's new in A1.4 XSI
Xilinx Answer #3350 : M1.4 JTAG Programmer: Problems communicating to the serial port on HP-UX
Xilinx Answer #3352 : Spartan: Targeting Spartan devices in Viewlogic schematics
Xilinx Answer #3357 : M1.4 Map - Incorrect mapping leads to DRC warning about component pin with no signal attached.
Xilinx Answer #3358 : XABEL: How to lock down (constrain) pins through ABEL code
Xilinx Answer #3359 : What kinds of information IBIS Models do and don't provide.
Xilinx Answer #3364 : Foundation BASE package: Dynatext browser not installed by default
Xilinx Answer #3372 : SYNPLIFY: Synthesizes XBLOX components for 3100A and 3000A devices targeting M1
Xilinx Answer #3374 : M1: WARNING:bastw:174- The current connection evalutation limit of 1000 caused ....
Xilinx Answer #3377 : EXEMPLAR: Instantiating a pulldown/pullup in Verilog?
Xilinx Answer #3378 : PAR M1.4: FATAL_ERROR:basrt:basrtsanity.c:167:1.3 - Process will terminate.
Xilinx Answer #3379 : M1.4, Map, Error: FATAL_ERROR:x4kma:x4kmamerge.c:2460:1.145...
Xilinx Answer #3380 : Licensing the Alliance version 1.4 software (PC and UNIX)
Xilinx Answer #3381 : M1.4 Map - FATAL_ERROR:x4ema:x4emaclb.c:663:1.44:5.2 - Flop in Y found
Xilinx Answer #3384 : XABEL M1.3 - Slew rate property does not work with EPLD patches
Xilinx Answer #3385 : M1.4,NT,Map,FATAL_ERROR:x4kma:x4kmagrclapse.c:1953:1.90.12.2 - No pin for sig...
Xilinx Answer #3386 : M1.4: Fatal error: basnc:basncgrid.c:129:1.5: grid file from xilinx:5200:5210: is corrupted
Xilinx Answer #3387 : M1.3/M1.4: Hitop, Done: Failed with exit code: 002
Xilinx Answer #3389 : M1 docs., library guide,X74_168: Fig. 12.12, shown cascading counter is wrong.
Xilinx Answer #3391 : M1.4, NT, PAR, INTERNAL_ERROR:baspl:basplbscore.c:553:1.17
Xilinx Answer #3392 : M1.3 Map - FATAL ERROR:x4kma:x4kmacarry.c:681:1.96.10.4 - COUTO...
Xilinx Answer #3393 : Hardwire: What package are available in Hardwire for FPGA?
Xilinx Answer #3395 : Foundation F1.3/F1.4: LMACS and Btrieve errors and what to do about them!
Xilinx Answer #3396 : M1.4 PAR - XC4000 design crashes after starting the Initial Timing Analysis.
Xilinx Answer #3397 : Foundation: Can I use Alliance 1.4 implementation tools with F1.3 or F1.4?
Xilinx Answer #3400 : M1.4 CPLD: C1244, internal error, corrupted partition product term.
Xilinx Answer #3401 : Workview Office 7.4, Windows NT: Path to LogiBLOX under tools menu is incorrect
Xilinx Answer #3402 : FPGA Express 1.2/2.0: clock buffer not inserted if clock net sources RAMs or Black Boxes
Xilinx Answer #3403 : A1.4/F1.4: Some figures in the 1.4 Hardware User Guide are incorrect
Xilinx Answer #3404 : M1.3/M1.4 CPLDs: How to use the 'TIE' option of unused pins in 9500 devices
Xilinx Answer #3405 : M1.4 Map - Map will sometimes run FLUT to Flop connection through an HLUT routethru.
Xilinx Answer #3406 : EZTAG: How to generate a .svf file?
Xilinx Answer #3407 : M1.4 MAP:ERROR:x4kma:371 - IBUF symbol "symbol_name" is unable to combine with ...
Xilinx Answer #3409 : Foundation Simulator: End of time error
Xilinx Answer #3410 : Design Mangager/ngdbuild M1: Application error/Invalid Page Fault in module mfc40.dll
Xilinx Answer #3411 : M1.4: Spartan devices do not appear in the Part Selector dialog box
Xilinx Answer #3416 : M1 Constraints: How to specify a specific CLB to LOC an instance to.
Xilinx Answer #3417 : CPLD, M1.3/M1.4: How to run the JTAG Programmer, Hardware Debugger and PROM File Formatter as a stand alone?
Xilinx Answer #3418 : What are the latest version of the JTAG/Parallel schematic & cable?
Xilinx Answer #3419 : M1.4 License: lmutil lmhostid returns hostid of all zeros
Xilinx Answer #3421 : M1.4 MAP: ERROR: x4kma:111 -- Design is empty
Xilinx Answer #3423 : 96/98 DATA BOOK: RAM: Write enable pulse width following active edge of WCLK.
Xilinx Answer #3427 : M1.4 MAP: ERROR:x52ma:250 This type of signal is not supported by the XC5200 ...
Xilinx Answer #3431 : M1.4 MAP/PAR: BUFG is not routed properly for 3164Apc84 package.
Xilinx Answer #3436 : FPGA Express: Instantiations in VHDL are UNLINKED (FE-CHECK-4)
Xilinx Answer #3438 : A1.4/F1.4 Bitgen - Bad 5200 bitstream is created for IOB routethrus and CLB latches
Xilinx Answer #3440 : Map M1.4.12 ERROR:basut:162 - This Xilinx application has run out of memory
Xilinx Answer #3441 : A1.4: How to Target the Spartan Device With Most Schematic and SynthesisTools When a Library is Not Yet Availible
Xilinx Answer #3442 : M1.4 CPLD - A patch is available for several issues.
Xilinx Answer #3444 : NGDBUILD: Could not find NET " " in design " " with Cadence Concept design
Xilinx Answer #3445 : Xact 5.2.1: Floorplanner core dumps on HP-UX 10.xx
Xilinx Answer #3447 : MAP FATAL ERROR: Illegal situation for H1 pack.
Xilinx Answer #3448 : M1.4 Map - Map crashes for a specific case. A patch is available.
Xilinx Answer #3449 : M1.4 MAP:FATAL_ERROR:basnc:basncsignal.c:262:1.62
Xilinx Answer #3450 : MAP M1.4: ERROR:x4kma:312 - The following symbols could not be constrained...
Xilinx Answer #3451 : M1.4 Map - If mapper has errors, the map report (.mrp) doesn't contain trim information.
Xilinx Answer #3452 : FATAL_ERROR: baste:bastecomp.c:1943:1.61.9.3 - idx not found.
Xilinx Answer #3453 : Alliance 1.4: Operating system, disk space, memory and swap space requirements
Xilinx Answer #3454 : Foundation F1.3/F1.4, XVHDL, Synthesis, grayed, Error: Hde: Foundation option in xilinx, Keylock not found. (Sentinel driver)
Xilinx Answer #3455 : M1.4 Ngdanno - ERROR : Non numeric pin number 'P90' found.
Xilinx Answer #3456 : M1.4 PAR - Some xc5200 designs core dump.
Xilinx Answer #3457 : M1.4 PAR - The xc3000 and xc5200 routers will incorrectly use route-thrus in unused bonded pads.
Xilinx Answer #3458 : core dump on Win95 platform during fplan run
Xilinx Answer #3459 : M1.4 Ngdanno - Timing discrepency between Trce and back annotated timingfor EQN logic.
Xilinx Answer #3460 : M1.4 NGDANNO - Ngdanno fails to properly annotate back to logical representation.
Xilinx Answer #3461 : M1.4 PAR - PAR runs out of memory during placement of design with hard macros (.nmc's) that contain routing information.
Xilinx Answer #3462 : M1.4 PAR - PAR crashes on a specific xc5200 case.
Xilinx Answer #3463 : M1.4 PAR - PAR hangs when using a PCF to LOC single component hard macros (.nmc's).
Xilinx Answer #3465 : Foundation Schematic Editor F1.3/F1.4: How to print all black schematics(instead of grey scale).
Xilinx Answer #3466 : M1 Constraints/UCF/TRCE: How fine can the resolution be on timing constraints?
Xilinx Answer #3469 : M1.x Install: Windows protection error (caused by 3com network board running OSR2)
Xilinx Answer #3470 : M1.4 Constraints: LOC'ing a PAD to an edge or multiple sites
Xilinx Answer #3471 : Design Manager M1: Gui fails to execute, open or start.
Xilinx Answer #3473 : Spartan: Pinouts on the Version 0.6 of the data sheet are incorrect.
Xilinx Answer #3474 : M1.3/M1.4 Map FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL U3/N1304 belong
Xilinx Answer #3476 : M1.4 EPIC - How to make use of history substitution on the EPIC command line.
Xilinx Answer #3477 : Foundation Express 2.0: Module compile inserts STARTUP and clock buffers
Xilinx Answer #3480 : Foundation Express: Upgrading licenses for Express 2.0.x
Xilinx Answer #3482 : M1.4 LogiBLOX: How to constrain a 4KE/X LogiBLOX Counter
Xilinx Answer #3483 : floating license: While running M1.x dialup networking is evoked severaltimes
Xilinx Answer #3486 : SYNPLIFY: How does Synplify handle asynchronous set/reset flip-flops (DFFRS)?
Xilinx Answer #3487 : The HW-112 Programmer is also known as the PP1 (and PP2)
Xilinx Answer #3488 : M1: What is in the $XILINX/xc4500e directory?
Xilinx Answer #3490 : Workview Office: Calc tutorial needs newer commmand (.CMD) files
Xilinx Answer #3491 : M1.4 JTAG Programmer: How to Create SVF files that support BULK Erase
Xilinx Answer #3493 : V1.4.0 COREGEN: Incorrect data on output of PDA FIR and SDA FIR cores when maximum output width is not selected
Xilinx Answer #3494 : Workview Office 7.4: Tutorial in "Getting Started" guide will not work with Xilinx license
Xilinx Answer #3497 : F1.x State Machine Editor: Syntax Error 1031: Undefined identifier name 'SREG0'
Xilinx Answer #3498 : V1.5, V1.4 COREGEN: Does COREGen support floating point values in the .COE coefficient files?
Xilinx Answer #3499 : M1.4 PAR: ERROR: x45dr - netcheck: / Warning: basrt
Xilinx Answer #3506 : Foundation\FPGA Express 2.0: Adding new libraries for Express projects
Xilinx Answer #3508 : MAP: CY4 Symbol Errors. FPGA Express: Reading xnf or edf netlists into project.
Xilinx Answer #3509 : M1.4 Win95 - A patch is available to address slow runtimes for applications that load/write .ngd files.
Xilinx Answer #3512 : Viewlogic: Inverted signals (with tilde, ~) can be used with M1
Xilinx Answer #3513 : M1 NGDBUILD: invalid NCF/UCF file entry value "~" detected on line ##.
Xilinx Answer #3516 : M1.4 Timing: Do NOT use the FTP patch M1.3.7 speed files for EX
Xilinx Answer #3517 : M1.4 TRACE: Do NOT activate CMOS level timing for XL family
Xilinx Answer #3518 : 9500: What are the differences between reset lines in simulation and onthe device
Xilinx Answer #3519 : M1.4 XC3000/3100: The signal "<signal between ipad and bufg>" is unused and has been removed.
Xilinx Answer #3522 : M1.4: Error in bitgen: error:basbs no bfd file specified
Xilinx Answer #3523 : V1.5, V1.4 COREGEN: Required license features for Viewlogic Viewdraw interface executables used by COREGen v1.4.0 (EDIFNETI, EDIFNETO, VHDL2SYM)
Xilinx Answer #3524 : M1.4 Map - Map creates an illegal IOB configuration with conflicting EC pin and OMUX usage.
Xilinx Answer #3525 : M1.4 Map - 5200: Map is not trimming global reset signals
Xilinx Answer #3526 : MAP M1.4 - Application error on XC4000E design during the "Optimizing" phase.
Xilinx Answer #3527 : M1.4 Map - FATAL_ERROR:basnc:basncsignal.c:262:1.62 - Could not find a bel for a signal...
Xilinx Answer #3528 : M1.4 PAR - PAR core dumps when trying to place a large xc4000xv design
Xilinx Answer #3529 : M1.4 Ngdanno - Ngdanno must be updated to handle new CB228 pkgs for 4kxldevices in x1.4.
Xilinx Answer #3530 : M1.4 Ngdanno - Ngdanno fix to allow back annotation to logical model forcase not covered.
Xilinx Answer #3531 : Foundation F1.4 Install: Not all 4000XL devices installed by default
Xilinx Answer #3532 : A1.4/F1.4 - List of all Software Updates with dependencies
Xilinx Answer #3533 : A1.4/F1.4 CPLD - List of all CPLD patches available in A1.4/F1.4.
Xilinx Answer #3534 : M1.x: How to preserve the pinout of a previous PAR run (pad2ucf)
Xilinx Answer #3535 : Foundation Logic Simulator: WARNING: More than one normal (Totem_Pole) output in the folloing node...
Xilinx Answer #3536 : M1.4 hwdebugr: Hardware Debugger does not load FPGA bit files successfully in Lab Install environment.
Xilinx Answer #3540 : Foundation Simulator, Logiblox, F1.4: Async_Val not simulated at power-up or GSR.
Xilinx Answer #3541 : F1.4, Demo License, Docs, Features: Demo license prevents use of Constraints GUI in Express
Xilinx Answer #3560 : Foundation F1.4: Xilinx Online Books (Dynatext) not installed by default
Xilinx Answer #3561 : Spartan: What is the comparison between Spartan and 4000E families?
Xilinx Answer #3562 : Foundation F1.3/F1.4, XABEL: Xabel.exe not found
Xilinx Answer #3563 : XC3000A: Map ignores LOC on pads driving BUFG
Xilinx Answer #3564 : FPGA Express 2.0: Selecting Synthesis->Options causes Express to crash
Xilinx Answer #3566 : FPGA Express 2.0, Foundation Express 1.4: Patch version 2.0.3 available
Xilinx Answer #3567 : 9500:CPLDs can not source logic with a global buffer
Xilinx Answer #3568 : Foundation Simulator F1.4: Keyboard toggle may not work
Xilinx Answer #3569 : SPARTAN: Pinouts for XCS20 and XCS30 in PQ208 package are incorrect in 1998 Databook
Xilinx Answer #3570 : A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on routing which is not available because the EC pin is using the Logic Zero option.
Xilinx Answer #3571 : XC95108 with date code of 9717 is not configuring
Xilinx Answer #3575 : M1.4 : Dynatext gives Dynatext 3.0 Config Error 5055
Xilinx Answer #3577 : 3100 F1.4/A1.4: NGDANNO: FATAL_ERROR:basna:basnasite.c:131.1.3 - cannotfind BEL delay TCKI...
Xilinx Answer #3579 : 9500: What are the checksums in a JEDEC file and how do I read it?
Xilinx Answer #3580 : Foundation F1.4: Is it year 2000 compliant?
Xilinx Answer #3581 : EZTAG 6.0.1: How to Program without Erasing from the command line.
Xilinx Answer #3582 : Quick Start Guide for Xilinx Alliance Series 1.4: where to find it on the web?
Xilinx Answer #3583 : FPGA Express: How to avoid latch inferences
Xilinx Answer #3584 : SYNPLIFY: How to use OSC5, OSC52, and CK_DIV cells for the XC5200 in HDL?
Xilinx Answer #3585 : M1 PAR: Is there a way to prevent route-thrus?
Xilinx Answer #3587 : Design Manager M1.4/M1.5: How to generate a VHDL/Verilog test fixture/testbench file
Xilinx Answer #3588 : M1.4/Design Manager/template Manager: Customized options not added to template.
Xilinx Answer #3590 : Foundation XVHDL, CPLD: How to set global signals (tristate, set/reset, clock)
Xilinx Answer #3592 : Spartan: What library components in the 4000E library are not supported by spartan devices
Xilinx Answer #3594 : SYNPLIFY: How to invert the reset (GSR/GR) pin on the STARTUP block in HDL?
Xilinx Answer #3595 : NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a SYNPLICITY design
Xilinx Answer #3596 : 9500: What cables and voltages can I use to program a CPLD?
Xilinx Answer #3597 : Fatal_error:x3kma:x3kmarmunused.c:120:1.8 remove input sig U9/$Net00047_from comp U9/$I67 causes empty F func.
Xilinx Answer #3598 : WVO 7.4: LogiBLOX library file for VHDL simulation with Workview Office 7.4
Xilinx Answer #3599 : Foundation F1.3/F1.4 HDL Editor: Bus pins not created for ABEL macros
Xilinx Answer #3605 : Foundation F1.3/F1.4, XABEL: ahdl2blf exited with error code 1
Xilinx Answer #3606 : Foundation F1.4: PDF versions of Quickstart Guide, Express User Guide, Release Notes (docs)
Xilinx Answer #3608 : M1.3/M1.4 JTAG Programmer: How to create an SVF file
Xilinx Answer #3611 : NGDBUILD: "logical block" of type 'DFFRSE' is unexpanded with a SYNPLICITY design
Xilinx Answer #3615 : MAP M1.4.12: FATAL_ERROR:x4kma:x4kmaclkbuf.c:591:1.25 - No input sig on CLKBUF inst_name.
Xilinx Answer #3616 : A1.4/F1.4 Map - Map runs out of memory on designs containing more than 64K logic primitives.
Xilinx Answer #3617 : A1.4/F1.4 Map - Map causes an invalid page fault inmodule libbaste.dll at...
Xilinx Answer #3618 : A1.4/F1.4 Map - Map enhancement to add support for guiding BUFGP/S for floorplanning
Xilinx Answer #3619 : A1.4/F1.4 DC2NCF: set_output_delay command affects following set_max_delay command
Xilinx Answer #3622 : Workview Office: Required License file not found (Errror 8030)
Xilinx Answer #3624 : FPGA Express v2.x (Foundation & Alliance): How to install FPGA Express v2.x for use on a PC network
Xilinx Answer #3627 : V1.5, V1.4 COREGEN GUI: Hourglass "busy" cursor lingers indefinitely until mouse is moved
Xilinx Answer #3628 : V1.5, V1.4 COREGEN: Errors when loading spec sheets in Acrobat 2.1
Xilinx Answer #3629 : V1.5, V1.4: COREGEN VIEWLOGIC: PINORDER property/attribute is visible onViewlogic symbols generated by COREGen
Xilinx Answer #3630 : M1.4: Can I use the JTAG/Parallel cable to configure an FPGA?
Xilinx Answer #3632 : M1.4:FATAL_ERROR:baste:bastetspec.c:1333:1.69 - TNM TI_H1 on NET 'TI_H1'has a reference that has no NC_BEL and no TECHMAP_SIGNAL
Xilinx Answer #3633 : V1.4.0 COREGEN: How to uninstall it
Xilinx Answer #3635 : Naming restrictions for CORE Generator modules (upper case names are illegal)
Xilinx Answer #3639 : V1.5, V1.4 COREGEN: How do I get my COREGen module implementation to match the performance / speed specified in the COREGen spec sheet?
Xilinx Answer #3641 : A1.4, F1.4, MTI: VHDL Timing Simulation produces "Error: a positive value of WIDTH must be specified"
Xilinx Answer #3649 : Foundation F1.4: Incorrect pin name in symbol editor
Xilinx Answer #3650 : JTAG/Boundary Scan: Using ATEs to program XC9500 devices
Xilinx Answer #3652 : XC9500 JTAG: Troubleshooting hints for the Embedded micorprocessor ISP programming
Xilinx Answer #3653 : XC9500: Device fails to erase when used in an embedded or ATE environment
Xilinx Answer #3654 : A1.4/F1.4 PAR - Problems with placement of Wide Edge Decoders or associated Pullups.
Xilinx Answer #3655 : M1.4 MAP: FATAL_ERROR:x4kma:x4kmamerge.c:4429:1.145.12.5 - Missing signal on pin 10
Xilinx Answer #3656 : XC9500: IDCODE instruction fails when used in an embedded or ATE environment using svf files
Xilinx Answer #3657 : MAP, PAR: Does Map or PAR insert global buffers on high fanout nets and/or unbuffered clock nets?
Xilinx Answer #3658 : CORE Generator v1.4.0: Known Problems / Issues (README file / release document).
Xilinx Answer #3661 : M1.4, map, Readback, NT, Dr.Watson: Exception: access violation...
Xilinx Answer #3662 : M1.4, map, Fatal_Error:x4kma:x4kmacarry.c:2946:1.130 - Illegal call to swap...
Xilinx Answer #3663 : Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
Xilinx Answer #3664 : M1.3/M1.4 Map: FATAL_ERROR:baste:bastetspec.c:1737:1.69
Xilinx Answer #3665 : fatal error in map on a 4052xl design.
Xilinx Answer #3666 : M1.4 Bitgen -- Output using OMUX2 stuck low...
Xilinx Answer #3668 : V1.4.0 COREGEN and later: How to determine the build version of the COREGenerator v1.4.x GUI
Xilinx Answer #3669 : Flow Engine M1: Error in reading flow definition file; unable to continue
Xilinx Answer #3670 : COREGen v1.4.0, Windows: Blank / empty warning message boxes pop up whenwarning message is too long on 800x600 video resolution (e.g., Viewlogic, PDA FI R)
Xilinx Answer #3672 : Hardware Debugger: Readback verification disabled in XC5200 designs...
Xilinx Answer #3673 : COREGEN v1.4.0: Solaris Stopwatch "busy" cursor or Windows hourglass cursor lingers (seems to hang) after an operation is completed.
Xilinx Answer #3674 : V1.4.0 COREGEN: Can v1.4.0 be installed over the Alpha 3.0.x release?
Xilinx Answer #3675 : COREGEN v1.4.0: Which cores / modules are being shipped in this release?
Xilinx Answer #3676 : COREGEN v1.4.0: How can I get a copy of the CORE Generator v1.4.0 CD?
Xilinx Answer #3677 : V1.5, V1.4 COREGEN: How can I install AcroRead on a Solaris system if it is not already installed?
Xilinx Answer #3678 : Foundation F1.4: Project Manager slow to open in Windows NT
Xilinx Answer #3679 : FPGA Express 2.0/Synopsys: RISING_EDGE vhdl syntax not supported. (VHDL-2204)
Xilinx Answer #3681 : V1.5, V1.4 COREGEN, LOGIBLOX: Differences between COREGen and LogiBLOX,which modules are generated as RPMs
Xilinx Answer #3682 : Foundation F1.4: Error when opening: "pcm:file timecore.cpp, line 58"
Xilinx Answer #3686 : M1.4: FATAL_ERROR:baslo:basloglobal.c:35:1.9 - on line 972 of file "baslodriver.c"
Xilinx Answer #3687 : M1.4 Floorplanner - ACD files changes needed for xc4000.acd, xc4000e.acd, xc4500e.acd for Floorplanner
Xilinx Answer #3690 : M1 Par or HITOP, ERROR: /usr/lib/dld.sl: Unresolved symbol: seekoff_9streambuf... libbasrw.sl running Xilinx DM through Mentor B.1-B.4
Xilinx Answer #3692 : M1.4 XC4000XV Speed Files - A Patch is available with new 40125XV speedsfiles.
Xilinx Answer #3693 : Cadence Concept, M1.4: How to LOC global buffers in Concept schematic for the XC4000 family
Xilinx Answer #3694 : V1.5, V1.4 COREGEN: Limitations on running the CORE Generator over networks on UNIX & Win95 platforms
Xilinx Answer #3695 : V1.4 COREGEN, VIEWLOGIC: "The VLLINK.BAT file has a line that is longerthan 254 characters."
Xilinx Answer #3696 : COREGen v1.4.0: COREGen overwrites files in the working or project directory without checking with the user
Xilinx Answer #3697 : COREGen v1.4.0: COREGen does not release CPU after generating a core module
Xilinx Answer #3699 : Flexlm, security, TCP/IP, modem, ISP: License server only works when ISPis connected to through a modem.
Xilinx Answer #3700 : V1.4.0 COREGEN, VIEWLOGIC: "ERROR starting PM. Missing LIBBASUT.DLL"
Xilinx Answer #3701 : Hardware Debugger: Configuring FPGA with Parallel Cable fails, Serial Cable works.
Xilinx Answer #3702 : COREGEN v1.4.0: Parameter File Information tables in the COREGen datasheets
Xilinx Answer #3704 : M1.4: Prom File Formatter uses different format for byte-wide prom sizes
Xilinx Answer #3705 : Foundation Express, XC9500: Recommended synthesis and fitter options for CPLDs
Xilinx Answer #3706 : Foundation 1.4, MAP: ERROR:basnu:93 - logical block <instance number> oftype "OBUF" is unexpanded... when OMUX2 is used in XNF netlist
Xilinx Answer #3708 : A1.4 Install: Possible problem with BASE install and Spartan
Xilinx Answer #3709 : XC4010E CB196: pin locations for the XC4010E CB196 are incorrect
Xilinx Answer #3710 : M1.4:Setting Up Dynatext Browser or OnLine Books if not installed (PC)
Xilinx Answer #3711 : Foundation F1.3/F1.4: Cannot select 4000EX/4000XL, Spartan devices whencreating new project
Xilinx Answer #3712 : Foundation F1.4: Sentinal Driver Causes Conflict with Printer Driver
Xilinx Answer #3715 : JTAG and Boundary Scan Information for FPGAs and CPLDs
Xilinx Answer #3716 : Foundation F1.4 Project Manager: Restore Project returns a blank window under Win95
Xilinx Answer #3717 : How to import Synplify's XNF netlist into the Foundation schematic?
Xilinx Answer #3719 : XABEL (DS-371) and Alliance software; workstation support
Xilinx Answer #3720 : M1.3/M1.4: Hitop hangs for 9500 design
Xilinx Answer #3721 : Foundation F1.4: Symbol references conflict assigned to same symbol
Xilinx Answer #3722 : A1.4/F1.4 Map - XC5200 combinatorial latch implemented wrong in a f5_mux.
Xilinx Answer #3723 : A1.4/F1.4 Map - Map crashes with segmentation fault for a particular case.
Xilinx Answer #3724 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3725 : A1.4/F1.4 Map - FATAL_ERROR:x4kma:x4kmamerge.c:1561:1.145.12.7 - No floprt available.
Xilinx Answer #3726 : A1.4/F1.4 MAP: Map corruption during logic replication loses HLUT connection.
Xilinx Answer #3727 : A1.4/F1.4 Bitgen - ERROR:x4kbs:18 - Tiedown failed. 2 untied nodes.
Xilinx Answer #3728 : A1.4/F1.4 EPIC - Several fixes have been added to fix EPIC crash problems.
Xilinx Answer #3729 : COREGen v1.4.0: MS-DOS box on the Windows 95 taskbar does not terminate when you exit COREGen
Xilinx Answer #3730 : M1.4 CPLD Fitter: Combinatorial logic duplicated with multilevel logic optimization
Xilinx Answer #3732 : M1.4 Hitop - hitop error: Error:rg119
Xilinx Answer #3733 : M1.4 Hitop - Optimization disregards that control signals can have only 1 pterm.
Xilinx Answer #3734 : When using Turns Engine, you are unable to nice the PARs that are spawned off
Xilinx Answer #3735 : FPGA Express: Concatenating select bits of mux causes error VSS-1029
Xilinx Answer #3737 : M1.4 Ngd2vhdl - The TOC cell created by ngd2vhdl does not contain WIDTH generic.
Xilinx Answer #3738 : M1.4 Ngd2vhdl - 2-dimensional array used in .vhd file but type not declared
Xilinx Answer #3739 : M1.4 Back Annotation - List of all software updates available for M1.4 back annotation.
Xilinx Answer #3741 : A1.4 - Problems reading Answers Book from Dynatext viewer
Xilinx Answer #3742 : A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.
Xilinx Answer #3747 : M1.3 Mentor calc_sot tutorial is missing VHDL source files
Xilinx Answer #3748 : XC9500: Generic XC9500 IBIS (I/O Buffer Information Specification) modelis on the FTP site
Xilinx Answer #3749 : M1 PAR: Multi-Pass Place and Route: The Design Score and what it means
Xilinx Answer #3753 : M1 Constraints: UCF to PCF conversion examples
Xilinx Answer #3754 : COREGen v1.4.0: Xilinx M1.4 and Viewlogic must be installed first for Viewlogic users, and Foundation must be installed for Foundation users
Xilinx Answer #3755 : XABEL, F1.4: App Note available for using XABEL with F1.4
Xilinx Answer #3756 : FSM Editor F1.4: Vhdl code synthesis errors, Enum_encoding not declared
Xilinx Answer #3757 : Map: Removes logic that is tied to pads locked to Unbonded pins.
Xilinx Answer #3760 : A1.4/F1.4 Map - FATAL_ERROR:basnc:basncsignal.c:262:1.62 - Could not find a
Xilinx Answer #3761 : A1.4/F1.4 Map - MAP introduces DRC problem: WARNING:x4kdr:82 - Blockcheck: The pin "F1"...
Xilinx Answer #3766 : MAP M1.4: x4kma:312 - The following symbols could not be constrained to a single CLB (Two F-LUT's, an H-LUT, and carry logic).
Xilinx Answer #3767 : A1.4 and Modelsim: How to use the OSC4 component with VHDL simulation (Functional and Timing)
Xilinx Answer #3770 : A1.4/F1.4 - Installation of Software Updates.
Xilinx Answer #3772 : A1.4/F1.4 Map - Map connects xc5200 readback symbol incorrectly.
Xilinx Answer #3773 : M1.4 PAR, TRCE, Timing - How to invoke the "KPATHS" timing algorithm.
Xilinx Answer #3774 : JTAG Cable cannot be used for FPGA configuration with PROG pin connected.
Xilinx Answer #3779 : SPROMs (XC1700): How to program reset polarity on Xilinx SPROMs
Xilinx Answer #3781 : FPGA Express: "XNF Bus style" checkbox in Synthesis->Options->Project defined
Xilinx Answer #3782 : Foundation F1.4: Moving pin on a logiblox symbol in Symbol Editor does not update symbol.
Xilinx Answer #3785 : COREGEN v1.4.0: Blank DOS box appears when COREGen is invoked with Windows Display set to "True Color", entire program hangs; Windows NT.
Xilinx Answer #3786 : M1.4 Map - How to produce map reports with full details.
Xilinx Answer #3787 : EZTAG/JTAG Programmer: How to create a SVF file that performs a blank check operation?
Xilinx Answer #3790 : COREGEN v1.4.0: Output Options dialog box background color is two shadesof gray instead of one uniform shade
Xilinx Answer #3791 : V1.4.0 COREGEN: After FULL indicator goes high, FIFO output changes to the first value written before READ ENABLE goes active.
Xilinx Answer #3792 : Exemplar Leonardo 4.x: How to instantiate READBACK using RDBK and RDCLK
Xilinx Answer #3794 : M1.4 PAR: FATAL_ERROR:basnd:basndutils.c:130:1.6 - Internal Error - signal has a loop
Xilinx Answer #3798 : MAP WARNING:x4kma:78 - STARTUP symbol "$I1" (output signal=<none>) conflicts with other symbol connections on the clock signal
Xilinx Answer #3799 : ngd2vhdl v1.4p ---Latest patch fixes 2-dimensional array problem and ROCpulse width
Xilinx Answer #3801 : M1.4 CPLD - A software update is available to support the new CSP48 package in the XC9000 family.
Xilinx Answer #3802 : M1.4 CPLD - Timing violation: Slow simulation model produced with the "Use Local Macrocell Feedback" switch
Xilinx Answer #3803 : M1.4 CPLD - Fitter report & timing simulation (F1.4) gives incorrect equations.
Xilinx Answer #3805 : EZTag: SVF file generation mode doesn't work when data protection optionis enabled.
Xilinx Answer #3807 : XACT-CPLD: Listing of all the Fitter patches
Xilinx Answer #3808 : EZTAG v6.x: List of various fixes available in the latest patch
Xilinx Answer #3809 : XACT-CPLD: Mentor & Cadence interface patches available for the XC9500 family
Xilinx Answer #3810 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3811 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:1333:1.69
Xilinx Answer #3812 : M1.4 PAR - Nodes list for Turns Engine doesn't accept special characters
Xilinx Answer #3813 : A1.4/F1.4 - PAR duplicates flops to create an output to output route-thru.
Xilinx Answer #3814 : A1.4/F1.4 PAR - PAR crashes during placement of XC4000XL device.
Xilinx Answer #3815 : A1.4/F1.4 Ngdanno - INTERNAL_ERROR:basnb:basnbconv.c:546:1.21
Xilinx Answer #3817 : M1.5 EPIC: How to change modes in EPIC?
Xilinx Answer #3818 : F1.4 General - Chinese, Korean and Japanese encodings corrupted by US Foundation Design Entry CD
Xilinx Answer #3819 : V1.4.0 COREGEN: CD jacket has an error in path to workstation install--/cdrom.cdrom0/install should be /cdrom/cdrom0/install
Xilinx Answer #3820 : M1.4 Concept: How to place a TIG property on a net in your schematic
Xilinx Answer #3822 : A1.4/F1.4 Map - Guided map crashes
Xilinx Answer #3824 : Leonardo 4.13/Galileo 4.11 is creating wrong logic for D latch on 4K devices using xnf format
Xilinx Answer #3825 : M1 NGDBUILD error based51: on or above line ... in design.edf, using Mentor flow
Xilinx Answer #3826 : Spartan: Are Spartan devices footprint compatible with 4000E/XL devices?
Xilinx Answer #3830 : A1.5: Cadence Concept 9604 and 97a: How to target a Spartan device
Xilinx Answer #3831 : M1.4 LOGIBLOX: MAP may convert 5K Logiblox adder CY_MUX's to FG muxes and leaves buffers in.
Xilinx Answer #3839 : COREGEN 1.4, M1.4 ngd2edif: FATAL_ERROR:baspm:baspmdlm.c:99:1.18 - dll library <vwlne> does not exist
Xilinx Answer #3840 : V1.4.0 COREGEN: How to obtain the latest COREs, software enhancements, and patches / SDA FIR Filter module available in v1.4.0p1 patch supplement
Xilinx Answer #3843 : A1.4/F1.4 Map - FATAL_ERROR:x4kmamerge.c:2858:1.145.12.11 - Too many signals to move..
Xilinx Answer #3845 : BG-432 package pinout info error
Xilinx Answer #3846 : V1.4.0 COREGEN: Tips on simulating the SDA FIR filter
Xilinx Answer #3850 : V1.4.0 COREGEN: What's new in the v1.4.0 release
Xilinx Answer #3852 : A1.5/1.4: NGD2VHDL, NGD2VER: Bus indexes are always declared in descending order within simulation netlist
Xilinx Answer #3857 : Power sequencing issue forXC3100L, XC3000L, XC4000XL and Spartan-XL : where can we find the information
Xilinx Answer #3860 : Foundation Simulator: How to fit more simulation time in one page when printing it.
Xilinx Answer #3863 : V1.4.0 COREGEN, FPGA EXPRESS: How to generate Foundation functional simulation files for a VHDL design
Xilinx Answer #3867 : M1 Timing Analyzer: No default physical constraints file "\...\map.pcf" was found.
Xilinx Answer #3868 : M1.4 Map - FATAL_ERROR:baspm:baspmdevkey.c - Unable to load file or override file "mapl2ppins.acd"
Xilinx Answer #3872 : COREGEN V1.4.0, FOUNDATION F1.3: "Invalid call to .DLL" error during netlist creation in Foundation F1.3 after installing COREGen v1.4.0
Xilinx Answer #3874 : Foundation Schematic F1.4 : Options->Replace Symbol replaces all instances of symbol
Xilinx Answer #3875 : A1.4/F1.4 Map - Map connects wrong LUT output to FFY D input
Xilinx Answer #3876 : A1.4/F1.4 5200 Map - FATAL_ERROR:baste:basteparse.c:333:1.1
Xilinx Answer #3877 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...
Xilinx Answer #3879 : A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:982:1.69.14.2 - NC_BEL ...
Xilinx Answer #3880 : A1.4/F1.4 - PC only PAR crash during placement of high density devices (>= 4085XL).
Xilinx Answer #3883 : V1.4.0 COREGEN: How to permanently set the default output format for COREGen
Xilinx Answer #3884 : V1.4.0 COREGEN, VIEWLOGIC, FOUNDATION, SYNOPSYS, EXPRESS: versions of third party CAE platforms and M1 supported by COREGEN
Xilinx Answer #3888 : M1 TRCE : How does trce list the number of timing errors?
Xilinx Answer #3889 : M1.5 EPIC: Can an Epic script be launched without invoking the GUI?
Xilinx Answer #3891 : COREGEN: What is "SystemView" from Elanix, and how can I get more information on it?
Xilinx Answer #3892 : How to start the license manager automatically at boot time (Unix workstation)?
Xilinx Answer #3895 : Foundation F1.4, Translate: Where does the &__A__ net name in my warningcome from?
Xilinx Answer #3897 : Foundation F1.4, XC95144-20: XC95144-20 device is available from Design Entry but not Implementation
Xilinx Answer #3903 : M1.4 Map - FATAL ERROR: Too many signals to move and not enough slots oncomp
Xilinx Answer #3904 : M1.5 LogiBlox introduces .ngc as new file extension for the implementation netlist
Xilinx Answer #3905 : Workstation Install: How to mount Xilinx CD-ROM on workstations
Xilinx Answer #3907 : SYNPLIFY: How to generate an .xnf compatible with Viewlogic busnaming convention?
Xilinx Answer #3908 : LOGIBLOX: Legal ranges reported by LogiBLOX for base 2 and base 4 numbers are incorrect.
Xilinx Answer #3915 : V1.4.0 COREGEN: 30-bit bus input width limit on COREGEN modules / Cannot specify 32-bit input bus widths / integer arithmetic overflow
Xilinx Answer #3923 : Aldec Active-VHDL: Key inactivates Foundation install (puts into evaluation mode)
Xilinx Answer #3927 : Design Manager/Flow Engine M1.4: Incorrect DonePin value for Bitgen (XC3000A ONLY)
Xilinx Answer #3928 : Foundation F1.4 XVHDL: Using JTAG pins (TDI, TDO, TCK, TMS) for generalI/O
Xilinx Answer #3930 : Verilog: Timing simulation: An X_FF waveform does not look correct and may be mistaken for a latch
Xilinx Answer #3931 : F1.4,docs,base,device_support: Incorrect list of supported devices in F1.4 Release Document
Xilinx Answer #3932 : Foundation F1.4 Simulator: Explanations of Functional and Timing modes in Simulator
Xilinx Answer #3933 : F1.4,M1.4,Map,license,Error: basse ... No such feature exists (-5,116)
Xilinx Answer #3934 : FlexLM,security,network: How setup floating license on dummy ethernet card?
Xilinx Answer #3935 : WEBLINX: Problems with Xilinx WebLINX or CoreLINX passwords, logging on, or registering on WebLINX
Xilinx Answer #3937 : M1.4 TSIM - ERROR:basnu:115 - logical net "b_reset" has both active and tristate drivers.
Xilinx Answer #3939 : M1.4 Map - WARNING:baspl:291 - The IOB component "io<0>" could not be placed.
Xilinx Answer #3940 : M1.4 Speed Files - New Spartan Speed Files are available.
Xilinx Answer #3946 : Foundation F1.4 Schematic Editor: 'Print all macros' command does not print correctly
Xilinx Answer #3947 : Coregen v1.4: Exemplar flow (with and without LogiBLOX) (basnb:79 - Pin mismatch, basnu:93 - Unexpanded...).
Xilinx Answer #3949 : COREGEN Registered Scaled Adder: What is the "floor()" function?
Xilinx Answer #3953 : Foundation XVHDL: mmvhdl.exe not found when synthesizing
Xilinx Answer #3965 : V1.4.0 COREGEN: COREGen may create .VHX, XNF and .XSF output files evenwhen not directed to do so
Xilinx Answer #3967 : Can you create test vectors in EZtag?
Xilinx Answer #3969 : M1.4 Bitgen - Tie fails (1 untied node)
Xilinx Answer #3970 : M1.4 Speed files - Pullup res. for x4002xl and wire segment res. for x4085 is incorrect
Xilinx Answer #3971 : M1.4 Speed Files - An M1.4 XC4000XL speed file update is available that also includes bitgen updates.
Xilinx Answer #3976 : SYNPLIFY: How to disable FMAP/HMAP mapping?
Xilinx Answer #3978 : A1.4 ngd2edif -v mentor on a PC gives FATAL_ERROR:baspm:baspmdlm.c:99:1.18 dll library <mtrne> does not exist
Xilinx Answer #3979 : How to startup Galileo Extreme from a command line with Leonardo software and license?
Xilinx Answer #3980 : FPGA Express 2.0.x: Instantiating I/O in VHDL.
Xilinx Answer #3984 : XABEL, Foundation F1.4: XABEL patch available on Web site
Xilinx Answer #3986 : Design Manager M1: The specified part is either invalid or not supported(XC95***/XL)
Xilinx Answer #3988 : M1.4/M1.5 Map - Error: x4kma:215-the component AAA is a synchronous RAM,which is not available in the xc4000 architecture
Xilinx Answer #3993 : A1.4/A1.5 XSI: What to do when insert_pads fails in FPGA Compiler
Xilinx Answer #3999 : FPGA Express 2.0.x: Instantiating I/O in Verilog.
Xilinx Answer #4005 : EPIC M1.4/M1.5: Arc x/y offset file <unknown> not found
Xilinx Answer #4006 : M1.5 EPIC: How to manually route signals
Xilinx Answer #4007 : HW-130/Third party programmers (such as DATA IO, BP): Supported file formats .mcs, .exo, .tek but not .bit
Xilinx Answer #4008 : M1.5 EPIC: EPIC vs. XDE and other useful EPIC Tidbits
Xilinx Answer #4009 : COREGEN, VHDL: where is the UL_UTILS.vhd library for behavioral simulation
Xilinx Answer #4017 : COREGEN: What is SystemLINX?
Xilinx Answer #4024 : DESIGN MANAGER/LOGIBLOX/etc... M1.5 versions of XILINX GUI-based programs issue an error about an old version of the windu_registryd program (WS ONLY)
Xilinx Answer #4026 : M1.4 Map - ERROR:x4kma:387 - Unable to obey design constraints which require the combination of the following symbols into a single CLB:
Xilinx Answer #4029 : 98 DATABOOK: Does Xilinx have XC4028EX or X4036EX parts in -1 Speed grade?
Xilinx Answer #4031 : M1.4 General - XC4000XL speed file upgrade adds -08 speed grade for 4013XL, 4036XL and 4062XL.
Xilinx Answer #4034 : SYNPLIFY: Conditions of "Force GSR Usuage" - to generate the STARTUP block?
Xilinx Answer #4038 : SYNPLIFY: How to change the colors used in HDL Analyst?
Xilinx Answer #4048 : M1.4 Fitter/Hitop - Incorrect logic generated.
Xilinx Answer #4051 : M1.4 CPLD: FPGA-EXPRESS - VHDL, Input to toggle control of FF inverted instead of the output.
Xilinx Answer #4056 : SPROMS: XC1700E/EL are the replacements for the XC1700D/L
Xilinx Answer #4060 : M1.4 Map - Map creates TIMEGRPs in PCF file that are incorrect.
Xilinx Answer #4061 : M1.4 Map - Unable to RLOC tbufs to column 0: ERROR:baste:117 - RLOC_ORIGIN value ...
Xilinx Answer #4064 : Design Manager M1.4/M1.5: What command line options can be used to invoke the Design Manager ?
Xilinx Answer #4065 : M1 NGDBUILD/CSTTRANS: Why INST can sometimes be used instead on NET for Pad LOCs
Xilinx Answer #4067 : M1.4 EPLD-FIT (1.4): Dr. Watson for Windows NT: hitop.exe
Xilinx Answer #4072 : M1.4: WARNING:x4edr:21 - Blockcheck: CLB "frfi3_alism_fiCtr_upDown" is configured to use the G LUT as RAM, but the D1 and WE lines use the same pin, wh ich will likely cause a D->WE setup violation.
Xilinx Answer #4074 : M1.4 PAR - DRC incorrectly posts warning about DPRAM D1 pin when it is unused.
Xilinx Answer #4081 : Map 1.4:FATAL_ERROR:x4kma:x4kmaclkinfo.c:786:1.24 - Clkinfo: sitearray overrun: page1$1p/page1$i135.
Xilinx Answer #4086 : A1.5: Cadence PE 13.x Concept-HDL will not be supported until the next Xilinx software release after A1.5
Xilinx Answer #4088 : M1.4 XC4000XV - Package File Update adds BG432 package to the XC40125XV device.
Xilinx Answer #4089 : How to simulate Exemplar written VHDL in MTI or QuickHDL. Post synthesispre NGDBuild
Xilinx Answer #4090 : ERROR:time_sim.vhd(132):Cannot assign to object with mode IN:ce. MTI timing simulation
Xilinx Answer #4091 : Using Exemplar Leonardo with Virtex what Modgen library do I load?
Xilinx Answer #4099 : V1.4.0 COREGEN, VF1.3 Foundation: "Call to Undefined Dynalink"
Xilinx Answer #4100 : M1.5 9500/XL FITTER/HITOP: PROHIBIT property does not exclude pins from "Programmable Ground Pins" option
Xilinx Answer #4101 : M1.5 9500/XL: (basts:158) Incorrect Warnings - CPLD Fitter does not support the TNM_NET property
Xilinx Answer #4109 : V1.4.0 COREGEN, Install, French Windows95: "a file .dll required, MSVCRT.DLL has not been found"
Xilinx Answer #4112 : M1.4 Map - FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No route-thru available in pack_lutflop() to swap with H input pin 8:
Xilinx Answer #4116 : JTAG/Parallel Cable III: Cable will accept 5V or 3V as power supply.
Xilinx Answer #4117 : Mentor, pld_edif2tim: error line 2 illegal identifier "15 encountered from synthesis
Xilinx Answer #4131 : Design Manager M1.5: New version is created instead of new revision eventhough the input design netlist has not changed
Xilinx Answer #4137 : Design Manager M1.5: Multi-pass place and route (MPPR) naming conventionhas changed (ex - p1_rev_2_3_4)
Xilinx Answer #4141 : Orcad Express: Using TIMESPEC to set global attributes in Xilinx
Xilinx Answer #4146 : M1.4/M1.5 Map - FATAL_ERROR:x4kma:x4kmaaclk.c:145:1.16.12.2 - More than one driver on clock net.
Xilinx Answer #4147 : Design Manager/Template Manager M1.5: Cannot delete the program/option within Template Manager
Xilinx Answer #4151 : V1.5 COREGEN: Can V1.5 be installed over the V1.4 release?
Xilinx Answer #4156 : M1.5: Timing analysis doesn't use TPTHRU as more specific than FROM:TO
Xilinx Answer #4161 : M1.5: Cannot TIMESPEC the TDO pin on XC4000E/X FPGAs.
Xilinx Answer #4164 : V1.5, V1.4 COREGEN, HP: Folder icons are not displayed when COREGEN is invoked on an HP and GUI is displayed on Solaris
Xilinx Answer #4166 : V1.5 COREGEN: What's new in the v1.5 release
Xilinx Answer #4169 : V1.5 COREGEN: Datasheets only viewable when COREGEN is invoked from the Acrobat install directory after installing Acrobat to "."
Xilinx Answer #4173 : M1.5 9500XL Fitter/Library: Clock-enable p-term not used for FDPE in Cadence and Mentor schematics.
Xilinx Answer #4174 : M1.5 9500/XL: Fitter uses 2 macrocells instead of 1 for combinatorial latch
Xilinx Answer #4175 : M1.5 9500/XL Fitter: T-flops get transformed into D-flops
Xilinx Answer #4176 : M1.5 9500/XL Fitter/Report: Unbonded device pins marked as "TIE" or "PGND" instead of "NC"
Xilinx Answer #4181 : M1/Exemplar: How to instantiate Logiblox modules