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Xilinx Answer #8207 : EXEMPLAR: How to instantiate LUT primitives in HDL for Virtex?
Xilinx Answer #8074 : EXEMPLAR 1999.1x: How to force I/O standards onto ports
Xilinx Answer #7947 : EXEMPLAR: How to instantiate and initialize Virtex Select BlockRAM?
Xilinx Answer #7929 : EXEMPLAR:How to infer Virtex Block RAM in HDL? (Verilog/VHDL)
Xilinx Answer #7822 : How to infer SRL16 for Virtex/E devices in HDL (Verilog/VHDL)? (in EXEMPLAR and SYNPLIFY)
Xilinx Answer #7087 : Exemplar Leonardo Spectrum v1999.1c: ngdhelpers:312 - logical block of type GND is unexpanded
Xilinx Answer #6899 : Exemplar: How to lock pins in the Spectrum GUI, in the VHDL code, or in a Tcl script.
Xilinx Answer #6841 : Exemplar Spectrum 1998.2 is connecting GSR on an instantiated OFDT to common Ground causing some trimming.
Xilinx Answer #6840 : Exemplar Spectrum 1998.2 is not inferring Xilinx Virtex flip flops with both synchronous set and reset
Xilinx Answer #6433 : Exemplar: My instantiated Xilinx component is getting removed by synthesis (Optimize)
Xilinx Answer #5681 : Exemplar: After upgrading from Spectrum 1998.2d build 5.94 to 1998.2d build 5.103 my project now targets Spartan where the saved project was targeting Virtex?
Xilinx Answer #5678 : Exemplar Spectrum: Read gives :hdl_file.v", line 14: Error, Empty port is not supported
Xilinx Answer #5346 : Exemplar: How to infer STARTUP, using the infer_gsr command.
Xilinx Answer #5280 : Exemplar: Spectrum synthesis is giving me warning component ... has no visible entity binding
Xilinx Answer #5192 : Exemplar: After optimization Spectrum changes my instantiated BUFGDLL to a BUFGP
Xilinx Answer #4512 : Exemplar:Tips on how to use blackbox EDIF and XNF netlists in HDL. (Coregen)
Xilinx Answer #4488 : Exemplar: How to Preset or initialize a flop to a '1', on powerup only, FPGA's
Xilinx Answer #4331 : Exemplar: How to force some outputs FAST and some SLOW
Xilinx Answer #4330 : Exemplar: How to force a clock signal to use an IBUF instead of the tools insert of BUFG
Xilinx Answer #4329 : Examplar: How to get a listing of the components and port for a given technology.
Xilinx Answer #4328 : Exemplar: How to initialize RAM or ROM in VHDL code
Xilinx Answer #4244 : Leonardo: How to change the slew rate from Leonardo.(Fast, Nodelay)
Xilinx Answer #3979 : How to startup Galileo Extreme from a command line with Leonardo software and license?
Xilinx Answer #3792 : Exemplar Leonardo 4.x: How to instantiate READBACK using RDBK and RDCLK
Xilinx Answer #3377 : EXEMPLAR: Instantiating a pulldown/pullup in Verilog?
Xilinx Answer #2517 : Exemplar: How to instantiate a pullup or pulldown (Galileo and Leonardo) in VHDL
Xilinx Answer #2516 : Exemplar Galileo/Leonardo EDIF files prior to version 4.1.3 are not M1 compatible
Xilinx Answer #1975 : How to lock down I/O pins in Exemplar