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Xilinx Answer #4532 : 5200 power dissipation: What is the K factor for 5200?
Xilinx Answer #3284 : XC5200: Power on delay of 4mS is too fast for power supplies
Xilinx Answer #2858 : XC5200: Speed files are now available on the web
Xilinx Answer #2645 : FPGA Configuration: INIT goes low unrelated to frame error.
Xilinx Answer #2502 : XC5200: 5206- Incorrect pinouts for any parts with daycode earlier than 9620
Xilinx Answer #2423 : XC5200: What is the delay setting for the IOB when driving logic instead registers?
Xilinx Answer #2196 : 5200: Readback with xchecker on 5202 devices
Xilinx Answer #2017 : FPGA Configuration: Difference between the preamble/length count of XC4000/E/EX and the XC5200
Xilinx Answer #1925 : XC5200: XACT 5.2.1- xnfprep: Error 4708
Xilinx Answer #1560 : FPGA Configuration: Express Mode requires CRC disabled or INIT will go LOW.
Xilinx Answer #1399 : XC5200: Recommended maximum sink and source currents
Xilinx Answer #1359 : JTAG - Pullup and pulldown availability on 5200 TDO
Xilinx Answer #1305 : XC5200: BUFG - different skew between clock pin and non clock pin.
Xilinx Answer #1112 : XC5200: Typo reads "50-kW to 100-kW pull-up resistor" in 'The Programmable Logic Data Book', 7/96
Xilinx Answer #1111 : XC5200: Dynamic power consumption values (most up-to-date)
Xilinx Answer #1017 : Designing with the XC5200 family using synthesis
Xilinx Answer #992 : XC5200 JTAG - Sample/Preload in a XC5200 appears to work like BYPASS
Xilinx Answer #949 : XC5200: Slew rates (RISE and FALL times) for outputs with a 50 pF load
Xilinx Answer #921 : FLOORPLANNER-XACT: Unable to load fplan.pm occurs when opening the Floorplanner.
Xilinx Answer #885 : FPGA Configuration: Express Mode Bitstream loaded to the same pins as Peripheral Download.
Xilinx Answer #819 : XC5200: Dedicated GCLK pins for I/O when using BUFGP
Xilinx Answer #774 : XC5200: Mode pins M0, M1, M2 are bidirectional, but library MD0, MD1, MD2 are unidirectional.
Xilinx Answer #633 : XC5200: How to shut off the internal oscillator