Boundary Scan/JTAG: Tips and Techniques

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Boundary Scan in XC4000/XC5200

Solution 940: How to configure the XC4K/XC5K devices via Boundary Scan
Solution 941: How to do consecutive READBACKS in XC4K/XC5K devices
Solution 992: SAMPLE/PRELOAD instruction in XC5200 appears to work like BYPASS
Solution 993: Boundary Scan Instructions not available in XC4K/XC5K if the /PROG pin is held low
Solution 194: How to use the EXTEST instruction in XC4K/XC5K devices before configuration
Solution 1356: Can the TDO pin be used as a user output and an output of the TAP
Solution 1358: How to attach a Pullup/Pulldown on the XC4K TDO pin
Solution 1359: Pullup/Pulldown availability on the XC5K TDO pin
Solution 1220: How to turn on the JTAG circuitry in XC4K/XC5K devices using XDE or EPIC
Solution 239: How to prevent the inadvertent activation of Boundary Scan in XC4K devices
Solution 1362: How to instantiate the BSCAN symbol in Foundation XVHDL
Solution 1966: How to instantiate the BSCAN symbol and Mode pins in Viewsynthesis
Solution 3074: How to do functional simulation in Cadence Concept and Verilog-XL with Mode and Boundary Scan pins in schematic
Solution 488: How to instantiate the BSCAN symbol in Synopsys (FPGA Compiler, Design Compiler, FPGA Express)

Boundary Scan in XC9500

XC9500 hardware

Solution 1408: What should be done with the unused JTAG TAP pins of the XC9500 device

Using EZTAG/JTAG Programmer Software

Using Serial Vector Format (SVF) files with XC9500

Boundary Scan with XC4K/XC5K/XC9K and non-Xilinx parts

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