/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
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/* */
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/* foreign patents, or pending applications. */
/* */
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/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)hold_control.v
***
***
****************************************************************************
****************************************************************************/
/*
@(#)hold_control.v 1.30 8/7/93
Split out hold control for better placement and synopsys
*/
module Mhold_control
(
FHOLD,
ER_SDOUT,
ss_clock,
ss_scan_mode,
dwait_w,
dt_hit_w,
dc_shold,
enbl_dtag_match_w,
enbl_itag_match_f,
iwait_f,
it_hit_f,
force_ifill,
flush_ic_e,
reset,
w_hhn_2,
w_op,
w_op3_5,
w_op3_3,
w_op3_2,
w_op3_0,
stop_fetch,
ic_idle,
mm_icache_enbl,
hold,
pipe_hold4fpc,
pipe_hold4fprf,
pipe_hold4mmu_cntl,
pipe_hold4mmu_dp,
pipe_hold4dc,
pipe_hold4dc_l,
pipe_hold4ic,
hold_Mexec1,
hold_Mexec2,
hold_Mexec3,
hold_Mdecode,
hold_Mregfile,
hold_noic,
hold_ic,
fast_hld_terms,
ihold_d1,
dhold_d1,
// extend_tag_miss,
enbl_fetch,
Mhold_control_scan_in,
Mhold_control_scan_out
);
input FHOLD
;
input ER_SDOUT
;
input ss_clock
;
input ss_scan_mode
;
input dwait_w
;
input dt_hit_w
;
input dc_shold
;
input enbl_dtag_match_w
;
input enbl_itag_match_f
;
input iwait_f
;
input it_hit_f
;
input force_ifill
;
input flush_ic_e
;
input reset
;
input w_hhn_2
;
input [1:0] w_op
;
input w_op3_5
;
input w_op3_3
;
input w_op3_2
;
input w_op3_0
;
input ic_idle
;
input mm_icache_enbl
;
input stop_fetch
;
output hold
;
output [2:0] pipe_hold4fpc
;
output pipe_hold4fprf
;
output pipe_hold4mmu_cntl
;
output pipe_hold4mmu_dp
;
output pipe_hold4dc
;
output [1:0] pipe_hold4dc_l
;
output pipe_hold4ic
;
output hold_Mexec1
;
output hold_Mexec2
;
output hold_Mexec3
;
output hold_Mdecode
;
output hold_Mregfile
;
output hold_noic
;
output hold_ic
;
output fast_hld_terms
;
output ihold_d1
;
output dhold_d1
;
//output extend_tag_miss;
output enbl_fetch
;
input Mhold_control_scan_in
;
output Mhold_control_scan_out
;
// bits 4 and 1 of w_op3 are not used. Tied to zero.
wire [5:0] w_op3
=
{w_op3_5, 1'b0, w_op3_3, w_op3_2, 1'b0, w_op3_0};
wire [8:0] w_hop3
= {w_hhn_2, w_op, w_op3};
wire [2:0] w_hop
= {w_hhn_2, w_op}; // w_hop3[8:6];
wire enbl_fetch;
// Data Cache hold
// Must hold during dmhold if
// memop in W
// SWAP or LDST in R (it caused the miss)
wire memop_in_w
= w_hop==`MEMALL;
wire w_atomic_op
=
( w_hop3 == `SWAP | w_hop3 == `SWAPA
| w_hop3 == `LDSTB | w_hop3 == `LDSTBA )
;
wire r_atomic_op
;
Mflipflop_1 raop_reg_1(r_atomic_op,w_atomic_op,ss_clock,hold) ;
wire dmiss_line
=
enbl_dtag_match_w & ~dt_hit_w
& (memop_in_w | r_atomic_op)
;
wire dml_t1
= enbl_dtag_match_w & (memop_in_w | r_atomic_op);
// new hold logic for I$
wire imiss_line
=
~it_hit_f
& (enbl_itag_match_f & ~reset & enbl_fetch); // & iu_fetch_f)
wire iml_t1
= enbl_itag_match_f & ~reset & enbl_fetch;
// wire extend_tag_miss;
// modification to iwait_f - move this term for I$ to IU
wire enable_ic
;
Mflipflop_1 enable_ic_reg_1(enable_ic,mm_icache_enbl,ss_clock,1'b0) ;
wire new_iwait_f_term
=
ic_idle & enbl_fetch & ~enable_ic
| force_ifill & flush_ic_e
;
wire iwait_f_iu
= iwait_f | new_iwait_f_term;
wire hold_term1
= ~reset & (
dc_shold
| FHOLD
| iwait_f_iu // & iu_fetch_f
| dwait_w
// | extend_tag_miss
)
;
wire fast_hld_terms = hold_term1;
// assign hold =
// (dmiss_line | imiss_line | hold_term1)
// ;
wire it_hit_f_l
= ~it_hit_f;
wire dt_hit_w_l
= ~dt_hit_w;
JDB122A arthur_hc_g1 ( .A1(it_hit_f_l), .A2(iml_t1),
.B1(dt_hit_w_l), .B2(dml_t1), .C(hold_term1), .O(hold1
) );
JDB122A arthur_hc_g2 ( .A1(it_hit_f_l), .A2(iml_t1),
.B1(dt_hit_w_l), .B2(dml_t1), .C(hold_term1), .O(hold2
) );
JDB122A arthur_hc_g3 ( .A1(it_hit_f_l), .A2(iml_t1),
.B1(dt_hit_w_l), .B2(dml_t1), .C(hold_term1), .O(hold3
) );
JDB122A arthur_hc_g4 ( .A1(it_hit_f_l), .A2(iml_t1),
.B1(dt_hit_w_l), .B2(dml_t1), .C(hold_term1), .O(hold4
) );
JDB122A arthur_hc_g5 ( .A1(it_hit_f_l), .A2(iml_t1),
.B1(dt_hit_w_l), .B2(dml_t1), .C(hold_term1), .O(hold5
) );
JDB122A arthur_hc_g6 ( .A1(it_hit_f_l), .A2(iml_t1),
.B1(dt_hit_w_l), .B2(dml_t1), .C(hold_term1), .O(hold6
) );
wire hold = hold2;
wire [2:0] pipe_hold4fpc;
JBUFD arthur_hc_b1 ( .A(hold5), .O(pipe_hold4fpc[0]) );
assign pipe_hold4fpc[1] = pipe_hold4fpc[0];
assign pipe_hold4fpc[2] = pipe_hold4fpc[0];
wire pipe_hold4fprf = hold2;
wire pipe_hold4mmu_cntl = hold2;
wire pipe_hold4mmu_dp = hold2;
JBUFD arthur_hc_b5 ( .A(hold3), .O(pipe_hold4dc) );
// wire pipe_hold4dc = hold2;
wire [1:0] pipe_hold4dc_l;
JINVD arthur_hc_i1 ( .A(hold4), .O(pipe_hold4dc_l[0]) );
assign pipe_hold4dc_l[1] = pipe_hold4dc_l[0];
wire pipe_hold4ic = hold2;
JBUFD arthur_hc_b2 ( .A(hold6), .O(hold_Mexec1) );
JBUFD arthur_hc_b3 ( .A(hold1), .O(hold_Mexec2) );
JBUFD arthur_hc_b4 ( .A(hold1), .O(hold_Mexec3) );
wire hold_Mdecode = hold;
wire hold_Mregfile = hold;
wire hold_noic = dmiss_line | dwait_w | dc_shold | FHOLD;
wire hold_ic =
iwait_f_iu // & iu_fetch_f & ~reset
| imiss_line
// | extend_tag_miss
;
// this reg is in here to tell the MMU when the IU is
// being held by the I$. this is for performance
// counters. the following one is for D$ holds except
// for dc_shold
wire ihold_d1;
Mflipflop_1 ihold_d1_reg_1(ihold_d1,hold_ic,ss_clock,1'b0) ;
wire dc_holds
= dwait_w | dmiss_line;
wire dhold_d1;
Mflipflop_1 dhold_d1_reg_1(dhold_d1,dc_holds,ss_clock,1'b0) ;
/*
REGWIRE tag_hld_fb;
wire ntag_hld_fb =
extend_tag_miss
| imiss_line & ~iwait_f // & ~imiss_in_progress
;
REG(tag_hld_fb_reg,1,tag_hld_fb,ntag_hld_fb,ss_clock,1'b0)
assign extend_tag_miss =
~(iwait_f | enbl_fetch & imiss_line)
& tag_hld_fb & ~reset
;
*/
// logic for enable fetch
wire tagmiss
= imiss_line & ~iwait_f_iu & enbl_fetch;
wire post_tagmiss
;
Mflipflop_1 post_tagmiss_reg_1(post_tagmiss,tagmiss,ss_clock,1'b0) ;
assign enbl_fetch = ~reset & ~post_tagmiss & ~stop_fetch & ~ER_SDOUT;
endmodule
This page: |
Created: | Thu Aug 19 11:56:50 1999 |
| From: |
../../../sparc_v8/ssparc/iu/Mhold_control/rtl/hold_control.v
|