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Xilinx Answer #8601 : 2.1i 9500 Family Hitop: hi811 - Cannot assign Fastclock Pin D2_PAD to Pin 40 (FB1_1).
Xilinx Answer #8599 : 2.1WP5.1 (WebPACK): Where are the original and 3.3V enhanced part selections for the XPLA Fitter and ISP Programmer? (XCR3032, XCR3064, XCR3128, XCR3064A, XCR3128A)
Xilinx Answer #8519 : 2.1i 9500/XL Hitop: ERROR:CPLDFitter - NGD2NDS failed. The NDS network is not created due to errors
Xilinx Answer #8258 : 2.1i : 9500 : Hitop : WARNING: CPLDFitter- The property SLOW set on the instance "<inst>" conflicts with the previous setting FAST.
Xilinx Answer #8245 : 2.1i : 9500 : Hprep6 : Inverted global tristates do not tristate properly
Xilinx Answer #8109 : 2.1i 9500/XL TAEngine : program abnormally terminated
Xilinx Answer #8095 : 2.1i 9500/XL Hitop: Designs that fit in 1.5x do not fit in 2.1i
Xilinx Answer #7948 : 2.1i 9500/xl Tsim- Timing model incorrect for negative edge triggered global clock signals
Xilinx Answer #7760 : 2.1i Hitop - Hitop (CPLD Fitter) uses SLOW slew when routing internal BUFG net through GTS pin
Xilinx Answer #7457 : 2.1i 9500/XL Hitop : "Warning NL_PRIMPIN has no net name. The pin is ignored."
Xilinx Answer #7438 : OrCad Express v9.x does not interface correctly with Xilinx A2.1 tools for XC9500 CPLDs
Xilinx Answer #7337 : 2.1i 9500/XL: Hitop (CPLD Fitter) not fitting DFF--> INV --> OBUF correctly
Xilinx Answer #7314 : 2.1i 9500/XL Hitop - Incorrect implementation of a <function> = VCC
Xilinx Answer #7234 : 2.1i Hitop: - 9500XL Fitter report shows GND and NC as TIE on XC95288XL-BG256
Xilinx Answer #6683 : 2.1i 9500XL Hitop - Fitting Report shows VCCIO pins as TIE on XC95288XL-BG256
Xilinx Answer #6645 : CPLD Fitter 2.1i: Access violation error when using a test vector file for xc95288xl BG256.
Xilinx Answer #6640 : 2.1i: Hitop: hi429 - Cannot apply TIMESPEC on what seems to be a valid signal
Xilinx Answer #5999 : 2.1i CPLD Fitter: Global Offset in 9500 is ignored
Xilinx Answer #5111 : F1.5i/2.1i: Taengine produces Timing report with no data - too many paths to trace
Xilinx Answer #4093 : 2.1i: 9500/XL: What does TIE and PGND mean in the fitter report?