Welcome v7.0
Quick start
About Libero IDE v6.3
Getting and Using Help
Project Management
Design Constraints Guide
Design Creation / Verification
Design Implementation
Welcome to Designer
Starting Designer
Getting Started
Device Selection
Importing Files
Compile
Assigning Design Constraints
Layout
Performing Analysis
Back-Annotation
Generating Reports
Exporting Files
Saving and Exiting
Designer Reference
Tool Guides
Tool Guide Summary
Fusion, ProASIC3E, ProASIC3, ProASICPLUS, ProASIC, SX-A, RTSX-S, eX
Axcelerator (including RTAX-S)
MultiView Navigator (MVN)
SmartPower
SmartTime
About SmartTime
SmartTime features
Architecture support
Design flows with SmartTime
Static timing analysis
Delay models
Timing path types
Maximum clock frequency
Setup check
Arrival time, required time, and slack
Timing exceptions
Clock skew
SmartTime Tutorial
Using SmartTime
Constraining your design
Analyzing timing in your design
Performing advanced timing analysis
Generating reports
Reference
Dialog Boxes
Menus, Toolbars, and Shortcut keys
Tcl commands
timer_add_clock_exception
timer_add_pass
timer_add_stop
timer_commit
timer_get_clock_actuals
timer_get_clock_constraints
timer_get_maxdelay
timer_get_path
timer_get_path_constraints
timer_remove_all_constraints
timer_remove_clock_exception
timer_remove_pass
timer_remove_stop
timer_restore
timer_set_maxdelay
timer_setenv_clock_freq
timer_setenv_clock_period
report (Timing) using SmartTime
report (Timing violations) using SmartTime
Error and warning messages
Glossary
SX, MX, DX, ACT3, ACT2, ACT1
Tcl Scripting
Device Programming
Saving and Exiting Libero
Contacting Actel
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