IOCAM_LINE tag09(hit[09],err[09],m_ok[09],tag09_out,
                c_data_in_reg,tg_stb_clk,tag_hld[09],flush_real,co_in_real) ;
IOCAM_LINE tag10(hit[10],err[10],m_ok[10],tag10_out,
                c_data_in_reg,tg_stb_clk,tag_hld[10],flush_real,co_in_real) ;
IOCAM_LINE tag11(hit[11],err[11],m_ok[11],tag11_out,
                c_data_in_reg,tg_stb_clk,tag_hld[11],flush_real,co_in_real) ;
IOCAM_LINE tag12(hit[12],err[12],m_ok[12],tag12_out,
                c_data_in_reg,tg_stb_clk,tag_hld[12],flush_real,co_in_real) ;
IOCAM_LINE tag13(hit[13],err[13],m_ok[13],tag13_out,
                c_data_in_reg,tg_stb_clk,tag_hld[13],flush_real,co_in_real) ;
IOCAM_LINE tag14(hit[14],err[14],m_ok[14],tag14_out,
                c_data_in_reg,tg_stb_clk,tag_hld[14],flush_real,co_in_real) ;
IOCAM_LINE tag15(hit[15],err[15],m_ok[15],tag15_out,
                c_data_in_reg,tg_stb_clk,tag_hld[15],flush_real,co_in_real) ;
 

/****** start to generate tlb_tag output ******/

/********* LEVEL 1 MUX ***************/

wire [41:0] tag12_15_out ;
IOCMUX4W CMUX4W13(tag12_out,tag13_out,tag14_out,tag15_out,addr_reg[1:0],tag12_15_out);
wire [41:0] tag08_11_out ;
IOCMUX4W CMUX4W14(tag08_out,tag09_out,tag10_out,tag11_out,addr_reg[1:0],tag08_11_out);
wire [41:0] tag04_07_out ;
IOCMUX4W CMUX4W15(tag04_out,tag05_out,tag06_out,tag07_out,addr_reg[1:0],tag04_07_out);
wire [41:0] tag00_03_out ;
IOCMUX4W CMUX4W16(tag00_out,tag01_out,tag02_out,tag03_out,addr_reg[1:0],tag00_03_out);

/********* LEVEL 2 MUX ***************/


wire [41:0] tag00_15_out ;
IOCMUX4W CMUX4W20(tag00_03_out,tag04_07_out,tag08_11_out,tag12_15_out,addr_reg[3:2],tag00_15_out);


assign tlb_tag = tag00_15_out;


/*** Decode address into separate hold lines ********************************/
     assign tag_hld = {
                        (tlb_write_op & (addr_reg == 4'hf)),
                        (tlb_write_op & (addr_reg == 4'he)),
                        (tlb_write_op & (addr_reg == 4'hd)),
                        (tlb_write_op & (addr_reg == 4'hc)),
                        (tlb_write_op & (addr_reg == 4'hb)),
                        (tlb_write_op & (addr_reg == 4'ha)),
                        (tlb_write_op & (addr_reg == 4'h9)),
                        (tlb_write_op & (addr_reg == 4'h8)),
                        (tlb_write_op & (addr_reg == 4'h7)),
                        (tlb_write_op & (addr_reg == 4'h6)),
                        (tlb_write_op & (addr_reg == 4'h5)),
                        (tlb_write_op & (addr_reg == 4'h4)),
                        (tlb_write_op & (addr_reg == 4'h3)),
                        (tlb_write_op & (addr_reg == 4'h2)),
                        (tlb_write_op & (addr_reg == 4'h1)),
                        (tlb_write_op & (addr_reg == 4'h0)) } ;


endmodule

 
/**************************************************************************/
// no reset input anymore
// reverse scan order of mflipflop_sr_6 


module IOMflipflop_s_4_r (out, din, scanen, sin, clock) ;
output [3:0] out ;
input [3:0]  din ;
input   scanen ;
input   sin ;
input   clock ;

        Mflipflop_s Mflipflop_s_4_0 (out[0], din[0], scanen, sin,  clock);
        Mflipflop_s Mflipflop_s_4_1 (out[1], din[1], scanen, out[0], clock);
        Mflipflop_s Mflipflop_s_4_2 (out[2], din[2], scanen, out[1], clock);
        Mflipflop_s Mflipflop_s_4_3 (out[3], din[3], scanen, out[2], clock);

endmodule

// reverse order of scan chain of sr_28 from 0 -> 27


module IOMflipflop_s_28_r (out, din, scanen, sin,  clock) ;
output [27:0] out ;
input [27:0]  din ;
input   scanen ;
input   sin ;
input   clock ;

        Mflipflop_s Mflipflop_s_27_0 (out[0], din[0], scanen, sin, clock);
        Mflipflop_s Mflipflop_s_27_1 (out[1], din[1], scanen, out[0], clock);
        Mflipflop_s Mflipflop_s_27_2 (out[2], din[2], scanen, out[1], clock);
        Mflipflop_s Mflipflop_s_27_3 (out[3], din[3], scanen, out[2], clock);
        Mflipflop_s Mflipflop_s_27_4 (out[4], din[4], scanen, out[3], clock);
        Mflipflop_s Mflipflop_s_27_5 (out[5], din[5], scanen, out[4], clock);
        Mflipflop_s Mflipflop_s_27_6 (out[6], din[6], scanen, out[5], clock);
        Mflipflop_s Mflipflop_s_27_7 (out[7], din[7], scanen, out[6], clock);
        Mflipflop_s Mflipflop_s_27_8 (out[8], din[8], scanen, out[7], clock);
        Mflipflop_s Mflipflop_s_27_9 (out[9], din[9], scanen, out[8], clock);
        Mflipflop_s Mflipflop_s_27_10 (out[10], din[10], scanen, out[9], clock);
        Mflipflop_s Mflipflop_s_27_11 (out[11], din[11], scanen, out[10], clock);
        Mflipflop_s Mflipflop_s_27_12 (out[12], din[12], scanen, out[11], clock);
        Mflipflop_s Mflipflop_s_27_13 (out[13], din[13], scanen, out[12], clock);
        Mflipflop_s Mflipflop_s_27_14 (out[14], din[14], scanen, out[13], clock);
        Mflipflop_s Mflipflop_s_27_15 (out[15], din[15], scanen, out[14], clock);
        Mflipflop_s Mflipflop_s_27_16 (out[16], din[16], scanen, out[15], clock);
        Mflipflop_s Mflipflop_s_27_17 (out[17], din[17], scanen, out[16], clock);
        Mflipflop_s Mflipflop_s_27_18 (out[18], din[18], scanen, out[17], clock);
        Mflipflop_s Mflipflop_s_27_19 (out[19], din[19], scanen, out[18], clock);
        Mflipflop_s Mflipflop_s_27_20 (out[20], din[20], scanen, out[19], clock);
        Mflipflop_s Mflipflop_s_27_21 (out[21], din[21], scanen, out[20], clock);
        Mflipflop_s Mflipflop_s_27_22 (out[22], din[22], scanen, out[21], clock);
        Mflipflop_s Mflipflop_s_27_23 (out[23], din[23], scanen, out[22], clock);
        Mflipflop_s Mflipflop_s_27_24 (out[24], din[24], scanen, out[23], clock);
        Mflipflop_s Mflipflop_s_27_25 (out[25], din[25], scanen, out[24], clock);
        Mflipflop_s Mflipflop_s_27_26 (out[26], din[26], scanen, out[25], clock);
        Mflipflop_s Mflipflop_s_27_27 (out[27], din[27], scanen, out[26], clock);
 
endmodule

/****************************************************************************/
/*** TLB CAM instantiation                                                ***/
/***    define CAM_LINE module                                            ***/
/***    Call IOCAM_LINE model 16 times                                      ***/
/****************************************************************************/

module IOCAM_LINE(hit,err,m_ok,tag_out,tag_in,clk,hold,flush,co_in);
output  hit;
output  err;
output  m_ok;
output [41:0] tag_out;
 
input   [41:0] tag_in;
input   clk;
input   hold;
input   flush;
input   co_in;

wire valid_in = tag_in[41] ;
wire lvl0_in = tag_in[40] ;
wire [7:0] indx0_in = tag_in[39:32] ;
wire lvl1_in = tag_in[31] ;
wire [5:0] indx1_in = tag_in[30:25] ;
wire lvl2_in = tag_in[24] ;
wire [5:0] indx2_in = tag_in[23:18] ;
wire [7:0] cntxt_in = tag_in[17:10] ;
wire [5:0] prtct_in = tag_in[09:04] ;
wire sprvsr_in = tag_in[03] ;
wire iopte_in = tag_in[02] ;
wire ptp_in = tag_in[01] ;
wire mbit_in = tag_in[00] ;
 
//wire reset = (hit & flush) | co_in ;
wire reset = (hit & flush);
 
wire valid ;
MflipflopR_1 cam_line_v_1(valid,tag_in[41],clk,~hold,reset) ;
 
// hardcode to non-scan register 
wire [40:0] tag_reg ;
//wire [40:0] tag_real_in = tag_in[40:0];
Mflipflop_h_32 cam_line_0_31(tag_reg[31:0],tag_in[31:0],~hold,~clk) ;
Mflipflop_h_9 cam_line_32_40(tag_reg[40:32],tag_in[40:32],~hold,~clk) ;

 
assign tag_out = {valid,tag_reg} ;
wire lvl0 = tag_reg[40] ;
wire [7:0] indx0 = tag_reg[39:32] ;
wire lvl1 = tag_reg[31] ;
wire [5:0] indx1 = tag_reg[30:25] ;
wire lvl2 = tag_reg[24] ;
wire [5:0] indx2 = tag_reg[23:18] ;
wire [7:0] cntxt = tag_reg[17:10] ;
wire [5:0] prtct = tag_reg[09:04] ;
wire sprvsr = tag_reg[03] ;
wire iopte = tag_reg[02] ;
wire ptp = tag_reg[01] ;
wire mbit = tag_reg[00] ;
 

 
 
wire hit_lvl02 = ( |indx0_in === 1'bx) & 
		(~(lvl1_in === 1'b0) | ~(lvl2_in === 1'b0) | ~(sprvsr_in === 1'b0));
wire hit_lvl12 = ( |indx1_in === 1'bx) & 
		(~(lvl0_in === 1'b0) | ~(lvl2_in === 1'b0) | ~(sprvsr_in === 1'b0));
wire hit_lvl22 = ( |indx2_in === 1'bx) & 
		(~(lvl0_in === 1'b0) | ~(lvl1_in === 1'b0) | ~(sprvsr_in === 1'b0));
wire hit_cntxt2 = ( |cntxt_in === 1'bx) & 
		(~(lvl0_in === 1'b0) | ~(lvl1_in === 1'b0) | ~(lvl2_in === 1'b0));
wire hit_lvl0 = (indx0_in === indx0) | ~(lvl0_in === 1'b0) | lvl0 | hit_lvl02;
wire hit_lvl1 = (indx1_in === indx1) | ~(lvl1_in === 1'b0) | lvl1 | hit_lvl12;
wire hit_lvl2 = (indx2_in === indx2) | ~(lvl2_in === 1'b0) | lvl2 | hit_lvl22;
wire hit_cntxt = (cntxt_in === cntxt) | ~(sprvsr_in === 1'b0) | sprvsr | hit_cntxt2;
wire hit_iopte = ~(~(iopte_in === 1'b0) ^ iopte) | co_in ;
wire hit_ptp =  co_in | ~(~(ptp_in === 1'b0) ^ ptp) ;
 
assign hit = ~(valid === 1'b0)  & hit_lvl0 & hit_lvl1 & hit_lvl2 & hit_cntxt &
                hit_iopte & hit_ptp ;
 
assign err = hit & ((~prtct[5] & prtct_in[5]) |
                      (~prtct[4] & prtct_in[4]) |
                      (~prtct[3] & prtct_in[3]) |
                      (~prtct[2] & prtct_in[2]) |
                      (~prtct[1] & prtct_in[1]) |
                      (~prtct[0] & prtct_in[0])) ;
 
assign m_ok = hit & (mbit | (~prtct_in[3] & ~prtct_in[0])) ;
 
endmodule




module iosram (
        decoded_addr,
        do,
        di,
        we,
	flush_op,
	miss,
        clk
);
 
input [15:0] decoded_addr;
input [`IOTLBDATA_WIDTH-1:0] di;
input we, flush_op, miss, clk;
integer i;
 
output [`IOTLBDATA_WIDTH-1:0] do;

// synopsys translate_off
 
        wire [3:0] addrx;
 
// IOTLB SRAM instantiated
 
        reg [`IOTLBDATA_WIDTH-1:0] tlb_data [`IOTLBENTRIES-1:0] ;

initial begin
	for(i= 0; i<16 ;i = i + 1)
		tlb_data[i] = 28'bx;
end
 
// Generate active low WE pulse
 
        wire we_ = ~(we & ~clk);
 
// Encode address
       
        assign addrx[3:0] = encode_address(decoded_addr[15:0]);
 
// IOTLB SRAM read
 
        assign do = (miss | flush_op) ? 28'bx : (we_ ? tlb_data[addrx] : di);
 
// TLB SRAM write
// implement to latch type 
// level senative 
 
         
        always @ (negedge we_)  begin 
               tlb_data[addrx] = di;
        end

// speciall hardwire for debuing

 
/////////////////////////////////////////////////////////////////////
// This function should be in GCB
//      encode_address:
//
//              Encodes 16 wires into 4 bits, assuming that only one
//              of the 16 inputs is high.

function [3:0] encode_address;
input [15:0] decoded_addr;
reg [3:0] encode_out;
integer i;
begin
        encode_out = 0;
        for (i = 0; i < 16; i = i + 1)
                if (decoded_addr[i] == 1)
                  encode_out = i;
        encode_address = encode_out;

end
endfunction

// synopsys translate_on

 
endmodule


module IOCMUX4W(in0_fn,in1_fn,in2_fn,in3_fn,select_fn,out_fna) ;
    input [41:0] in0_fn ;
    input [41:0] in1_fn ;
    input [41:0] in2_fn ;
    input [41:0] in3_fn ;
    input [1:0] select_fn ;
    output [41:0] out_fna ;

    wire [41:0] out_fna = CMUX(in0_fn,in1_fn,in2_fn,in3_fn,select_fn);
 
function [41:0] CMUX ;
    input [41:0] in0_fn ;
    input [41:0] in1_fn ;
    input [41:0] in2_fn ;
    input [41:0] in3_fn ;
    input [1:0] select_fn ;
    reg   [41:0] out_fn ;
    begin
            case (select_fn) //synopsys parallel_case full_case
                    2'b00:  out_fn = in0_fn ;
                    2'b01:  out_fn = in1_fn ;
                    2'b10:  out_fn = in2_fn ;
                    2'b11:  out_fn = in3_fn ;
            endcase
            CMUX = out_fn ;
    end
endfunction
endmodule


module IOMflipflop_s_6_old (out, din, scanen, sin, clock) ;
output [5:0] out ;
input [5:0]  din ;
input   scanen ;
input   sin ;
input   clock ;

        Mflipflop_s Mflipflop_s_5_0 (out[0], din[0], scanen, out[1], clock);
        Mflipflop_s Mflipflop_s_5_1 (out[1], din[1], scanen, out[2], clock);
        Mflipflop_s Mflipflop_s_5_2 (out[2], din[2], scanen, out[3], clock);
        Mflipflop_s Mflipflop_s_5_3 (out[3], din[3], scanen, out[4], clock);
        Mflipflop_s Mflipflop_s_5_4 (out[4], din[4], scanen, out[5], clock);
        Mflipflop_s Mflipflop_s_5_5 (out[5], din[5], scanen, sin, clock);

endmodule


module IOMflipflop_s_8_old (out, din, scanen, sin, clock) ;
output [7:0] out ;
input [7:0]  din ;
input   scanen ;
input   sin ;
input   clock ;

        Mflipflop_s Mflipflop_s_7_0 (out[0], din[0], scanen, out[1], clock);
        Mflipflop_s Mflipflop_s_7_1 (out[1], din[1], scanen, out[2], clock);
        Mflipflop_s Mflipflop_s_7_2 (out[2], din[2], scanen, out[3], clock);
        Mflipflop_s Mflipflop_s_7_3 (out[3], din[3], scanen, out[4], clock);
        Mflipflop_s Mflipflop_s_7_4 (out[4], din[4], scanen, out[5], clock);
        Mflipflop_s Mflipflop_s_7_5 (out[5], din[5], scanen, out[6], clock);
        Mflipflop_s Mflipflop_s_7_6 (out[6], din[6], scanen, out[7], clock);
        Mflipflop_s Mflipflop_s_7_7 (out[7], din[7], scanen, sin, clock);
 
endmodule

 

module IOMflipflop_s_2_old (out, din, scanen, sin, clock) ;
output [1:0] out ;
input [1:0]  din ;
input   scanen ;
input   sin ;
input   clock ;
 
        Mflipflop_s Mflipflop_s_1_0 (out[0], din[0], scanen, out[1], clock);
        Mflipflop_s Mflipflop_s_1_1 (out[1], din[1], scanen, sin, clock);
 
endmodule