/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)m_mmu_cntl.v
***
****************************************************************************
****************************************************************************/
// @(#)m_mmu_cntl.v 1.195 9/21/93
//****************************************************************************
// m_mmu_cntl.v
//
// Description:
// Preprocessed MMU Logic and State Machines
// Top Standard Cell Block for MMU
//
//****************************************************************************
![[Up: mmu MMU_cntl]](v2html-up.gif)
module m_mmu_cntl
(
ic_miss,
enbl_br_fold,
io_s_bit,
tw_io_bit,
mm_misc2cf,
mm_misc2cf_2nd,
issue_req_early,
tw_rewrite_cam,
lvl_probe_hld,
mm_fbpage_en,
mm_lvl15_int_l,
mm_dcdaten,
mm_icdaten,
mm_dct_daten,
mm_iccfstb,
mm_icstben,
mm_mreq,
m_in,
ptp_in,
va_s_in,
tw_sin,
tw_tlb_vbit,
mm_page_hit_en,
mm_page,
asi_dcd6,
mm_dccfstb,
tlb_flush,
tlb_ram_lvl,
tlb_cam_lvl,
mm_oddpar,
mm_parity_en,
mm_rfr_cntl,
tlb_asel,
mm_dabort,
mm_iabort,
mm_mfdaten,
mem_issue_req,
mem_issue_req2,
mm_fb_req,
mm_fb_size,
mm_bp_dtct, /* MMU breakpoint detect */
mm_istat_avail,
mm_dstat_avail,
mm_wbstb, /* Write buffer strobe for advancing wb */
mm_wbsel1, /* Write buffer select for std */
mm_icache_enbl,
mm_dcache_enbl,
mm_cache_stat,
/*** dp outputs **/
sfar_write, /* SFAR input mux select*/
sfar_read, /* SFAR input mux select*/
tlb_acc_cmp, /* TLB Mbit for compares */
tlb_mbit_cmp, /* TLB Mbit for compares */
mbit_sel, /* mux select for mbit muxes.*/
va_mux0_sel, /* mux select for VA muxes.*/
va_mux1_sel, /* mux select for VA muxes.*/
va_mux_sel, /* mux select for VA muxes.*/
hld_cxr, /* Hold enable for CXR*/
hold_sfar, /* Hold enable for SFAR*/
sel_mdat_mux, /* reg'd mdat mux sel. w/ asi_dcd*/
hld_ctpr, /* load enable for CTPR*/
hld_ibar, /* load enable for IBAR*/
hold_par, /* load enable for PAR*/
hld_afar, /* load enable for AFAR*/
hld_mfar, /* load enable for MFAR*/
afar_write, /* input mux select for AFAR.*/
mfar_write, /* input mux select for MFAR.*/
bp_sel_30, /* Bypass mux selects for bits [30:29].*/
bp_sel_28, /* Bypass mux selects for bit [28].*/
bp_sel_21, /* Bypass mux selects for bits [27:21].*/
bp_sel_20, /* Bypass mux selects for bit [20].*/
bp_sel_19, /* Bypass mux selects for bit [19].*/
bp_sel_18, /* Bypass mux selects for bit [18].*/
bp_sel_17, /* Bypass mux selects for bit [17].*/
bp_sel_16, /* Bypass mux selects for bit [16].*/
bp_sel_15, /* Bypass mux selects for bit [15].*/
bp_sel_14, /* Bypass mux selects for bit [14].*/
bp_mux_sel0, /* Bypass mux select for D0 input */
sr_tw, /* Bypass mux select for cpu_walk */
io_tlb_tw, /* Bypass mux select for io_walk */
dpa_sel_b, /* DPA mux select for ROOT/level-1 PTE*/
dpa_sel_8d, /* DPA mux select for bits [09:08] */
ctpr_sel, /* DPA mux selects for bits [07:04].*/
dpa_sel_0, /* DPA mux selects for bits [01:00].*/
va_ptp8_sel,
va_ptp4_sel,
dp_mux1_sel, /* mux select for TLB/ITBR read mux*/
pamux_rd_sel, /* mux select for PA regs read mux*/
boot_out_30, /* PA[30] for IO bypass path */
tlb_wrt_tag, /* write enable for TLB tag */
misc,
precharge_early_0,
precharge_early_1,
mm_dacc_err,
mm_dacc_miss, // Data access xlate miss
mm_dacc_wp, // Data watchpoint trap
mm_dacc_exc,
tlb_addr,
tlb_io_bit,
mm_sbae_0,
mm_rom_module_speed,
tlb_co_in,
tlb_c_rd,
par_sel,
hld_dpar,
hld_ipar,
cam_reg_hld,
ram_reg_hld,
mm_fs_lvl,
mm_fs_perr,
mm_fs_iae,
mm_fs_xerr,
mm_fs_mmiss,
mm_fs_sbe,
mm_fs_sto,
mm_fs_sptct,
ld_pcntr_a,
ld_pcntr_b,
trig_a,
trig_b,
iva_wp_sel,
sel_brkpt_mux,
vaf_en_hld,
va_bp_hld,
va_src_sel,
mm_mem_dbg,
pcic_ifetch, // added for pci boot
mm_go_standby, // added for programmable standby.
/*** Inputs ***/
turn_off_standby, // turns off programmable standby.
bm_sel, // if set, boot from SBus, else AFX
w_sp_sel, // Speed select (for mmu status)
w_div_ctl, // Divide by cntl (mmu status)
mc_afx_to, // AFX timeout indicator
ic_idle,
tb_error,
m_miss,
misc_in,
invalid_wb_entry,
mm_pa,
ld_op_e,
st_op_e,
fpu_mem_e,
fp_trap_fix, // FPU trap may occur at anytime
wb_3_size,
wb_3_asi,
wb_valid,
iu_size_e,
iu_asi_e,
mc_mstb_l,
mc_mbsy,
tlb_miss_raw,
acc_ok,
iu_pipe_hold,
tlb_acc_raw,
tlb_c_bit,
iu_in_trap,
io_space,
cntl_space,
fb_space,
mem_space,
pci_space,
cxr,
r_d_vaddr,
tlb_lvl,
pa_mux_rd,
dp_perr,
brk_pt_hit,
odd_wd,
page_hit,
page_miss0,
page_miss1,
mm_hold_rst,
ic_miss_or_part,
ic_miss_and_part,
it_hit_f, // itag hit in f stage ** ASSERTED LOW **
dc_miss_or_part,
dc_miss_and_part,
dt_hit_w,
dc_miss_sustain,
ic_miss_sustain,
iu_sfs_sup,
iu_sfs_perr,
iu_sfs_xerr,
iu_sfs_mmiss,
iu_sfs_iae,
iu_sfs_sbe,
iu_sfs_sto,
iu_sfs_prtct,
iu_sfs_priv,
iu_sfs_lvl,
iu_mm_iacc_wp_exc_d,
dcc_idle,
ihold_d1, // MMU perf counter trigger
dhold_d1, // MMU perf counter trigger
dc_shold, // MMU perf counter trigger
did_fetch, // MMU perf counter trigger
hold_fetch_f_l, // Holds fetch logic
fhold_d1, // MMU perf counter trigger
fhold_fqfull_d1, // MMU perf counter trigger
iu_sup_mode, // MMU perf counter trigger
pcntr_a_co, // MMU perf counter trigger
pcntr_b_co, // MMU perf counter trigger
p_reply_dec, // AFX queue status
ss_clock,
ss_reset,
ss_reset_any,
ss_scan_mode,
ss_scan_in,
ss_scan_out
);
output ic_miss; // decoded ic_miss for datapath
output enbl_br_fold; // enable for branch folding
wire mm_ifetch; // ifetch from EPROM
output io_s_bit; // enable for branch folding
output tw_io_bit; // enable for branch folding
output mm_misc2cf; // connect misc to cfb
output mm_misc2cf_2nd; // transfer misc to cachefill (MEMIF) 2nd word */
output issue_req_early; // signal to memif of a pending issue_req
output tw_rewrite_cam; // tw will rewrite PTE CAM entry
output lvl_probe_hld; // hold PTP/PTE coming from mem
output mm_fbpage_en;
wire mm_cpcyc_stb_l; // output indicating SBC data & addr. valid
wire mm_cpsb_wrt; // output indicating SBC wrt
output mm_lvl15_int_l; // Level 15 interrupt
wire mm_sb_err; // output to SBC indicating error on IO DMA
output mm_dcdaten;
output mm_icdaten;
output mm_dct_daten;
output mm_iccfstb; // assert stb_en for ic cache fill bus
output mm_icstben ; // indicates icstben is for ASI op (see bug 750)
wire mm_iodaten; // indicates data to be driven from sbc
wire mm_iostben; // assert stb_en for sbc
output [3:0] mm_mreq; // memory request type to mcb
output m_in; // tlb modified bit input
output ptp_in; // tlb ptp bit input
output va_s_in; // tlb lookup supervisor field input
output tw_sin; // tlb tablewalk supervisor field input
output tw_tlb_vbit; // tlb v bit for tlb tw writes
wire sbc_pa_valid; // IO physical address is valid
output [1:0]mm_page_hit_en;
output mm_page;
wire mm_slock; // indicates iu requires exclusive use of sbus
output asi_dcd6; // asi op to tlb
output mm_dccfstb;
output tlb_flush; // TLB hold, to flush one pte from TLB
output [2:0] tlb_ram_lvl; // Input level for TLB CAM lookups/writes.
output [2:0] tlb_cam_lvl; // Input level for TLB CAM lookups/writes.
wire [1:0] mm_sbsize; // size of iu to sb op
output mm_oddpar; // PCR[17]
output mm_parity_en; // PCR[18]
output [3:0] mm_rfr_cntl;
output tlb_asel;
output mm_dabort;
output mm_iabort;
output mm_mfdaten; // tri-state enable for MEMIF
output mem_issue_req;
output mem_issue_req2;
output mm_fb_req;
output [1:0] mm_fb_size;
output mm_bp_dtct; /* MMU breakpoint detect */
output mm_istat_avail;
output mm_dstat_avail;
output mm_wbstb; /* Write buffer strobe for advancing wb */
output mm_wbsel1; /* Write buffer select for std */
output mm_icache_enbl;
output mm_dcache_enbl;
output mm_cache_stat; /* Cacheability status for both caches */
input invalid_wb_entry;
//output mm_dmhold_r;
/**************************************************************************/
output sfar_write; /* SFAR input mux select*/
output sfar_read; /* SFAR input reset term*/
output [5:0] tlb_acc_cmp; /* TLB ACC bits for compares .*/
output tlb_mbit_cmp; /* TLB Mbit for compares .*/
output [2:0] mbit_sel; /* mux select for mbit muxes.*/
output [3:0] va_mux0_sel; /* mux select for VA muxes.*/
output [4:0] va_mux1_sel; /* mux select for VA muxes.*/
output [3:0] va_mux_sel; /* mux select for VA muxes.*/
output hld_cxr; /* Hold enable for CXR*/
output hold_sfar; /* Hold enable for SFAR*/
output sel_mdat_mux; /* reg'd mdat mux sel. w/ asi_dcd*/
output pcic_ifetch; // for pci boot
wire pcic_ifetch; // for pci boot
output mm_go_standby; // for auto standby
wire mm_go_standby; // for auto standby
/* Input control from ASI decode */
output hld_ctpr; /* load enable for CTPR*/
output hld_ibar; /* load enable for IBAR*/
output hold_par; /* load enable for PAR*/
output hld_afar; /* load enable for AFAR*/
output hld_mfar; /* load enable for MFAR*/
output afar_write; /* input mux select for AFAR.*/
output mfar_write; /* input mux select for MFAR.*/
/*** Mux select outputs */
output [1:0] bp_sel_30; /* Bypass mux selects for bits [30:29].*/
output [1:0] bp_sel_28; /* Bypass mux selects for bit [28].*/
output bp_sel_21; /* Bypass mux selects for bits [27:21].*/
output [1:0] bp_sel_20; /* Bypass mux selects for bit [20].*/
output [1:0] bp_sel_19; /* Bypass mux selects for bit [19].*/
output [1:0] bp_sel_18; /* Bypass mux selects for bit [18].*/
output [1:0] bp_sel_17; /* Bypass mux selects for bit [17].*/
output [1:0] bp_sel_16; /* Bypass mux selects for bit [16].*/
output [1:0] bp_sel_15; /* Bypass mux selects for bit [15].*/
output [1:0] bp_sel_14; /* Bypass mux selects for bit [14].*/
output bp_mux_sel0; /* Bypass mux select for D0 input */
output sr_tw; /* Bypass mux select for cpu_walk */
output io_tlb_tw; /* Bypass mux select for io_walk */
output dpa_sel_b; /* DPA mux select for ROOT/level-1 PTE*/
output dpa_sel_8d; /* DPA mux selects for bits [09:08].*/
output ctpr_sel; /* DPA mux selects for bits [07:04].*/
output dpa_sel_0; /* DPA mux selects for bits [01:00].*/
output va_ptp8_sel;
output [3:0] va_ptp4_sel;
output [4:0] dp_mux1_sel; /* mux select for TLB/ITBR read mux*/
output [4:0] pamux_rd_sel; /* mux select for PA regs read mux*/
output boot_out_30; /* PA[30] for IO bypass path */
output tlb_wrt_tag; /* write enable for TLB tag */
output [31:0] misc;
output precharge_early_0;
output precharge_early_1;
output mm_dacc_err;
output mm_dacc_miss;
output mm_dacc_wp;
output mm_dacc_exc;
output [5:0] tlb_addr;
output tlb_io_bit;
output mm_sbae_0;
wire [5:0] mm_sbae;
output [3:0] mm_rom_module_speed;
wire [4:0] mm_sscr_ba8;
/**** new added for new tlb *****/
output tlb_co_in; /* tlb comp in */
output tlb_c_rd; /* tlb cam read control siganl */
/**** output to new data path *****/
output [1:0] par_sel;
output hld_dpar;
output hld_ipar;
output cam_reg_hld ; /* register for TLB CAM output */
output ram_reg_hld ; /* register for TLB RAM output */
output [1:0] mm_fs_lvl; // Instruction Fault status PTE level
output [1:0] mm_fs_perr; // Instruction Fault status TW perr
output mm_fs_iae; // Instr Fault Invalid Address Error
output mm_fs_xerr; // Instr Fault translation error
output mm_fs_mmiss; // Instr Fault TLB miss (software tw)
output mm_fs_sbe; // Instr Fault Sbus Error
output mm_fs_sto; // Instr Fault Sbus timeout
output mm_fs_sptct; // Instr Fault protection exception
output ld_pcntr_a;
output ld_pcntr_b;
output trig_a;
output trig_b;
output iva_wp_sel;
output sel_brkpt_mux;
output vaf_en_hld;
output va_bp_hld;
output [1:0] va_src_sel; /* VA breakpoint mux source select **/
output [1:0] mm_mem_dbg;
/**************************************************************************/
input [1:0] bm_sel; // if set, boot from SBus, else AFX
input [2:0] w_sp_sel; // Speed select (for mmu status)
input [1:0] w_div_ctl; // Divide by cntl (mmu status)
input mc_afx_to; /* AFX timeout indicator */
input ic_idle; // input to tell ic is idle now
input turn_off_standby; // force mm_go_standby off
/****** new input from tlb output **********/
input tb_error; // tlb protection error
input m_miss; // tlb output Modified Miss bit
input [31:0] misc_in;
input [30:00] mm_pa; // physical address input
input ld_op_e; // input indicating read req pending
input st_op_e; // input indicating write req pending
input fpu_mem_e; // indicates fpu mem op in E-stage
input fp_trap_fix; // FPU trap may occur at anytime
input [1:0] wb_3_size; // input indicating size of iu mem op in wb_3
input [1:0] wb_3_asi; // input indicating asi of iu mem op in wb_3
input [1:0] wb_valid; // input reflecting the valid bit of the wr buf
input [1:0] iu_size_e; // input indicating size of iu mem op in e stage
input [5:0] iu_asi_e; // input indicating asi in e stage
input mc_mstb_l; // input mdata strobe from mcb
input mc_mbsy; // input mcb busy indicator
input tlb_miss_raw; // tlb miss indication
input acc_ok ; // tlb access ok indication
input iu_pipe_hold; // indicates that pipeline is being held
input [2:0] tlb_acc_raw;
input tlb_c_bit; // cacheable bit output from tlb
input iu_in_trap; // iu in trap, cancel any pending write op
input io_space; // physical addr space decode for I/O space
input cntl_space; // physical addr space decode for Control space
input fb_space; // physical addr space decode for AFX sapce
input mem_space; // physical addr space decode for memory space
input pci_space;
wire sb_cyc_pnd = 1'b0; // sbc is busy, cannot accept new iu op
input [7:0] cxr;
input [12:2] r_d_vaddr;
wire [3:0] sb_ioreq;
wire sb_ioreq_vld;
wire [1:0] sb_err_type;
wire sb_wrt_err;
wire [2:0] sb_errsize;
// wire [3:0] sb_ioreq = {1'b0, 1'b0, 1'b0, 1'b0}; // input sbc io requests
// wire sb_ioreq_vld = 1'b0; // strobe for encoded sbc io request
// wire [1:0] sb_err_type = {1'b1, 1'b1};
// wire sb_wrt_err = 1'b0;
// wire [2:0] sb_errsize = {1'b0, 1'b0, 1'b0};
input [2:0] tlb_lvl;
input [31:0] pa_mux_rd;
input [1:0] dp_perr;
wire [2:0] sb_sbslot = {1'b0, 1'b0, 1'b0};
input brk_pt_hit; // Breakpoint address match detected
input odd_wd; /* Last memory op for an odd word */
wire [31:24] sb_ioa = {1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}; // IO address used for virtual address error checks
wire sb_va_val_l = 1'b0;
input page_hit;
input page_miss0; // page 0 miss (but valid)
input page_miss1; // page 0 miss (but valid)
output mm_hold_rst ;
input ic_miss_or_part; // I$ miss sustain from D$ controller
input ic_miss_and_part; // I$ miss sustain from D$ controller
input it_hit_f; // itag hit in f stage ** ASSERTED LOW **
input dc_miss_or_part; // D$ miss sustain from D$ controller
input dc_miss_and_part; // D$ miss sustain from D$ controller
input dt_hit_w; // D$ miss sustain from D$ controller
input dc_miss_sustain; // D$ miss sustain from D$ controller
input ic_miss_sustain; // I$ miss sustain from I$ controller
input iu_sfs_sup; // IU fault status supervisor bit
input [1:0] iu_sfs_perr; // IU fault status Parity error
input iu_sfs_xerr; // IU fault status translation error
input iu_sfs_mmiss; // IU fault status TLB miss (software tw)
input iu_sfs_iae; // IU fault status Invalid Address Error
input iu_sfs_sbe; // IU fault status Sbus error
input iu_sfs_sto; // IU fault status Sbus timeout
input iu_sfs_prtct; // IU fault status protection exception
input iu_sfs_priv; // IU fault status privilege exception
input [1:0] iu_sfs_lvl; // IU fault status PTE level field
input iu_mm_iacc_wp_exc_d; // IU instr watchpoint trap trigger
input dcc_idle;
input ihold_d1; // MMU perf counter trigger
input dhold_d1; // MMU perf counter trigger
input dc_shold; // MMU perf counter trigger
input did_fetch; // MMU perf counter trigger
input hold_fetch_f_l; // Holds fetch logic
input fhold_d1; // MMU perf counter trigger
input fhold_fqfull_d1; // MMU perf counter trigger
input iu_sup_mode; // MMU perf counter trigger
input pcntr_a_co; // MMU perf counter trigger
input pcntr_b_co; // MMU perf counter trigger
input [2:0] p_reply_dec; // AFX queue status
input ss_clock; // input clock
input ss_reset; // input reset
input ss_reset_any; // input reset
input ss_scan_mode; // scan enable
input ss_scan_in; // scan in
output ss_scan_out; // scan out
wire [31:0] misc_in;
wire [31:0] misc;
/** dp wires **/
/*****************************************************************************/
/***** Wire declarations for interconnect ************************************/
wire [1:0] size_w;
wire [2:0] data_acc_s;
wire [2:0] r_p_reply_dec;
wire [1:0] tw_sm_lvl;
wire [1:0] tw_err_lvl;
wire mmu_bypass;
wire r_tw_err;
wire probe;
wire [31:0] mmu_cr;
wire [3:0] mop_mreq;
wire [2:0] io_range;
wire [3:0] r_sb_ioreq;
wire [7:1] io_range_sel;
wire [5:0] asi_w;
wire [1:0] mdata_in_et = misc_in[1:0];
wire [1:0] mdata_in_acc = misc_in[4:3];
wire mdata_in_r = misc_in[05];
wire mdata_in_m = misc_in[06];
wire probe_err;
/** PCR decodes **/
wire mm_ac_en = mmu_cr[15]; // Alternate cacheability enable.
wire mmu_en = mmu_cr[00]; // MMU enable is PCR[00].
wire pcr_dcen = mmu_cr[08];
wire pcr_icen = mmu_cr[09];
assign mm_dcache_enbl = mmu_cr[08];
assign mm_icache_enbl = mmu_cr[09];
wire[31:00] dc_wrtbuf1;
wire[31:00] dc_wrtbuf0;
wire[3:0] dp_mux2_sel;
wire[1:0] wb_3_asi_buf;
wire[11:00] mmu_brkpt_en;
assign mm_sbae_0 = mm_sbae[0];
/*****************************************************************************/
/***** Module instantiations *************************************************/
/*****************************************************************************/
/*****************************************************************************/
/*** Memory Arbitration state machine ***/
/*** ***/
/*** Contains state machine logic for internal bus controls. ***/
/*** This includes the misc[31:0] and cache_fill[63:0] busses. ***/
/*** All tri-state enables, data strobes, memory requests, and ***/
/*** priority decodes for the 2 busses is done here. ***/
/*** ***/
/*****************************************************************************/
rl_marb_sm marb_sm(
.cs_st_op (cs_st_op), /* control space mmu reg st op */
.mm_ifetch (mm_ifetch), /* ifetch from EPROM */
.mm_slock (mm_slock), /* indicates PIO atomic op */
.issue_req_early (issue_req_early),/* issue_req coming for sb write */
.mm_cpcyc_stb_l (mm_cpcyc_stb_l), /* indicates SBC data & addr valid */
.mm_cpsb_wrt (mm_cpsb_wrt), /* output indicating PIO write */
.sb_data_clr (sb_data_clr), /* indicates sb_data_avail serviced*/
.sb_par_clr (sb_par_clr), /* IO Control space op is done */
.pio_data_rcvd (pio_data_rcvd), /* PIO data received */
.mem_issue_req (mem_issue_req), /* Main memory issue request */
.mem_issue_req2 (mem_issue_req2), /* Main memory issue request -copy */
.io_issue_req (io_issue_req), /* IO space issue request */
.r_mbsy (r_mbsy), /* write decode for MEMIF */
.r_fb_space (r_fb_space), /* AFX space decoded */
.mm_istat_avail (mm_istat_avail), /* Status Valid decode for I-cache */
.mm_dstat_avail (mm_dstat_avail), /* Status Valid decode for I-cache */
.ic_issue_req (ic_issue_req), /* Issue request for I-cache op */
.dc_issue_req (dc_issue_req), /* Issue request for D-cache op */
.mmdaten (mmdaten), /* tristate enable for MMU */
.mm_dcdaten (mm_dcdaten), /* tristate enable for D-cache */
.mm_icdaten (mm_icdaten), /* tristate enable for I-cache */
.mm_iodaten (mm_iodaten), /* tristate enable for SBC */
.mm_mfdaten (mm_mfdaten), /* tristate enable for MEMIF */
.mmstben (mmstben), /* Data Strobe for MMU (misc) */
.mm_iostben (mm_iostben), /* Data Strobe for SBC (misc) */
.mm_icstben (mm_icstben), /* Data Strobe for I$ ASI (misc) */
.mm_dct_daten (mm_dct_daten), /* Data Stb for D$ Tag ASI (misc) */
.mm_dccfstb (mm_dccfstb), /* Data Strobe for D$ (cachefill) */
.mm_iccfstb (mm_iccfstb), /* Data Strobe for I$ (cachefill) */
.mm_misc2cf (mm_misc2cf), /* transfer misc to cachefill */
.mm_misc2cf_2nd (mm_misc2cf_2nd), /* misc to cachefill 2nd word */
.sbc_pa_valid (sbc_pa_valid), /* PA valid for SBC (read or xlate)*/
.r_sb_ic_op (r_sb_ic_op), /* Last PIO was for I-cache miss */
.ldst_st (ldst_st), /* Store part of ldsto (D_ATOMIC) */
.ldst_block (ldst_block), /* Store part of ldsto (D_ATOMIC) */
.mm_dnocache_done (mm_dnocache_done), /* non $ op done */
.asi_sm_done (asi_sm_done), /* non $ asi op done */
.r_mstb_l (r_mstb_l), /* Reg'd mc_mstb_l */
.iwait_state (iwait_state), /* Waiting for 1st instr from mem */
.mmstben_aarb (mmstben_aarb), /* Data strobe for MMU for ASI store */
.mmreg_rd_asi (mmreg_rd_asi), /* Data strobe for MMU for ASI loads */
.mmreg_rd_cs (mmreg_rd_cs), /* Data strobe for MMU for ASI loads */
.mm_wbstb (mm_wbstb), /* Write Buffer strobe */
.mm_wbsel1 (mm_wbsel1), /* Write Buffer select */
.tlb_asi_act (tlb_asi_act), /* TLB ASI op active */
.tlb_c_rd (tlb_c_rd), /* cam direct read decode */
.asi_cam_read (asi_cam_read), /* from marb to tell asi is doing cam read */
.asi_ram_read (asi_ram_read), /* tell asi is doing ram read */
.ic_stream (ic_stream), /* Performance monitor decode */
.dc_stream (dc_stream), /* Performance monitor decode */
.r_drd_c1 (r_drd_c1), /* Marb state DRD_C1 reg'd */
.sel_cache_stat (sel_cache_stat), /* MMU register select decode */
.marb_busy (marb_busy), /* Memory arb sm busy */
.aarb_bsy (aarb_bsy), /* ASI arb sm busy */
.pcic_ifetch (pcic_ifetch), /* instruction fetch held for pcic boot */
.sb_err_type (sb_err_type), /* all PIO results in errors. */
.sb_wrt_err (sb_wrt_err), /* all PIO results in errors. */
.sb_errsize (sb_errsize), /* all PIO results in errors. */
.sb_ioreq (sb_ioreq), /* all PIO results in errors. */
.sb_ioreq_vld (sb_ioreq_vld), /* all PIO results in errors. */
/* inputs */
.mm_sbsize (mm_sbsize), /* PIO error size. */
.r_dc_miss (r_dc_miss), /* registered dc_miss */
.mc_mbsy (mc_mbsy), /* Memory busy signal */
.sb_sbsy (sb_cyc_pnd), /* SBC busy signal */
.dvma_req_x (dvma_req_x), /* dvma request signal */
.r_dc_par (r_dc_par), /* D-cache address in PAR */
.r_ic_par (r_ic_par), /* I-cache address in PAR */
.r_sb_par (r_sb_par), /* DMA (sbc) address in PAR */
.sb_par (sb_par), /* unregister version of sb_par */
.r_tw_par (r_tw_par), /* tablewalk address in PAR */
.r_io_space (r_io_space), /* PAR decode for IO space address */
.r_cntl_space (r_cntl_space), /* PAR decode for Control space addr */
.r_mem_space (r_mem_space), /* PAR decode for memory space addr */
.fb_space (fb_space), /* PAR decode for AFX space */
.mop_c_bit (mop_c_bit), /* Current memory op cacheable bit */
.mop_mreq (mop_mreq), /* Current memory op mreq bit */
.mc_mstb_l (mc_mstb_l), /* data strobe from MEMIF */
.wb_valid_x (wb_valid_x), /* D-cache addr in PAR for write op */
.read_w (read_w), /* ld or ldst in W-stage */
.probe_done (probe_done), /* probe op done */
.flush_done (flush_done), /* flush op done */
.ldsto_x (ldsto_x), /* D-cache address in PAR for ldsto */
.sb_write (sb_write), /* DMA (sbc) write request pending */
.r_srd_ioreq (r_srd_ioreq), /* DMA (sbc) read request pending */
.r_sxlate (r_sxlate), /* DVMA xlate op (pending or active)*/
.sb_data_avail (sb_data_avail), /* Data avail from SBC (on PIO read) */
.r_sb_ioreq (r_sb_ioreq), /* SBC request for current memory op */
.tw_read_req (tw_read_req), /* tablewalk read request */
.tw_write_req (tw_write_req), /* tablewalk address is PAR for write op */
.std_x (std_x), /* Store is double word size */
.ldd_w (ldd_w), /* D-cache load in W-stage is double word */
.mmu_asi_op (mmu_asi_op), /* ASI op in par cntl sm */
.mmu_asi (mmu_asi), /* MMU ASI op in W-stage */
.asi_dcd6 (asi_dcd6), /* MMU access ASI=x06 in W-stage */
.ic_asi (ic_asi), /* I-cache access ASI in W-stage */
.dc_asi (dc_asi), /* D-cache access ASI in W-stage */
.write_x (write_x), /* reg'd write_w */
.st_miss_c (st_miss_c), /* Store miss in W-stage - cacheable */
.st_miss_x (st_miss_x), /* Store miss in W-stage */
.derr_wbstb (derr_wbstb), /* Data error write buffer strobe */
.dabort_in (dabort_in),
.r_trap_w (r_trap_w),
.fp_ld_mask (fp_ld_mask),
.wb_err (wb_err),
.afx_qbusy (afx_qbusy),
.mmu_cr_14 (mmu_cr[14]), // mmu_cr boot_mode bit
.ss_clock (ss_clock),
.ss_scan_mode (ss_scan_mode), // added
.ss_reset (ss_reset));
/****************************************************************************/
/*** MMU (random) Logic ***/
/*** ***/
/*** This file contains most of the MMU logic that didn't fit ***/
/*** neatly in any other file. ***/
/*** This includes: ***/
/*** shadow registers for IU pipeline info ***/
/*** SBC request decodes ***/
/*** Write buffer valid decode ***/
/*** ***/
/****************************************************************************/
rl_mmu_lgc mmu_lgc(
.mm_mreq (mm_mreq), /* */
.mm_fb_req (mm_fb_req), /* */
.r_dc_miss (r_dc_miss), /* */
.dc_miss (dc_miss),
.r_ic_miss (r_ic_miss), /* */
.ic_miss (ic_miss),
.dvma_req_s (dvma_req_s), /* valid dvma request detected */
.dvma_req_x (dvma_req_x), /* valid dvma request detected */
.set_m_on_tw (set_m_on_tw),
.r_sxlate (r_sxlate),
.r_sxlate_ioreq (r_sxlate_ioreq),
.strt_tw_for_m (strt_tw_for_m),
.dmiss_for_m (dmiss_for_m),
.sb_write (sb_write),
.r_srd_ioreq (r_srd_ioreq),
.r_tlb_miss (r_tlb_miss), /* Registered TLB miss */
.size_w (size_w),
.mm_fb_size (mm_fb_size), /* Frame buffer op size */
.bypass_mmu_asi (bypass_mmu_asi),
.asidcd_mask (asidcd_mask), /* mask non-device ASIs */
.asi_done (asi_done), /* ASI operation done */
.sb_data_avail (sb_data_avail),
.mm_sbsize (mm_sbsize),
.data_acc_s (data_acc_s), /* data access type code */
.r_tlb_miss_tw (r_tlb_miss_tw),
.tlb_miss_tw (tlb_miss_tw),
.mm_dabort (mm_dabort),
.dabort_in (dabort_in),
.mm_iabort (mm_iabort),
.ldd_w (ldd_w),
.std_x (std_x),
.r_tlb_used (r_tlb_used),
.asi_w (asi_w),
.r_sb_ioreq (r_sb_ioreq),
.r_trap_w (r_trap_w),
.read_w (read_w),
.read_w_reg (read_w_reg),
.write_x (write_x),
.st_op_w (st_op_w),
.ldsto_w (ldsto_w),
.ldsto_x (ldsto_x),
.r_ldsto_w (r_ldsto_w),
.cbit_in (cbit_in),
.mmulgc_bp_hit (mmulgc_bp_hit),
.ok_2_probe (ok_2_probe),
.mm_page (mm_page),
.r_io_space (r_io_space),
.r_mem_space (r_mem_space),
.r_cntl_space (r_cntl_space),
.r_pci_space (r_pci_space),
.wb_valid_t (wb_valid_t),
.wb_valid_x (wb_valid_x),
.wb_valid_x_reg (wb_valid_x_reg),
.wb_empty (wb_empty),
.st_miss_c (st_miss_c),
.st_miss_x (st_miss_x),
.st_miss_x_reg (st_miss_x_reg),
.last_st_w (last_st_w),
.derr_wbstb (derr_wbstb), /* Data error write buffer strobe */
.r_dc_in_par (r_dc_in_par),
.r_ic_in_par (r_ic_in_par),
.r_ic_tlb (r_ic_tlb),
.r_dc_tlb (r_dc_tlb),
.r_wr_tlb (r_wr_tlb),
.pipe_moved (pipe_moved), /* */
.dfetch (dfetch),
.fp_ld_mask (fp_ld_mask),
.precharge_early_0 (precharge_early_0),
.precharge_early_1 (precharge_early_1),
.mm_hold_rst (mm_hold_rst),
.afx_qbusy (afx_qbusy),
.wb_3_asi_buf (wb_3_asi_buf),
/*** start of inputs ***/
.tw_tlb_nxt (tw_tlb_nxt),
.cntrl_spc_err (cntrl_spc_err),
.dcc_idle (dcc_idle),
.hold_par (hold_par), // Hold PAR register
.mc_mstb_l (mc_mstb_l),
.normal_asi_w (normal_asi_w),
.invalid_wb_entry (invalid_wb_entry),
.mm_dnocache_done (mm_dnocache_done),
.sb_data_clr (sb_data_clr),
.sbc_pa_valid (sbc_pa_valid),
.sb_ioreq (sb_ioreq),
.sb_ioreq_vld (sb_ioreq_vld),
.tw_par (tw_par),
.ld_op_e (ld_op_e),
.st_op_e (st_op_e),
.fpu_mem_e (fpu_mem_e),
.fp_trap_fix (fp_trap_fix),
.wb_3_size (wb_3_size),
.wb_valid (wb_valid),
.iu_size_e (iu_size_e),
.iu_asi_e (iu_asi_e),
.tlb_miss (tlb_miss),
.ld_par (ld_par),
.ld_mreq_tw (ld_mreq_tw),
.pcr_dcen (pcr_dcen),
.pcr_icen (pcr_icen),
.tw_read_req (tw_read_req),
.tw_write_req (tw_write_req),
.mem_issue_req (mem_issue_req),
.iu_pipe_hold (iu_pipe_hold),
.iu_pipe_hold_fast (iu_pipe_hold),
.m_miss (m_miss),
.tlb_c_bit (tlb_c_bit),
.bypass_mmu_asi_w (bypass_mmu_asi_w),
.mmu_bypass (mmu_bypass),
.pcr_mmuen (mmu_en),
.pcr_ac (mm_ac_en),
.ldst_st (ldst_st),
.iu_in_trap (iu_in_trap),
.io_space (io_space),
.cntl_space (cntl_space),
.mem_space (mem_space),
.fb_space (fb_space),
.pci_space (pci_space),
.flush_iopte (flush_iopte),
.tw_err (tw_err),
.priv_err_x (priv_err_x),
.prtct_err_x (prtct_err_x),
.sb_cyc_pnd (sb_cyc_pnd),
.io_tlb_err (io_tlb_err),
.tw_init_par (tw_init_par),
.probe (probe),
.probe_done (probe_done),
.tw_sm_lvl (tw_sm_lvl),
.r_acc_err_tw (r_acc_err_tw),
.tw_prb_drdy (tw_prb_drdy),
.iacc_miss (iacc_miss),
.dacc_miss (dacc_miss),
.enbl_soft_tw (enbl_soft_tw),
.ic_tlb (ic_tlb),
.ic_tlb_state (ic_tlb_state),
.dc_tlb (dc_tlb),
.dc_tlb_state (dc_tlb_state),
.wr_tlb (wr_tlb),
.io_tlb (io_tlb),
.ic_tlb_tw (ic_tlb_tw),
.dc_tlb_tw (dc_tlb_tw),
.wr_tlb_tw (wr_tlb_tw),
.io_tlb_tw (io_tlb_tw),
.ic_in_par (ic_in_par),
.dc_in_par (dc_in_par),
.par_cbit (par_cbit),
.ipar_cbit (ipar_cbit),
.dpar_cbit (dpar_cbit),
.ic_par_state (ic_par_state),
.dc_par_state (dc_par_state),
.mop_c_bit (mop_c_bit),
.ic_miss_or_part (ic_miss_or_part),
.ic_miss_and_part (ic_miss_and_part),
.it_hit_f (it_hit_f), // itag hit in f stage ** ASSERTED LOW **
.dc_miss_or_part (dc_miss_or_part),
.dc_miss_and_part (dc_miss_and_part),
.dt_hit_w (dt_hit_w),
.dc_miss_sustain (dc_miss_sustain),
.dc_stream (dc_stream),
.ic_miss_sustain (ic_miss_sustain),
.mm_wbstb (mm_wbstb),
.wb_3_asi (wb_3_asi),
.mm_sb_err (mm_sb_err),
.mmu_asi_op (mmu_asi_op), // Par Control in ASI_OP state
.dc_issue_req (dc_issue_req), /* Issue request for D-cache op */
.asi_dcd3 (asi_dcd3),
.r_pipe_moved (r_pipe_moved),
.page_hit (page_hit),
.page_miss0 (page_miss0),
.page_miss1 (page_miss1),
.req_pending (req_pending),
.mc_mbsy (mc_mbsy),
.r_mbsy (r_mbsy),
.sup_nalloc (sup_nalloc),
.r_sup_mode (r_sup_mode),
.dp_bp_hit (brk_pt_hit),
.mmu_brkpt_en (mmu_brkpt_en),
.r_p_reply_dec (r_p_reply_dec),
.afx_qlvl (afx_qlvl),
.marb_busy (marb_busy),
.aarb_bsy (aarb_bsy),
.r_mem_issue_req (r_mem_issue_req),
.sbus_id_hit (sbus_id_hit),
.cs_st_op (cs_st_op), /* control space reg st op */
.ss_clock (ss_clock),
.ss_reset (ss_reset));
/****************************************************************************/
/*** Tablewalk state machine ***/
/*** ***/
/*** This file contains the MMU tablewalk state machine and ***/
/*** associated control decodes. ***/
/*** ***/
/****************************************************************************/
rl_tw_sm tw_sm(
.root_tw (root_tw),
.pt1_tw (pt1_tw),
.pt2_tw (pt2_tw),
.tw_done (tw_done),
.io_s_bit (io_s_bit),
.tw_abort (tw_abort),
.lvl_probe_hld (lvl_probe_hld),
.tw_tlb_vbit (tw_tlb_vbit),
.tlb_cam_reload (tlb_cam_reload),
.co_in (tlb_co_in),
.tw_rewrite_cam (tw_rewrite_cam),
.ldtlb_data_tw (ldtlb_data_tw),
.ldtlb_tag_tw (ldtlb_tag_tw),
.va_sel_par_in (va_sel_par_in),
.tw_read_req (tw_read_req),
.read_word_mreq (read_word_mreq),
.tw_write_req (tw_write_req),
.tw_io_bit (tw_io_bit),
.m_in (m_in),
.ptp_in (ptp_in),
.va_s_in (va_s_in),
.tlb_ram_lvl (tlb_ram_lvl),
.tlb_cam_lvl (tlb_cam_lvl),
.tw_tlb_nxt (tw_tlb_nxt),
.tw_sm_lvl (tw_sm_lvl),
.tw_err_lvl (tw_err_lvl),
.ld_par_tw (ld_par_tw),
.tw_init_par (tw_init_par),
.ld_mreq_tw (ld_mreq_tw),
.tlb_flush (tlb_flush),
.r_flush_entry (r_flush_entry),
.tlb_update (tlb_update),
.tw_trcr_hld (tw_trcr_hld),
.tw_addr_err (tw_addr_err),
.tw_xlat_err (tw_xlat_err),
.tw_prb_drdy (tw_prb_drdy),
.tw_prb_err (tw_prb_err),
.probe_invalid (probe_invalid),
.probe_done (probe_done),
.flush_done (flush_done),
.tw_sin (tw_sin),
.tw_pte_chk (tw_pte_chk),
.io_tw_wrt (io_tw_wrt),
.sr_tw_wrt (sr_tw_wrt),
.cam_reg_hld (cam_reg_hld),
.ram_reg_hld (ram_reg_hld),
.io_tlb_tw (io_tlb_tw),
.io_tlb (io_tlb),
.set_m_on_tw (set_m_on_tw),
.strt_tw_for_m (strt_tw_for_m),
.mdata_in_et (mdata_in_et),
.mdata_in_acc (mdata_in_acc),
.mdata_in_r (mdata_in_r),
.mdata_in_m (mdata_in_m),
.tlb_miss (tlb_miss_tw),
.mmstben (mmstben),
.mmdaten (mmdaten),
.mc_mstb_l (mc_mstb_l),
.r_dc_tlb (r_dc_tlb),
.st_miss_x (st_miss_x),
.asi_done (asi_done),
.dvma_req_x (dvma_req_x),
.dc_tlb_tw (dc_tlb_tw),
.flush_tlb_pte (flush_tlb_pte),
.flush_tlb_reg (flush_tlb_reg),
.flush_tlb_seg (flush_tlb_seg),
.flush_tlb_ctx (flush_tlb_ctx),
.flush_tlb_all (flush_tlb_all),
.flush_iopte (flush_iopte),
.flush_ioall (flush_ioall),
.probe_err (probe_err),
.flush (flush),
.virt_ptp2 (virt_ptp2),
.probe (probe),
.probe_entire (probe_entire),
.probe_lvl0 (probe_lvl0),
.probe_lvl1 (probe_lvl1),
.probe_lvl2 (probe_lvl2),
.probe_lvl3 (probe_lvl3),
.r_acc_err_tw (r_acc_err_tw),
.mm_misc2cf (mm_misc2cf),
.tw_perr (tw_perr),
.r_tw_err (r_tw_err),
.tw_par (tw_par), // Par Control in **_TLB_TW state
.mmu_asi_op (mmu_asi_op), // Par Control in ASI_OP state
.r_trap_w (r_trap_w),
.asi_cam_read (asi_cam_read),
.asi_ram_read (asi_ram_read),
.sb_data_avail (sb_data_avail),
.enbl_soft_tw (enbl_soft_tw),
.ss_clock (ss_clock),
.ss_reset (ss_reset));
/****************************************************************************/
/*** PAR (Physical Address Register) state machine and control ***/
/*** ***/
| This page: |
Created: | Thu Aug 19 12:03:19 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/m_mmu_cntl.v
|