/******************************************************************************/
/* */
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/* */
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/******************************************************************************/
// @(#)writebuffer.v 1.46 4/17/93
//
// This file contains the writebuffer data, along with the valid bits.
// There are basically 4 modes of operation
// 1. Shift out of the write buffer.
// 2. Shift into the write buffer.
// 3. Shift in and Shift out (at the same time) from the write buffer.
// 4. Handle STD (int), seperately from any other type of store.
//
// Important:
// The write buffer should not be shifted it it is empty.
//
// The write buffer is a FIFO, connected as follows:
//
// wb_0 -> wb_1 -> wb_2 -> wb_3 -> (dout_pre) -> (dout)
module writebuffer
(
release_hold,
// cancel_last,
iu_in_trap,
add_wb_entry_d1,
iu_held,
iu_held_l,
din,
little_endian,
st_op_wb_e, // Instead use inputs below
dt_hit_w,
dc_miss_or_part,
dc_miss_and_part,
nonatomic_st_e,
nomiss_asi_e,
atomic_op_w,
nomiss_asi_w,
dcc_idle,
atomic_wb_strobed,
dcc_stat_wait,
mm_dstat_avail,
wb_full,
wb_empty,
dout,
mm_dcdaten_in,
mm_wbstb,
mm_wbsel1,
stdi_e,
// 7 signals for the mmu to clock the associated VA regs
// NOTE : these four signals are register *load* enables,
// not register *hold* controls. Please change the names
// (to either *_hold_*_l or *_load_*)!! JP
wb0_hold_hi,
wb1_hold_hi,
wb2_hold_hi,
wb3_hold_hi,
wb_1_sel_lo,
wb_2_sel_lo,
wb_3_sel_lo,
wb_valid,
//
wb_reset,
wb_clk
);
input release_hold
;
input [63:0] din
;
input little_endian
;
output [31:0] dout
; // Changed from 64 -> 32 bit bus
output wb_full
;
// input cancel_last;
input iu_in_trap
;
input add_wb_entry_d1
;
output st_op_wb_e
;
input dc_miss_or_part
;
input dt_hit_w
;
input dc_miss_and_part
;
input nonatomic_st_e
;
input nomiss_asi_e
;
input atomic_op_w
;
input nomiss_asi_w
;
input dcc_idle
;
input atomic_wb_strobed
;
input dcc_stat_wait
;
input mm_dstat_avail
;
input mm_dcdaten_in
;
input mm_wbstb
;
input mm_wbsel1
;
input wb_reset
;
input wb_clk
;
input stdi_e
;
input iu_held
;
input iu_held_l
;
output wb_empty
;
output wb0_hold_hi
;
output wb1_hold_hi
;
output wb2_hold_hi
;
output wb3_hold_hi
;
output wb_1_sel_lo
;
output wb_2_sel_lo
;
output wb_3_sel_lo
;
output [1:0] wb_valid
;
wire wb_shift_out
;
wire [63:0] wb_0_out
;
wire [63:0] wb_1_out
;
wire [63:0] wb_2_out
;
wire [63:0] wb_3_out
;
wire little_0_out
;
wire little_1_out
;
wire little_2_out
;
wire little_3_out
;
wire [63:0] wb_1_in
;
wire [63:0] wb_2_in
;
wire [63:0] wb_3_in
;
wire wb_0_vin
;
wire wb_1_vin
;
wire wb_2_vin
;
wire wb_3_vin
;
wire wb_0_vout
;
wire wb_1_vout
;
wire wb_2_vout
;
wire wb_3_vout
;
// Logic replicated to speedup iu_in_trap setup SETHLD
wire cancel_last
= iu_in_trap & add_wb_entry_d1 ;
// Logic moved to speedup dt_hit_w and mm_dstat_avail SETHLD's
wire dc_miss
= dc_miss_or_part | (~dt_hit_w & dc_miss_and_part);
wire atomic_dstat_avail
=
(atomic_op_w & ~nomiss_asi_w
& dcc_stat_wait & mm_dstat_avail & ~atomic_wb_strobed);
wire st_op_wb_e =
(~dc_miss & atomic_op_w & ~nomiss_asi_w & dcc_idle & ~atomic_wb_strobed)
| atomic_dstat_avail
| (nonatomic_st_e & ~nomiss_asi_e)
;
//
// Hard coded critical iu_held path.
// module JDB22A(A1, A2, B1, B2, O); A1, B1 are fastest inputs
wire iu_std_e
= st_op_wb_e & stdi_e ;
wire iu_std_wd2_input
, iu_std_wd2_new
;
JDB22A iu_std_wd2_gate1 (.A1(iu_held_l), .A2(iu_std_e),
.B1(release_hold), .B2(stdi_e), .O(iu_std_wd2_input));
Mflipflop_r wb_std2_ff (iu_std_wd2_new, iu_std_wd2_input,
~wb_reset, wb_clk);
// Store data registers (4)
wire hold_wb_0
, hold_wb_0_lsw
, hold_wb_1
, hold_wb_1_lsw
,
hold_wb_2
, hold_wb_2_lsw
, hold_wb_3
, hold_wb_3_lsw
;
Mflipflop_32 write_buffer_0_lo (wb_0_out[31:0], din[31:0],
wb_clk, hold_wb_0_lsw);
Mflipflop_32 write_buffer_0_hi (wb_0_out[63:32], din[63:32],
wb_clk, hold_wb_0);
Mflipflop_1 write_buffer_0 (little_0_out, little_endian,
wb_clk, hold_wb_0);
// Muxes for din of wb 1,2,3 are built into the flipflop cells
// If the *next* reg (towards BOQ) is valid, get your MSW input from that
// register, and get your LSW from that register unless that register
// is a half-filled StD. In all other cases, input comes from din.
wire wb_0_lsw_valid
, wb_1_lsw_valid
, wb_2_lsw_valid
, wb_3_lsw_valid
;
Mflipflop_mux2_h_32 write_buffer_1_lo (wb_1_out[31:0],
din[31:0], wb_0_out[31:0], wb_0_lsw_valid,
hold_wb_1_lsw, wb_clk);
Mflipflop_mux2_h_32 write_buffer_1_hi (wb_1_out[63:32],
din[63:32], wb_0_out[63:32], wb_0_vout,
hold_wb_1, wb_clk);
Mflipflop_mux2_h_1 write_buffer_1 (little_1_out,
little_endian, little_0_out, wb_0_vout,
hold_wb_1, wb_clk);
Mflipflop_mux2_h_32 write_buffer_2_lo (wb_2_out[31:0],
din[31:0], wb_1_out[31:0], wb_1_lsw_valid,
hold_wb_2_lsw, wb_clk);
Mflipflop_mux2_h_32 write_buffer_2_hi (wb_2_out[63:32],
din[63:32], wb_1_out[63:32], wb_1_vout,
hold_wb_2, wb_clk);
Mflipflop_mux2_h_1 write_buffer_2 (little_2_out,
little_endian, little_1_out, wb_1_vout,
hold_wb_2, wb_clk);
Mflipflop_mux2_h_32 write_buffer_3_lo (wb_3_out[31:0],
din[31:0], wb_2_out[31:0], wb_2_lsw_valid,
hold_wb_3_lsw, wb_clk);
Mflipflop_mux2_h_32 write_buffer_3_hi (wb_3_out[63:32],
din[63:32], wb_2_out[63:32], wb_2_vout,
hold_wb_3, wb_clk);
Mflipflop_mux2_h_1 write_buffer_3 (little_3_out,
little_endian, little_2_out, wb_2_vout,
hold_wb_3, wb_clk);
// Valid bits (4)
MflipflopR wb_0_vb (wb_0_vout, wb_0_vin,
wb_clk, hold_wb_0, wb_reset);
MflipflopR wb_1_vb (wb_1_vout, wb_1_vin,
wb_clk, hold_wb_1, wb_reset);
MflipflopR wb_2_vb (wb_2_vout, wb_2_vin,
wb_clk, hold_wb_2, wb_reset);
MflipflopR wb_3_vb (wb_3_vout, wb_3_vin,
wb_clk, hold_wb_3, wb_reset);
// For mmu
assign wb_valid = {wb_3_vout, wb_2_vout};
// The LSW is valid if the MSW is valid, unless this is the last valid queue
// entry and we're writing the second half of a StD.
// Bug # 564
// It was assumed all along that the FIFO will only show
// valid bit rep's like 0000, 0001, 0011, 1111. But unfortunately
// with the cancel operation, a string like this is possible 0101.
// This messes up the lsw of the WB for int std'd. Its fixed by
// invalidating the 'iu_std_wd2' signal during traps.
wire iu_std_wd2
= iu_std_wd2_new & ~cancel_last;
assign wb_0_lsw_valid = wb_0_vout & ~iu_std_wd2 ;
assign wb_1_lsw_valid = wb_1_vout & ~(iu_std_wd2 & ~wb_0_vout) ;
assign wb_2_lsw_valid = wb_2_vout & ~(iu_std_wd2 & ~wb_1_vout) ;
assign wb_3_lsw_valid = wb_3_vout & ~(iu_std_wd2 & ~wb_2_vout) ;
// Hold the valid bit and the MSW of a register if we're not shifting and
// it's valid; hold the LSW of a register if we're not shifting, it's
// valid, and it's not the last valid register during the write of the
// second word of a StD. Load all the registers on a Shift.
// assign hold_wb_0 = ~wb_shift_out & wb_0_vout ;
// assign hold_wb_1 = ~wb_shift_out & wb_1_vout ;
// assign hold_wb_2 = ~wb_shift_out & wb_2_vout ;
// assign hold_wb_3 = ~wb_shift_out & wb_3_vout ;
wire wb_0_vin_cancel
, wb_1_vin_cancel
, wb_2_vin_cancel
, wb_3_vin_cancel
;
assign hold_wb_0 = ~wb_shift_out & wb_0_vout & ~wb_0_vin_cancel;
assign hold_wb_1 = ~wb_shift_out & wb_1_vout & ~wb_1_vin_cancel;
assign hold_wb_2 = ~wb_shift_out & wb_2_vout & ~wb_2_vin_cancel;
assign hold_wb_3 = ~wb_shift_out & wb_3_vout & ~wb_3_vin_cancel;
assign hold_wb_0_lsw = ~wb_shift_out & wb_0_lsw_valid ;
assign hold_wb_1_lsw = ~wb_shift_out & wb_1_lsw_valid ;
assign hold_wb_2_lsw = ~wb_shift_out & wb_2_lsw_valid ;
assign hold_wb_3_lsw = ~wb_shift_out & wb_3_lsw_valid ;
// On adding an entry, don't set it valid until the pipe advances (see Bug 7).
// For integer store double, set it valid as soon as the StD reaches the
// W-stage (just like any other store); the second half of the data
// will be written at the end of the first 'valid' cycle (see Bug 9).
// Directly hardcoded, for iu_held
// wire add_entry = st_op_wb_e & ~(iu_held & ~release_hold) ;
// These are don't-cares when the corresponding valid bit is already set.
// wire set_wb_0 = (st_op_wb_e & ~(iu_held & ~release_hold)) & wb_1_vout ;
// wire set_wb_1 = (st_op_wb_e & ~(iu_held & ~release_hold)) & wb_2_vout ;
// wire set_wb_2 = (st_op_wb_e & ~(iu_held & ~release_hold)) & wb_3_vout ;
// wire set_wb_3 = (st_op_wb_e & ~(iu_held & ~release_hold)) ;
// Used only for Shift into a full FIFO
// wire set_wb_m1 = (st_op_wb_e & ~(iu_held & ~release_hold)) & wb_0_vout ;
// Remember that valid bit is held when set and no Shift.
// assign wb_0_vin = wb_shift_out ? set_wb_m1 : set_wb_0 ;
// assign wb_1_vin = wb_shift_out ? (wb_0_vout | set_wb_0) : set_wb_1 ;
// assign wb_2_vin = wb_shift_out ? (wb_1_vout | set_wb_1) : set_wb_2 ;
// assign wb_3_vin = wb_shift_out ? (wb_2_vout | set_wb_2) : set_wb_3 ;
// Insert a 1'b0 during a cancel_last cycle)
// 2 cases a) Shift & cancel b) ~Shift & cancel
assign wb_0_vin_cancel =
(cancel_last & wb_0_vout & ~wb_shift_out);
assign wb_1_vin_cancel =
(cancel_last & wb_1_vout & ~wb_0_vout & ~wb_shift_out)
| (cancel_last & wb_0_vout & wb_shift_out);
assign wb_2_vin_cancel =
(cancel_last & wb_2_vout & ~wb_1_vout & ~wb_0_vout & ~wb_shift_out)
| (cancel_last & wb_1_vout & ~wb_0_vout & wb_shift_out);
assign wb_3_vin_cancel =
(cancel_last & wb_3_vout & ~wb_2_vout & ~wb_1_vout & ~wb_0_vout & ~wb_shift_out)
| (cancel_last & wb_2_vout & ~wb_1_vout & ~wb_0_vout & wb_shift_out);
//--------------------------------------------------------------------------------
// assign wb_0_vin =
// (wb_0_vin_cancel) ? 1'b0 : (wb_shift_out ? set_wb_m1 : set_wb_0) ;
// assign wb_1_vin =
// (wb_1_vin_cancel) ? 1'b0 : (wb_shift_out ? (wb_0_vout | set_wb_0) : set_wb_1) ;
// assign wb_2_vin =
// (wb_2_vin_cancel) ? 1'b0 : (wb_shift_out ? (wb_1_vout | set_wb_1) : set_wb_2) ;
// assign wb_3_vin =
// (wb_3_vin_cancel) ? 1'b0 : (wb_shift_out ? (wb_2_vout | set_wb_2) : set_wb_3) ;
// Most critical iu_held path in . Hard coded.
// The logic below is a replica of the 2-level muxes shown above.
// Look above for a more logical explaination.
// module ANAND5C(A1, A2, A3, A4, A5, O); A5 is the fastest
// module JNAND4C(A1, A2, A3, A4, O); A4 is the fastest
// module JNAND2B(A1, A2, O); A2 is the fastest
// assign wb_0_vin =
wire wb_0_vin_a5
, wb_0_vin_a4
, wb_0_vin_a3
, wb_0_vin_a2
, wb_0_vin_a1
;
ANAND5C wb_0_vin_gate1( .A1(~wb_0_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_0_vout), .A5(iu_held_l), .O(wb_0_vin_a1));
ANAND5C wb_0_vin_gate2( .A1(~wb_0_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_0_vout), .A5(release_hold), .O(wb_0_vin_a2));
ANAND5C wb_0_vin_gate3( .A1(~wb_0_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(wb_1_vout),.A5(release_hold), .O(wb_0_vin_a3));
ANAND5C wb_0_vin_gate4( .A1(~wb_0_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(wb_1_vout),.A5(iu_held_l), .O(wb_0_vin_a4));
JNAND4C wb_0_vin_gate5( .A1(wb_0_vin_a1), .A2(wb_0_vin_a2),
.A3(wb_0_vin_a3), .A4(wb_0_vin_a4), .O(wb_0_vin));
// assign wb_1_vin =
wire wb_1_vin_a5
, wb_1_vin_a4
, wb_1_vin_a3
, wb_1_vin_a2
, wb_1_vin_a1
;
JNAND3B wb_1_vin_gate1( .A1(~wb_1_vin_cancel), .A2(wb_shift_out),
.A3(wb_0_vout), .O(wb_1_vin_a1));
ANAND5C wb_1_vin_gate2( .A1(~wb_1_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_1_vout),.A5(release_hold), .O(wb_1_vin_a2));
ANAND5C wb_1_vin_gate3( .A1(~wb_1_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(wb_2_vout),.A5(release_hold), .O(wb_1_vin_a3));
ANAND5C wb_1_vin_gate4( .A1(~wb_1_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_1_vout),.A5(iu_held_l), .O(wb_1_vin_a4));
ANAND5C wb_1_vin_gate5( .A1(~wb_1_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(wb_2_vout),.A5(iu_held_l), .O(wb_1_vin_a5));
ANAND5C wb_1_vin_gate6( .A1(wb_1_vin_a1), .A2(wb_1_vin_a2),
.A3(wb_1_vin_a3), .A4(wb_1_vin_a4), .A5(wb_1_vin_a5), .O(wb_1_vin));
// assign wb_2_vin =
wire wb_2_vin_a5
, wb_2_vin_a4
, wb_2_vin_a3
, wb_2_vin_a2
, wb_2_vin_a1
;
JNAND3B wb_2_vin_gate1( .A1(~wb_2_vin_cancel), .A2(wb_shift_out),
.A3(wb_1_vout), .O(wb_2_vin_a1));
ANAND5C wb_2_vin_gate2( .A1(~wb_2_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_2_vout),.A5(release_hold), .O(wb_2_vin_a2));
ANAND5C wb_2_vin_gate3( .A1(~wb_2_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(wb_3_vout),.A5(release_hold), .O(wb_2_vin_a3));
ANAND5C wb_2_vin_gate4( .A1(~wb_2_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_2_vout),.A5(iu_held_l), .O(wb_2_vin_a4));
ANAND5C wb_2_vin_gate5( .A1(~wb_2_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(wb_3_vout),.A5(iu_held_l), .O(wb_2_vin_a5));
ANAND5C wb_2_vin_gate6( .A1(wb_2_vin_a1), .A2(wb_2_vin_a2),
.A3(wb_2_vin_a3), .A4(wb_2_vin_a4), .A5(wb_2_vin_a5), .O(wb_2_vin));
// assign wb_3_vin =
wire wb_3_vin_a5
, wb_3_vin_a4
, wb_3_vin_a3
, wb_3_vin_a2
, wb_3_vin_a1
;
JNAND3B wb_3_vin_gate1( .A1(~wb_3_vin_cancel), .A2(wb_shift_out),
.A3(wb_2_vout), .O(wb_3_vin_a1));
ANAND5C wb_3_vin_gate2( .A1(~wb_3_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_3_vout),.A5(release_hold), .O(wb_3_vin_a2));
JNAND4C wb_3_vin_gate3( .A1(~wb_3_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(release_hold), .O(wb_3_vin_a3));
ANAND5C wb_3_vin_gate4( .A1(~wb_3_vin_cancel), .A2(wb_shift_out),
.A3(st_op_wb_e), .A4(wb_3_vout),.A5(iu_held_l), .O(wb_3_vin_a4));
JNAND4C wb_3_vin_gate5( .A1(~wb_3_vin_cancel), .A2(~wb_shift_out),
.A3(st_op_wb_e), .A4(iu_held_l), .O(wb_3_vin_a5));
ANAND5C wb_3_vin_gate6( .A1(wb_3_vin_a1), .A2(wb_3_vin_a2),
.A3(wb_3_vin_a3), .A4(wb_3_vin_a4), .A5(wb_3_vin_a5), .O(wb_3_vin));
//--------------------------------------------------------------------------------
assign wb_shift_out = mm_wbstb ;
// wb buffer full signal, will hold the iu pipe.
assign wb_full = wb_0_vout & wb_1_vout & wb_2_vout & wb_3_vout;
assign wb_empty = ~(wb_0_vout | wb_1_vout | wb_2_vout | wb_3_vout) ;
// Tristate enable's .. (higher word with mm_wbsel1)
Mflipflop_r wb_sel_ff (wbsel_hi
, mm_wbsel1, ~wb_reset, wb_clk);
function [63:0] swapit;
input [63:0] din;
input little_endian;
begin
casex(little_endian)
1'b0: swapit = din;
1'b1: begin
swapit[7:0] = din [63:56];
swapit[15:8] = din [55:48];
swapit[23:16] = din [47:40];
swapit[31:24] = din [39:32];
swapit[39:32] = din [31:24];
swapit[47:40] = din [23:16];
swapit[55:48] = din [15:8];
swapit[63:56] = din [7:0];
end
endcase
end
endfunction
wire [63:0] wb_3_swap
= swapit(wb_3_out,little_endian);
wire [31:00] wb_out
= wbsel_hi ? wb_3_swap[63:32] : wb_3_swap[31:0] ;
wire [31:00] dout_pre
;
tri_regen_32 wb_tri32_wbstben1 ( dout[31:0], wb_out , wb_clk,
mm_dcdaten_in, wb_reset);
// Outputs to the address portion of writebuffer.
assign wb0_hold_hi = ~hold_wb_0 ;
assign wb1_hold_hi = ~hold_wb_1 ;
assign wb2_hold_hi = ~hold_wb_2 ;
assign wb3_hold_hi = ~hold_wb_3 ;
assign wb_1_sel_lo = wb_0_vout ;
assign wb_2_sel_lo = wb_1_vout ;
assign wb_3_sel_lo = wb_2_vout ;
endmodule
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module Mflipflop_mux2_h_32
(out, in0, in1, select, enable_l, clock) ;
output [31:0] out
;
input [31:0] in0
, in1
;
input select
;
input enable_l
;
input clock
;
wire [31:0] mux_out
;
// Expanded macro begin.
// cmux2(Mux2_32bit, 32, out[31:0], in0[31:0], in1[31:0], sel1)
function [32:1] Mux2_32bit ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
Mux2_32bit = out_fn ;
end
endfunction
assign mux_out[31:0] = Mux2_32bit(in0[31:0], in1[31:0], select) ;
// Expanded macro end.
Mflipflop_h_32 ff(out, mux_out, enable_l, clock);
endmodule
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module Mflipflop_mux2_h_1
(out, in0, in1, select, enable_l, clock) ;
output out
;
input in0
, in1
;
input select
;
input enable_l
;
input clock
;
wire mux_out
;
// Expanded macro begin.
function Mux2_1bit ;
input in0_fn ;
input in1_fn ;
input select_fn ;
reg out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 1'bx;
endcase
Mux2_1bit = out_fn ;
end
endfunction
assign mux_out = Mux2_1bit(in0, in1, select) ;
// Expanded macro end.
Mflipflop_h_1 ff(out, mux_out, enable_l, clock);
endmodule
This page: |
Created: | Thu Aug 19 12:03:00 1999 |
| From: |
../../../sparc_v8/ssparc/cc/rl_dc_cntl/rtl/writebuffer.v
|