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Xilinx Answer #8327 : 2.1i Timing Analyzer : Memory leak when selecting custom sources
Xilinx Answer #7312 : Timing Analyzer 2.1i; 9500/XL: Custom Report for CPLD gives stack fault error (timingan.exe, mfc42.dll) or Process Exit Code 2
Xilinx Answer #7215 : 2.1i Timing Analyzer: Running Custom Analysis Report after running Advanced Analysis Report produces the same report.
Xilinx Answer #7082 : 2.1i: Timing Analyzer: Delay numbers not reported for pad to ifd/ofd to pad
Xilinx Answer #7013 : 2.1i; Timing Analyzer: Maximum Delay Path does not match Minimum Period value in Unconstrained section of Unconstrained Report
Xilinx Answer #6825 : 2.1i Timing Analyzer: TA only produces a summary report of constraints with no paths for advanced analysis.
Xilinx Answer #6566 : 2.1i Timing Analyzer: Does not accept decimal or negative values for temprature in prorating options
Xilinx Answer #6486 : 2.1i: Timing Analyzer: "Opening Design" dialog dissappears long before design is finished loading
Xilinx Answer #6485 : 2.1i: Timing Analyzer: Topic Does not exist for 'Run Macro' and 'About' GUI buttons.
Xilinx Answer #6392 : 2.1i: Timing Analyzer: Path items counts for twr file does not match the actual path items for designs with circuit loops.
Xilinx Answer #6390 : 2.1i: Timing Analyzer - Under the File menu, the Most Recent Updated (MRU) items are enabled even when the list is empty
Xilinx Answer #6316 : 2.1i: Timing Analyzer - The instruction at "0x5f40129c" referenced memory at "0x00000004". The memory could not be "read".
Xilinx Answer #6294 : Timing Analyzer 2.1i: Old filter settings are not removed
Xilinx Answer #6245 : 2.1i: Timing Analyzer: Blockram components are not listed in RAM Sources/Destinations element types.
Xilinx Answer #6226 : M1.5i/2.1i: Timing Analyzer: There is a limit to the number of paths reported per timing constraint, 4096.
Xilinx Answer #3285 : M1.5i/2.1i: Timing Analyzer reports "0 items analyzed" on a period constraint.
Xilinx Answer #2849 : M1.5i/2.1i: Timing Analyzer: How to save path filters for automatic processing?
Xilinx Answer #2673 : M1.3/M1.4/M1.5/2.1i: TIMING ANALYZER, XILINX DESIGN MANAGER, LBGUI, PROMFMTR, on Solaris: core dumps may be due to 97A Verilog XNLSPATH settings