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Xilinx Answer #7358 : 2.1i Constraints Editor Can't Add Configuration Pins for FG676 & FG680
Xilinx Answer #7235 : 2.1i: Constraints Editor: Spartan PQ208 Prohibit IO locations for config pins are incorrect
Xilinx Answer #7050 : 2.1i: Constraints Editor: An application error has occured and ... Constraint_editor.exe
Xilinx Answer #6848 : Constraints Editor 2.1i: TNM_NET is written twice in UCF
Xilinx Answer #6755 : 2.1i; Constraints Editor: CE is concatenating constraints causing an invalid UCF
Xilinx Answer #6710 : 2.1i: Constraints Editor; Constraints w/out quotes are interpreted as source constraints.
Xilinx Answer #6577 : 2.1i: Constraints Editor: From NGD, only first period constraint is being displayed by CE.
Xilinx Answer #6404 : M1.5/2.1i: Constraints Editor: Can I specify NODELAY?
Xilinx Answer #6388 : 2.1i: Constraints Editor: Can't override TSid from a source constraint
Xilinx Answer #6387 : 2.1i: Constraints Editor - Cannot remove point from existing FROM/THRU/TO constraint
Xilinx Answer #6386 : 2.1i: Constraints Editor - Can not create relative FROM PADS TO PADS constraints in the FROM/THRU/TO dialog
Xilinx Answer #6385 : 2.1i: Constraints Editor - Only first of several similar constraints placed in the editable constraints window
Xilinx Answer #6384 : 2.1i: Constraints Editor - Wildcard symbol " * " is not supported by Constraints Editor
Xilinx Answer #6383 : 2.1i: Constraints Editor - TIMESPEC TSxx = FROM(abc) TO(xyz) - WARNING : Unable to create FROM TO with tsxx
Xilinx Answer #6382 : 2.1i: Constraints Editor - Pad-to-Pad Dialog allows creation of duplicate timespec names
Xilinx Answer #6381 : 2.1i: Constraints Editor: FROM TO dialog doesn't allow open ended FROM TOs.
Xilinx Answer #6380 : 2.1i: Constraints Editor: Pad group pulldown lists all groups instead of just pad groups
Xilinx Answer #6357 : 2.1i: Constraints Editor issues false warning (NgdHelpers: 488)
Xilinx Answer #6355 : 2.1i: Constraints Editor: PULLUP/PULLDOWN constraints from the NGD file are not displayed.
Xilinx Answer #6130 : M1.5/2.1i: Constraint Editor : unable to find clock signal in global tab
Xilinx Answer #4660 : M1.5/2.1i: Constraints Editor: baste:262-bad format for LOC constraint
Xilinx Answer #4505 : M1.5/2.1i: Constraints Editor: PORTS window doesn't scroll properly (vertically)
Xilinx Answer #4461 : 2.1i: Constraint Editor: Can't find Clock Enable net when All Nets is selected.