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Xilinx Answer #8406 : 2.1i Virtex Constraints Editor: Drive strength constraints is ignored. (FPGA Express only)
Xilinx Answer #8398 : Foundation 2.1i: Timing simulation of Virtex DLL fails when input frequency is higher than 100MHz
Xilinx Answer #7748 : 2.1i: Timing: No OFF->PAD paths in the data sheet style report
Xilinx Answer #7378 : 1.5i/2.1i: Hierarchical constraints with dc2ncf are not supported
Xilinx Answer #6965 : 2.1i 4KE/Spartan Timing - There is a known case where back annotated xc4000e and Spartan delays are under reported.
Xilinx Answer #6964 : 2.1i Virtex Timing - There are two known issues where back annotated Virtex timing under reports delay.
Xilinx Answer #6905 : 2.1i CE/Timing: How to apply a Period constraint on Virtex CLKDLL for 2.1i
Xilinx Answer #6662 : M1.5i/2.1i: Timing: Instantiated TDO Pad Conflicts With UCF Constraint Causing error baste:263
Xilinx Answer #6446 : 2.1i: Timing: Offset out/before won't find clock period in calculating the timing values.
Xilinx Answer #6442 : 2.1i: FPGA Editor - Is there a way to add a TSID to the list of constraints in FPGA Editor?
Xilinx Answer #6437 : 2.1i: FPGA Editor: Path constraint functionality is not supported.
Xilinx Answer #6416 : 2.1i: FPGA Editor: ERROR:FPGAEditor:285 - Cannot alter a global period constraint via a new attribute.
Xilinx Answer #6321 : 2.1i: Timing - Default Analysis and Advanced Analysis report maximum frequency differently
Xilinx Answer #6067 : M1.5i/2.1i: How to obtain timing information from new speedfiles: Speedprint utility
Xilinx Answer #6066 : M1.5i/2.1i: RISING and FALLING constraint grouping does not filter out non-FF elements
Xilinx Answer #5965 : M1.5i/2.1i; Timing: PERIOD constraint analyzes path from a FROM:THRU:TO spec
Xilinx Answer #5859 : M2.1i: Specifying PULLUPs/PULLDOWNs in UCF
Xilinx Answer #5747 : M1.5i/2.1i: UCF priority
Xilinx Answer #5489 : M1.5i/2.1i: Timing: How the OFFSET IN and OUT calculation is made?
Xilinx Answer #5121 : M1.5i/2.1i: Timing: Explaination of a Timing Report File (.TWR)
Xilinx Answer #4978 : M1.5i/2.1i: What are the resources that needs to be constrained in the user constraint file?
Xilinx Answer #4839 : 2.1i: Timing: OFFSET in/after and out/before give negative values in timing report
Xilinx Answer #4823 : 2.1i: Timing: How is the Setup/Hold Times calculated for the Datasheet IO Report?
Xilinx Answer #4624 : M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP
Xilinx Answer #4188 : M1.5i/2.1i: Timing Report: There is no negative offset, setup, or hold time
Xilinx Answer #4161 : M1.5i/2.1i: Cannot TIMESPEC the TDO/MD1 pin on XC4000E/X FPGAs.
Xilinx Answer #4136 : 2.1i: How to initialize the contents of a RAM primitive via a constraint file
Xilinx Answer #4028 : M1.5i/2.1i :Post Layout Timing Report: No skew warning given for internal clocks
Xilinx Answer #3753 : M1.5i/2.1i: Constraints: UCF to PCF conversion examples
Xilinx Answer #2586 : 2.1i: CE/Timing: VIRTEX CLKDLL TIMING for 2.1i
Xilinx Answer #2339 : M1.5i/2.1i; CPLD: TIG (Ignore Timing) timing constraint not supported
Xilinx Answer #800 : M1.5i/2.1i: Constraints: TNM's cannot be attached to tri-stated output flip flops (OFDT) via the TIMEGRP statement.