// register flush_done first
reg r_flush_done
;
reg [`TLBTAG_WIDTH-1:0] tlb_t_tag;
always @(posedge tg_stb_clk) begin
r_flush_done = `MMU_CNTL.tw_sm.flush_done;
end
// connect the external wire here
reg flush_t_ioall;
always @(posedge clk) begin
flush_t_ioall = `MMU_CNTL.tw_sm.flush_ioall;
end
wire flush_t_seg = `MMU_CNTL.tw_sm.flush_tlb_seg;
wire flush_t_reg = `MMU_CNTL.tw_sm.flush_tlb_reg;
wire flush_t_ctx = `MMU_CNTL.tw_sm.flush_tlb_ctx;
wire flush_t_all = `MMU_CNTL.tw_sm.flush_tlb_all;
wire vptp_mode = `MMU_CNTL.tw_sm.virt_ptp2;
wire flush_t_iopte = `MMU_CNTL.tw_sm.flush_iopte;
always @(negedge tg_stb_clk) begin
if ( r_flush_done ) begin
if ( flush_t_seg | flush_t_reg | flush_t_ctx ) begin
for(i=0; i<`TLBENTRIES ; i=i+1) begin : ptp_check
case(i)
0: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag00_out;
1: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag01_out;
2: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag02_out;
3: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag03_out;
4: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag04_out;
5: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag05_out;
6: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag06_out;
7: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag07_out;
8: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag08_out;
9: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag09_out;
10: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag10_out;
11: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag11_out;
12: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag12_out;
13: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag13_out;
14: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag14_out;
15: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag15_out;
16: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag16_out;
17: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag17_out;
18: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag18_out;
19: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag19_out;
20: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag20_out;
21: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag21_out;
22: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag22_out;
23: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag23_out;
24: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag24_out;
25: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag25_out;
26: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag26_out;
27: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag27_out;
28: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag28_out;
29: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag29_out;
30: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag30_out;
31: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag31_out;
// 32: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag32_out;
// 33: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag33_out;
// 34: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag34_out;
// 35: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag35_out;
// 36: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag36_out;
// 37: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag37_out;
// 38: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag38_out;
// 39: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag39_out;
// 40: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag40_out;
// 41: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag41_out;
// 42: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag42_out;
// 43: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag43_out;
// 44: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag44_out;
// 45: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag45_out;
// 46: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag46_out;
// 47: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag47_out;
// 48: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag48_out;
// 49: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag49_out;
// 50: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag50_out;
// 51: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag51_out;
// 52: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag52_out;
// 53: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag53_out;
// 54: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag54_out;
// 55: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag55_out;
// 56: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag56_out;
// 57: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag57_out;
// 58: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag58_out;
// 59: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag59_out;
// 60: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag60_out;
// 61: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag61_out;
// 62: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag62_out;
// 63: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag63_out;
endcase
if (tlb_t_tag[`PTP_BIT] && tlb_t_tag[`VALIDBIT] && tlb_t_tag[`IO_PTE]) begin
$display("*** vptp entry left at %0d : after cntx, reg, or seg flush ",i);
$display("%h",tlb_t_tag);
Mclocks.error_count = Mclocks.error_count + 1 ;
disable ptp_check;
end
else if (tlb_t_tag[`PTP_BIT] && tlb_t_tag[`VALIDBIT]) begin
$display("*** ptp entry left at %0d : after cntx, reg, or seg flush ",i);
$display("%h",tlb_t_tag);
Mclocks.error_count = Mclocks.error_count + 1 ;
disable ptp_check;
end
end
end
if ( flush_t_all ) begin
for(i=0; i<`TLBENTRIES ; i=i+1) begin : valid_check
case(i)
0: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag00_out;
1: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag01_out;
2: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag02_out;
3: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag03_out;
4: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag04_out;
5: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag05_out;
6: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag06_out;
7: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag07_out;
8: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag08_out;
9: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag09_out;
10: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag10_out;
11: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag11_out;
12: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag12_out;
13: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag13_out;
14: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag14_out;
15: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag15_out;
16: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag16_out;
17: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag17_out;
18: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag18_out;
19: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag19_out;
20: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag20_out;
21: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag21_out;
22: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag22_out;
23: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag23_out;
24: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag24_out;
25: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag25_out;
26: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag26_out;
27: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag27_out;
28: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag28_out;
29: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag29_out;
30: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag30_out;
31: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag31_out;
// 32: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag32_out;
// 33: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag33_out;
// 34: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag34_out;
// 35: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag35_out;
// 36: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag36_out;
// 37: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag37_out;
// 38: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag38_out;
// 39: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag39_out;
// 40: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag40_out;
// 41: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag41_out;
// 42: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag42_out;
// 43: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag43_out;
// 44: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag44_out;
// 45: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag45_out;
// 46: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag46_out;
// 47: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag47_out;
// 48: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag48_out;
// 49: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag49_out;
// 50: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag50_out;
// 51: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag51_out;
// 52: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag52_out;
// 53: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag53_out;
// 54: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag54_out;
// 55: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag55_out;
// 56: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag56_out;
// 57: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag57_out;
// 58: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag58_out;
// 59: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag59_out;
// 60: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag60_out;
// 61: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag61_out;
// 62: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag62_out;
// 63: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag63_out;
endcase
if ( tlb_t_tag[`VALIDBIT] ) begin
$display("*** first valid left at %0d : after flush all ",i);
Mclocks.error_count = Mclocks.error_count + 1 ;
disable valid_check;
end
end
end
end
end
wire flush_ioall_cycle = flush_op & flush_t_ioall;
reg flush_ioall_cycle_reg;
always @(posedge tg_stb_clk) begin
flush_ioall_cycle_reg = flush_ioall_cycle;
end
always @(negedge tg_stb_clk) begin
if (flush_ioall_cycle_reg) begin
for(i=0; i<`TLBENTRIES ; i=i+1) begin : iopte_check
case(i)
0: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag00_out;
1: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag01_out;
2: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag02_out;
3: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag03_out;
4: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag04_out;
5: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag05_out;
6: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag06_out;
7: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag07_out;
8: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag08_out;
9: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag09_out;
10: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag10_out;
11: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag11_out;
12: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag12_out;
13: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag13_out;
14: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag14_out;
15: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag15_out;
16: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag16_out;
17: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag17_out;
18: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag18_out;
19: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag19_out;
20: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag20_out;
21: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag21_out;
22: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag22_out;
23: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag23_out;
24: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag24_out;
25: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag25_out;
26: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag26_out;
27: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag27_out;
28: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag28_out;
29: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag29_out;
30: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag30_out;
31: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag31_out;
// 32: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag32_out;
// 33: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag33_out;
// 34: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag34_out;
// 35: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag35_out;
// 36: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag36_out;
// 37: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag37_out;
// 38: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag38_out;
// 39: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag39_out;
// 40: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag40_out;
// 41: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag41_out;
// 42: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag42_out;
// 43: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag43_out;
// 44: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag44_out;
// 45: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag45_out;
// 46: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag46_out;
// 47: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag47_out;
// 48: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag48_out;
// 49: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag49_out;
// 50: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag50_out;
// 51: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag51_out;
// 52: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag52_out;
// 53: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag53_out;
// 54: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag54_out;
// 55: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag55_out;
// 56: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag56_out;
// 57: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag57_out;
// 58: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag58_out;
// 59: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag59_out;
// 60: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag60_out;
// 61: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag61_out;
// 62: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag62_out;
// 63: tlb_t_tag = `MMU.MMU_tlb.TLB_cam.tag63_out;
endcase
if (tlb_t_tag[`VALIDBIT] && tlb_t_tag[`IO_PTE]) begin
$display("*** iopte entry left at %0d : after iopte flush all",i);
$display("%h",tlb_t_tag);
Mclocks.error_count = Mclocks.error_count + 1 ;
disable iopte_check;
end
end
end
end
`endif
// synopsys translate_on
/**************** ram write addres decode and WE cntrol **************/
// if direct read or write , we put ram address as decode address .
// if not , we put is to default address which is 00
assign ram_address = ( asel_reg ) ? decode(addr_reg) :
((match_op | flush_op) & ~rst_reg ) ? hit : 32'h00000000;
// ((match_op | flush_op) & ~rst_reg ) ? hit : 64'h0000000000000000;
/*****************************************************************************/
// Direct write operation
// tag write is asserted directly from tag_hld to cam line input
// switch ram write control off if this is not a write operation
// tag_hld assert when tlb_write-op is true , in order to finish write
// in clk = 0 cycle. I use the ~clk to be the cam cell clk
assign ram_write = tlb_write_op;
/****************************************************************************/
// Direct addressed cam read.
// If clk is low and cam_read_op is decode .
// emulation cam pre-charge high
//
wire [41:0] cd_out = (cam_read_op) ? tlb_tag :
(~cam_read_c1) ? c_data_in_reg : 42'h3ffffffffff;
/****************************************************************************/
// Direct addressed ram read.and compare read & flush status output
//
// if none of ram_read_op or match_op , we set it to o.k. in 1 for synopsys
// DIRECT ram read equation
// if (ram_read_op) begin
// acc_ok_reg = 1'b1;
// error_reg = 1'b0;
// miss_reg = 1'b0;
// m_miss_reg = 1'b0;
// end
/******************************************************************************/
// CAM match detect. Could be doing either a content-addressed read,
// or a flush. In either case, first see if we get a tag match.
// if ((match_op | flush_op) & ~rst_reg) begin
// miss_reg = ~(|(hit[63:0])) ;
// error_reg = |(err[63:0]) ;
// m_ok_reg = |(m_ok[63:0]) ;
// m_miss_reg = miss_reg | ~m_ok_reg;
// acc_ok_reg = m_ok_reg & ~error_reg & ~miss_reg ;
// end
// wire miss = ((match_op | flush_op) & ~rst_reg) & ~(|(hit[63:0]));
wire miss = ((match_op | flush_op) & ~rst_reg) & ~(|(hit[31:0]));
// wire error = ((match_op | flush_op) & ~rst_reg) & (|(err[63:0]));
wire error = ((match_op | flush_op) & ~rst_reg) & (|(err[31:0]));
// wire m_ok_reg = ~((match_op | flush_op) & ~rst_reg) | (|(m_ok[63:0]));
wire m_ok_reg = ~((match_op | flush_op) & ~rst_reg) | (|(m_ok[31:0]));
wire acc_ok = ~((match_op | flush_op) & ~rst_reg) | (m_ok_reg & ~error & ~miss);
wire m_miss = ((match_op | flush_op) & ~rst_reg) & (miss | ~m_ok_reg);
///////////////////////////////////////////////////////////////////////////////
// decoder ( 6-64 decoder )
function [31:0] decode;
// function [63:0] decode;
// input [5:0] input_addr;
input [4:0] input_addr;
// reg [63:0] count;
reg [31:0] count;
integer k;
begin
count = 0;
// for (k=0; k <= 63; k=k+1)
for (k=0; k <= 31; k=k+1)
if (k == input_addr)
count[k] = 1'b1;
decode = count;
end
endfunction
/********************** start cam block **************************/
/****************************************************************************/
/*** Instantiate CAM lines ***/
wire flush_real = flush_reg & ~scm;
wire co_in_real = co_in_reg & ~scm;
CAM_LINE tag00(hit[00],err[00],m_ok[00],tag00_out,
c_data_in_reg,tg_stb_clk,tag_hld[00],flush_real,co_in_real) ;
CAM_LINE tag01(hit[01],err[01],m_ok[01],tag01_out,
c_data_in_reg,tg_stb_clk,tag_hld[01],flush_real,co_in_real) ;
CAM_LINE tag02(hit[02],err[02],m_ok[02],tag02_out,
c_data_in_reg,tg_stb_clk,tag_hld[02],flush_real,co_in_real) ;
CAM_LINE tag03(hit[03],err[03],m_ok[03],tag03_out,
c_data_in_reg,tg_stb_clk,tag_hld[03],flush_real,co_in_real) ;
CAM_LINE tag04(hit[04],err[04],m_ok[04],tag04_out,
c_data_in_reg,tg_stb_clk,tag_hld[04],flush_real,co_in_real) ;
CAM_LINE tag05(hit[05],err[05],m_ok[05],tag05_out,
c_data_in_reg,tg_stb_clk,tag_hld[05],flush_real,co_in_real) ;
CAM_LINE tag06(hit[06],err[06],m_ok[06],tag06_out,
c_data_in_reg,tg_stb_clk,tag_hld[06],flush_real,co_in_real) ;
CAM_LINE tag07(hit[07],err[07],m_ok[07],tag07_out,
c_data_in_reg,tg_stb_clk,tag_hld[07],flush_real,co_in_real) ;
CAM_LINE tag08(hit[08],err[08],m_ok[08],tag08_out,
c_data_in_reg,tg_stb_clk,tag_hld[08],flush_real,co_in_real) ;
CAM_LINE tag09(hit[09],err[09],m_ok[09],tag09_out,
c_data_in_reg,tg_stb_clk,tag_hld[09],flush_real,co_in_real) ;
CAM_LINE tag10(hit[10],err[10],m_ok[10],tag10_out,
c_data_in_reg,tg_stb_clk,tag_hld[10],flush_real,co_in_real) ;
CAM_LINE tag11(hit[11],err[11],m_ok[11],tag11_out,
c_data_in_reg,tg_stb_clk,tag_hld[11],flush_real,co_in_real) ;
CAM_LINE tag12(hit[12],err[12],m_ok[12],tag12_out,
c_data_in_reg,tg_stb_clk,tag_hld[12],flush_real,co_in_real) ;
CAM_LINE tag13(hit[13],err[13],m_ok[13],tag13_out,
c_data_in_reg,tg_stb_clk,tag_hld[13],flush_real,co_in_real) ;
CAM_LINE tag14(hit[14],err[14],m_ok[14],tag14_out,
c_data_in_reg,tg_stb_clk,tag_hld[14],flush_real,co_in_real) ;
CAM_LINE tag15(hit[15],err[15],m_ok[15],tag15_out,
c_data_in_reg,tg_stb_clk,tag_hld[15],flush_real,co_in_real) ;
CAM_LINE tag16(hit[16],err[16],m_ok[16],tag16_out,
c_data_in_reg,tg_stb_clk,tag_hld[16],flush_real,co_in_real) ;
CAM_LINE tag17(hit[17],err[17],m_ok[17],tag17_out,
c_data_in_reg,tg_stb_clk,tag_hld[17],flush_real,co_in_real) ;
CAM_LINE tag18(hit[18],err[18],m_ok[18],tag18_out,
c_data_in_reg,tg_stb_clk,tag_hld[18],flush_real,co_in_real) ;
CAM_LINE tag19(hit[19],err[19],m_ok[19],tag19_out,
c_data_in_reg,tg_stb_clk,tag_hld[19],flush_real,co_in_real) ;
CAM_LINE tag20(hit[20],err[20],m_ok[20],tag20_out,
c_data_in_reg,tg_stb_clk,tag_hld[20],flush_real,co_in_real) ;
CAM_LINE tag21(hit[21],err[21],m_ok[21],tag21_out,
c_data_in_reg,tg_stb_clk,tag_hld[21],flush_real,co_in_real) ;
CAM_LINE tag22(hit[22],err[22],m_ok[22],tag22_out,
c_data_in_reg,tg_stb_clk,tag_hld[22],flush_real,co_in_real) ;
CAM_LINE tag23(hit[23],err[23],m_ok[23],tag23_out,
c_data_in_reg,tg_stb_clk,tag_hld[23],flush_real,co_in_real) ;
CAM_LINE tag24(hit[24],err[24],m_ok[24],tag24_out,
c_data_in_reg,tg_stb_clk,tag_hld[24],flush_real,co_in_real) ;
CAM_LINE tag25(hit[25],err[25],m_ok[25],tag25_out,
c_data_in_reg,tg_stb_clk,tag_hld[25],flush_real,co_in_real) ;
CAM_LINE tag26(hit[26],err[26],m_ok[26],tag26_out,
c_data_in_reg,tg_stb_clk,tag_hld[26],flush_real,co_in_real) ;
CAM_LINE tag27(hit[27],err[27],m_ok[27],tag27_out,
c_data_in_reg,tg_stb_clk,tag_hld[27],flush_real,co_in_real) ;
CAM_LINE tag28(hit[28],err[28],m_ok[28],tag28_out,
c_data_in_reg,tg_stb_clk,tag_hld[28],flush_real,co_in_real) ;
CAM_LINE tag29(hit[29],err[29],m_ok[29],tag29_out,
c_data_in_reg,tg_stb_clk,tag_hld[29],flush_real,co_in_real) ;
CAM_LINE tag30(hit[30],err[30],m_ok[30],tag30_out,
c_data_in_reg,tg_stb_clk,tag_hld[30],flush_real,co_in_real) ;
CAM_LINE tag31(hit[31],err[31],m_ok[31],tag31_out,
c_data_in_reg,tg_stb_clk,tag_hld[31],flush_real,co_in_real) ;
//CAM_LINE tag32(hit[32],err[32],m_ok[32],tag32_out,
// c_data_in_reg,tg_stb_clk,tag_hld[32],flush_real,co_in_real) ;
//CAM_LINE tag33(hit[33],err[33],m_ok[33],tag33_out,
// c_data_in_reg,tg_stb_clk,tag_hld[33],flush_real,co_in_real) ;
//CAM_LINE tag34(hit[34],err[34],m_ok[34],tag34_out,
// c_data_in_reg,tg_stb_clk,tag_hld[34],flush_real,co_in_real) ;
//CAM_LINE tag35(hit[35],err[35],m_ok[35],tag35_out,
// c_data_in_reg,tg_stb_clk,tag_hld[35],flush_real,co_in_real) ;
//CAM_LINE tag36(hit[36],err[36],m_ok[36],tag36_out,
// c_data_in_reg,tg_stb_clk,tag_hld[36],flush_real,co_in_real) ;
//CAM_LINE tag37(hit[37],err[37],m_ok[37],tag37_out,
// c_data_in_reg,tg_stb_clk,tag_hld[37],flush_real,co_in_real) ;
//CAM_LINE tag38(hit[38],err[38],m_ok[38],tag38_out,
// c_data_in_reg,tg_stb_clk,tag_hld[38],flush_real,co_in_real) ;
//CAM_LINE tag39(hit[39],err[39],m_ok[39],tag39_out,
// c_data_in_reg,tg_stb_clk,tag_hld[39],flush_real,co_in_real) ;
//CAM_LINE tag40(hit[40],err[40],m_ok[40],tag40_out,
// c_data_in_reg,tg_stb_clk,tag_hld[40],flush_real,co_in_real) ;
//CAM_LINE tag41(hit[41],err[41],m_ok[41],tag41_out,
// c_data_in_reg,tg_stb_clk,tag_hld[41],flush_real,co_in_real) ;
//CAM_LINE tag42(hit[42],err[42],m_ok[42],tag42_out,
// c_data_in_reg,tg_stb_clk,tag_hld[42],flush_real,co_in_real) ;
//CAM_LINE tag43(hit[43],err[43],m_ok[43],tag43_out,
// c_data_in_reg,tg_stb_clk,tag_hld[43],flush_real,co_in_real) ;
//CAM_LINE tag44(hit[44],err[44],m_ok[44],tag44_out,
// c_data_in_reg,tg_stb_clk,tag_hld[44],flush_real,co_in_real) ;
//CAM_LINE tag45(hit[45],err[45],m_ok[45],tag45_out,
// c_data_in_reg,tg_stb_clk,tag_hld[45],flush_real,co_in_real) ;
//CAM_LINE tag46(hit[46],err[46],m_ok[46],tag46_out,
// c_data_in_reg,tg_stb_clk,tag_hld[46],flush_real,co_in_real) ;
//CAM_LINE tag47(hit[47],err[47],m_ok[47],tag47_out,
// c_data_in_reg,tg_stb_clk,tag_hld[47],flush_real,co_in_real) ;
//CAM_LINE tag48(hit[48],err[48],m_ok[48],tag48_out,
// c_data_in_reg,tg_stb_clk,tag_hld[48],flush_real,co_in_real) ;
//CAM_LINE tag49(hit[49],err[49],m_ok[49],tag49_out,
// c_data_in_reg,tg_stb_clk,tag_hld[49],flush_real,co_in_real) ;
//CAM_LINE tag50(hit[50],err[50],m_ok[50],tag50_out,
// c_data_in_reg,tg_stb_clk,tag_hld[50],flush_real,co_in_real) ;
//CAM_LINE tag51(hit[51],err[51],m_ok[51],tag51_out,
// c_data_in_reg,tg_stb_clk,tag_hld[51],flush_real,co_in_real) ;
//CAM_LINE tag52(hit[52],err[52],m_ok[52],tag52_out,
// c_data_in_reg,tg_stb_clk,tag_hld[52],flush_real,co_in_real) ;
//CAM_LINE tag53(hit[53],err[53],m_ok[53],tag53_out,
// c_data_in_reg,tg_stb_clk,tag_hld[53],flush_real,co_in_real) ;
//CAM_LINE tag54(hit[54],err[54],m_ok[54],tag54_out,
// c_data_in_reg,tg_stb_clk,tag_hld[54],flush_real,co_in_real) ;
//CAM_LINE tag55(hit[55],err[55],m_ok[55],tag55_out,
// c_data_in_reg,tg_stb_clk,tag_hld[55],flush_real,co_in_real) ;
//CAM_LINE tag56(hit[56],err[56],m_ok[56],tag56_out,
// c_data_in_reg,tg_stb_clk,tag_hld[56],flush_real,co_in_real) ;
//CAM_LINE tag57(hit[57],err[57],m_ok[57],tag57_out,
// c_data_in_reg,tg_stb_clk,tag_hld[57],flush_real,co_in_real) ;
//CAM_LINE tag58(hit[58],err[58],m_ok[58],tag58_out,
// c_data_in_reg,tg_stb_clk,tag_hld[58],flush_real,co_in_real) ;
//CAM_LINE tag59(hit[59],err[59],m_ok[59],tag59_out,
// c_data_in_reg,tg_stb_clk,tag_hld[59],flush_real,co_in_real) ;
//CAM_LINE tag60(hit[60],err[60],m_ok[60],tag60_out,
// c_data_in_reg,tg_stb_clk,tag_hld[60],flush_real,co_in_real) ;
//CAM_LINE tag61(hit[61],err[61],m_ok[61],tag61_out,
// c_data_in_reg,tg_stb_clk,tag_hld[61],flush_real,co_in_real) ;
//CAM_LINE tag62(hit[62],err[62],m_ok[62],tag62_out,
// c_data_in_reg,tg_stb_clk,tag_hld[62],flush_real,co_in_real) ;
//CAM_LINE tag63(hit[63],err[63],m_ok[63],tag63_out,
// c_data_in_reg,tg_stb_clk,tag_hld[63],flush_real,co_in_real) ;
/****** start to generate tlb_tag output ******/
/********* LEVEL 1 MUX ***************/
//wire [41:0] tag60_63_out;
//CMUX4W CMUX4W1(tag60_out,tag61_out,tag62_out,tag63_out,addr_reg[1:0],tag60_63_out);
//wire [41:0] tag56_59_out ;
//CMUX4W CMUX4W2(tag56_out,tag57_out,tag58_out,tag59_out,addr_reg[1:0],tag56_59_out);
//wire [41:0] tag52_55_out ;
//CMUX4W CMUX4W3(tag52_out,tag53_out,tag54_out,tag55_out,addr_reg[1:0],tag52_55_out);
//wire [41:0] tag48_51_out ;
//CMUX4W CMUX4W4(tag48_out,tag49_out,tag50_out,tag51_out,addr_reg[1:0],tag48_51_out);
//wire [41:0] tag44_47_out ;
//CMUX4W CMUX4W5(tag44_out,tag45_out,tag46_out,tag47_out,addr_reg[1:0],tag44_47_out);
//wire [41:0] tag40_43_out ;
//CMUX4W CMUX4W6(tag40_out,tag41_out,tag42_out,tag43_out,addr_reg[1:0],tag40_43_out);
//wire [41:0] tag36_39_out ;
//CMUX4W CMUX4W7(tag36_out,tag37_out,tag38_out,tag39_out,addr_reg[1:0],tag36_39_out);
//wire [41:0] tag32_35_out ;
//CMUX4W CMUX4W8(tag32_out,tag33_out,tag34_out,tag35_out,addr_reg[1:0],tag32_35_out);
wire [41:0] tag28_31_out ;
CMUX4W CMUX4W9(tag28_out,tag29_out,tag30_out,tag31_out,addr_reg[1:0],tag28_31_out);
wire [41:0] tag24_27_out ;
CMUX4W CMUX4W10(tag24_out,tag25_out,tag26_out,tag27_out,addr_reg[1:0],tag24_27_out);
wire [41:0] tag20_23_out ;
CMUX4W CMUX4W11(tag20_out,tag21_out,tag22_out,tag23_out,addr_reg[1:0],tag20_23_out);
wire [41:0] tag16_19_out ;
CMUX4W CMUX4W12(tag16_out,tag17_out,tag18_out,tag19_out,addr_reg[1:0],tag16_19_out);
wire [41:0] tag12_15_out ;
CMUX4W CMUX4W13(tag12_out,tag13_out,tag14_out,tag15_out,addr_reg[1:0],tag12_15_out);
wire [41:0] tag08_11_out ;
CMUX4W CMUX4W14(tag08_out,tag09_out,tag10_out,tag11_out,addr_reg[1:0],tag08_11_out);
wire [41:0] tag04_07_out ;
CMUX4W CMUX4W15(tag04_out,tag05_out,tag06_out,tag07_out,addr_reg[1:0],tag04_07_out);
wire [41:0] tag00_03_out ;
CMUX4W CMUX4W16(tag00_out,tag01_out,tag02_out,tag03_out,addr_reg[1:0],tag00_03_out);
/********* LEVEL 2 MUX ***************/
//wire [41:0] tag48_63_out ;
//CMUX4W CMUX4W17(tag48_51_out,tag52_55_out,tag56_59_out,tag60_63_out,addr_reg[3:2],tag48_63_out);
//wire [41:0] tag32_47_out ;
//CMUX4W CMUX4W18(tag32_35_out,tag36_39_out,tag40_43_out,tag44_47_out,addr_reg[3:2],tag32_47_out);
wire [41:0] tag16_31_out ;
CMUX4W CMUX4W19(tag16_19_out,tag20_23_out,tag24_27_out,tag28_31_out,addr_reg[3:2],tag16_31_out);
wire [41:0] tag00_15_out ;
CMUX4W CMUX4W20(tag00_03_out,tag04_07_out,tag08_11_out,tag12_15_out,addr_reg[3:2],tag00_15_out);
/********* LEVEL 1 MUX ***************/
// wire [41:0] tag00_63_out ;
// CMUX4W CMUX4W21(tag00_15_out,tag16_31_out,tag32_47_out,tag48_63_out,addr_reg[5:4],tag00_63_out);
wire [41:0] tag00_31_out ;
CMUX4W CMUX4W21(tag00_15_out,tag16_31_out,42'b0,42'b0,{1'b0,addr_reg[4]},tag00_31_out);
// assign tlb_tag = tag00_63_out;
assign tlb_tag = tag00_31_out;
/*** Decode address into separate hold lines ********************************/
// assign tag_hld = {(tlb_write_op & (addr_reg == 6'h3f)),
// (tlb_write_op & (addr_reg == 6'h3e)),
// (tlb_write_op & (addr_reg == 6'h3d)),
// (tlb_write_op & (addr_reg == 6'h3c)),
// (tlb_write_op & (addr_reg == 6'h3b)),
// (tlb_write_op & (addr_reg == 6'h3a)),
// (tlb_write_op & (addr_reg == 6'h39)),
// (tlb_write_op & (addr_reg == 6'h38)),
// (tlb_write_op & (addr_reg == 6'h37)),
// (tlb_write_op & (addr_reg == 6'h36)),
// (tlb_write_op & (addr_reg == 6'h35)),
// (tlb_write_op & (addr_reg == 6'h34)),
// (tlb_write_op & (addr_reg == 6'h33)),
// (tlb_write_op & (addr_reg == 6'h32)),
// (tlb_write_op & (addr_reg == 6'h31)),
// (tlb_write_op & (addr_reg == 6'h30)),
// (tlb_write_op & (addr_reg == 6'h2f)),
// (tlb_write_op & (addr_reg == 6'h2e)),
// (tlb_write_op & (addr_reg == 6'h2d)),
// (tlb_write_op & (addr_reg == 6'h2c)),
// (tlb_write_op & (addr_reg == 6'h2b)),
// (tlb_write_op & (addr_reg == 6'h2a)),
// (tlb_write_op & (addr_reg == 6'h29)),
// (tlb_write_op & (addr_reg == 6'h28)),
// (tlb_write_op & (addr_reg == 6'h27)),
// (tlb_write_op & (addr_reg == 6'h26)),
// (tlb_write_op & (addr_reg == 6'h25)),
// (tlb_write_op & (addr_reg == 6'h24)),
// (tlb_write_op & (addr_reg == 6'h23)),
// (tlb_write_op & (addr_reg == 6'h22)),
// (tlb_write_op & (addr_reg == 6'h21)),
// (tlb_write_op & (addr_reg == 6'h20)),
// (tlb_write_op & (addr_reg == 6'h1f)),
// (tlb_write_op & (addr_reg == 6'h1e)),
// (tlb_write_op & (addr_reg == 6'h1d)),
// (tlb_write_op & (addr_reg == 6'h1c)),
// (tlb_write_op & (addr_reg == 6'h1b)),
// (tlb_write_op & (addr_reg == 6'h1a)),
// (tlb_write_op & (addr_reg == 6'h19)),
// (tlb_write_op & (addr_reg == 6'h18)),
// (tlb_write_op & (addr_reg == 6'h17)),
// (tlb_write_op & (addr_reg == 6'h16)),
// (tlb_write_op & (addr_reg == 6'h15)),
// (tlb_write_op & (addr_reg == 6'h14)),
// (tlb_write_op & (addr_reg == 6'h13)),
// (tlb_write_op & (addr_reg == 6'h12)),
// (tlb_write_op & (addr_reg == 6'h11)),
// (tlb_write_op & (addr_reg == 6'h10)),
// (tlb_write_op & (addr_reg == 6'h0f)),
// (tlb_write_op & (addr_reg == 6'h0e)),
// (tlb_write_op & (addr_reg == 6'h0d)),
// (tlb_write_op & (addr_reg == 6'h0c)),
// (tlb_write_op & (addr_reg == 6'h0b)),
// (tlb_write_op & (addr_reg == 6'h0a)),
// (tlb_write_op & (addr_reg == 6'h09)),
// (tlb_write_op & (addr_reg == 6'h08)),
// (tlb_write_op & (addr_reg == 6'h07)),
// (tlb_write_op & (addr_reg == 6'h06)),
// (tlb_write_op & (addr_reg == 6'h05)),
// (tlb_write_op & (addr_reg == 6'h04)),
// (tlb_write_op & (addr_reg == 6'h03)),
// (tlb_write_op & (addr_reg == 6'h02)),
// (tlb_write_op & (addr_reg == 6'h01)),
// (tlb_write_op & (addr_reg == 6'h00)) } ;
assign tag_hld = {(tlb_write_op & (addr_reg == 5'h1f)),
(tlb_write_op & (addr_reg == 5'h1e)),
(tlb_write_op & (addr_reg == 5'h1d)),
(tlb_write_op & (addr_reg == 5'h1c)),
(tlb_write_op & (addr_reg == 5'h1b)),
(tlb_write_op & (addr_reg == 5'h1a)),
(tlb_write_op & (addr_reg == 5'h19)),
(tlb_write_op & (addr_reg == 5'h18)),
(tlb_write_op & (addr_reg == 5'h17)),
(tlb_write_op & (addr_reg == 5'h16)),
(tlb_write_op & (addr_reg == 5'h15)),
(tlb_write_op & (addr_reg == 5'h14)),
(tlb_write_op & (addr_reg == 5'h13)),
(tlb_write_op & (addr_reg == 5'h12)),
(tlb_write_op & (addr_reg == 5'h11)),
(tlb_write_op & (addr_reg == 5'h10)),
(tlb_write_op & (addr_reg == 5'h0f)),
(tlb_write_op & (addr_reg == 5'h0e)),
(tlb_write_op & (addr_reg == 5'h0d)),
(tlb_write_op & (addr_reg == 5'h0c)),
(tlb_write_op & (addr_reg == 5'h0b)),
(tlb_write_op & (addr_reg == 5'h0a)),
(tlb_write_op & (addr_reg == 5'h09)),
(tlb_write_op & (addr_reg == 5'h08)),
(tlb_write_op & (addr_reg == 5'h07)),
(tlb_write_op & (addr_reg == 5'h06)),
(tlb_write_op & (addr_reg == 5'h05)),
(tlb_write_op & (addr_reg == 5'h04)),
(tlb_write_op & (addr_reg == 5'h03)),
(tlb_write_op & (addr_reg == 5'h02)),
(tlb_write_op & (addr_reg == 5'h01)),
(tlb_write_op & (addr_reg == 5'h00)) } ;
endmodule
/**************************************************************************/
// no reset input anymore
// reverse scan order of mflipflop_sr_6
// module Mflipflop_s_6_r (out, din, scanen, sin, clock) ;
// output [5:0] out ;
// input [5:0] din ;
// input scanen ;
// input sin ;
// input clock ;
//
// Mflipflop_s Mflipflop_s_5_0 (out[0], din[0], scanen, sin, clock);
// Mflipflop_s Mflipflop_s_5_1 (out[1], din[1], scanen, out[0], clock);
// Mflipflop_s Mflipflop_s_5_2 (out[2], din[2], scanen, out[1], clock);
// Mflipflop_s Mflipflop_s_5_3 (out[3], din[3], scanen, out[2], clock);
// Mflipflop_s Mflipflop_s_5_4 (out[4], din[4], scanen, out[3], clock);
// Mflipflop_s Mflipflop_s_5_5 (out[5], din[5], scanen, out[4], clock);
//
// endmodule
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module Mflipflop_s_5_r (out, din, scanen, sin, clock) ;
output [4:0] out ;
input [4:0] din ;
input scanen ;
input sin ;
input clock ;
Mflipflop_s Mflipflop_s_5_0 (out[0], din[0], scanen, sin, clock);
Mflipflop_s Mflipflop_s_5_1 (out[1], din[1], scanen, out[0], clock);
Mflipflop_s Mflipflop_s_5_2 (out[2], din[2], scanen, out[1], clock);
Mflipflop_s Mflipflop_s_5_3 (out[3], din[3], scanen, out[2], clock);
Mflipflop_s Mflipflop_s_5_4 (out[4], din[4], scanen, out[3], clock);
endmodule
// reverse order of scan chain of sr_28 from 0 -> 27
module Mflipflop_s_28_r (out, din, scanen, sin, clock) ;
output [27:0] out ;
input [27:0] din ;
input scanen ;
input sin ;
input clock ;
Mflipflop_s Mflipflop_s_27_0 (out[0], din[0], scanen, sin, clock);
Mflipflop_s Mflipflop_s_27_1 (out[1], din[1], scanen, out[0], clock);
Mflipflop_s Mflipflop_s_27_2 (out[2], din[2], scanen, out[1], clock);
Mflipflop_s Mflipflop_s_27_3 (out[3], din[3], scanen, out[2], clock);
Mflipflop_s Mflipflop_s_27_4 (out[4], din[4], scanen, out[3], clock);
Mflipflop_s Mflipflop_s_27_5 (out[5], din[5], scanen, out[4], clock);
Mflipflop_s Mflipflop_s_27_6 (out[6], din[6], scanen, out[5], clock);
Mflipflop_s Mflipflop_s_27_7 (out[7], din[7], scanen, out[6], clock);
Mflipflop_s Mflipflop_s_27_8 (out[8], din[8], scanen, out[7], clock);
Mflipflop_s Mflipflop_s_27_9 (out[9], din[9], scanen, out[8], clock);
Mflipflop_s Mflipflop_s_27_10 (out[10], din[10], scanen, out[9], clock);
Mflipflop_s Mflipflop_s_27_11 (out[11], din[11], scanen, out[10], clock);
Mflipflop_s Mflipflop_s_27_12 (out[12], din[12], scanen, out[11], clock);
Mflipflop_s Mflipflop_s_27_13 (out[13], din[13], scanen, out[12], clock);
Mflipflop_s Mflipflop_s_27_14 (out[14], din[14], scanen, out[13], clock);
Mflipflop_s Mflipflop_s_27_15 (out[15], din[15], scanen, out[14], clock);
Mflipflop_s Mflipflop_s_27_16 (out[16], din[16], scanen, out[15], clock);
Mflipflop_s Mflipflop_s_27_17 (out[17], din[17], scanen, out[16], clock);
Mflipflop_s Mflipflop_s_27_18 (out[18], din[18], scanen, out[17], clock);
Mflipflop_s Mflipflop_s_27_19 (out[19], din[19], scanen, out[18], clock);
Mflipflop_s Mflipflop_s_27_20 (out[20], din[20], scanen, out[19], clock);
Mflipflop_s Mflipflop_s_27_21 (out[21], din[21], scanen, out[20], clock);
Mflipflop_s Mflipflop_s_27_22 (out[22], din[22], scanen, out[21], clock);
Mflipflop_s Mflipflop_s_27_23 (out[23], din[23], scanen, out[22], clock);
Mflipflop_s Mflipflop_s_27_24 (out[24], din[24], scanen, out[23], clock);
Mflipflop_s Mflipflop_s_27_25 (out[25], din[25], scanen, out[24], clock);
Mflipflop_s Mflipflop_s_27_26 (out[26], din[26], scanen, out[25], clock);
Mflipflop_s Mflipflop_s_27_27 (out[27], din[27], scanen, out[26], clock);
endmodule
/****************************************************************************/
/*** TLB CAM instantiation ***/
/*** define CAM_LINE module ***/
/*** Call CAM_LINE model 64 times ***/
/****************************************************************************/
module CAM_LINE(hit,err,m_ok,tag_out,tag_in,clk,hold,flush,co_in);
output hit;
output err;
output m_ok;
output [41:0] tag_out;
input [41:0] tag_in;
input clk;
input hold;
input flush;
input co_in;
wire valid_in = tag_in[41] ;
wire lvl0_in = tag_in[40] ;
wire [7:0] indx0_in = tag_in[39:32] ;
wire lvl1_in = tag_in[31] ;
wire [5:0] indx1_in = tag_in[30:25] ;
wire lvl2_in = tag_in[24] ;
wire [5:0] indx2_in = tag_in[23:18] ;
wire [7:0] cntxt_in = tag_in[17:10] ;
wire [5:0] prtct_in = tag_in[09:04] ;
wire sprvsr_in = tag_in[03] ;
wire iopte_in = tag_in[02] ;
wire ptp_in = tag_in[01] ;
wire mbit_in = tag_in[00] ;
//wire reset = (hit & flush) | co_in ;
wire reset = (hit & flush);
wire valid ;
MflipflopR_1 cam_line_v_1(valid,tag_in[41],clk,~hold,reset) ;
// hardcode to non-scan register
wire [40:0] tag_reg ;
//wire [40:0] tag_real_in = tag_in[40:0];
Mflipflop_h_32 cam_line_0_31(tag_reg[31:0],tag_in[31:0],~hold,~clk) ;
Mflipflop_h_9 cam_line_32_40(tag_reg[40:32],tag_in[40:32],~hold,~clk) ;
assign tag_out = {valid,tag_reg} ;
wire lvl0 = tag_reg[40] ;
wire [7:0] indx0 = tag_reg[39:32] ;
wire lvl1 = tag_reg[31] ;
wire [5:0] indx1 = tag_reg[30:25] ;
wire lvl2 = tag_reg[24] ;
wire [5:0] indx2 = tag_reg[23:18] ;
wire [7:0] cntxt = tag_reg[17:10] ;
wire [5:0] prtct = tag_reg[09:04] ;
wire sprvsr = tag_reg[03] ;
wire iopte = tag_reg[02] ;
wire ptp = tag_reg[01] ;
wire mbit = tag_reg[00] ;
wire hit_lvl02 = ( |indx0_in === 1'bx) &
(~(lvl1_in === 1'b0) | ~(lvl2_in === 1'b0) | ~(sprvsr_in === 1'b0));
wire hit_lvl12 = ( |indx1_in === 1'bx) &
(~(lvl0_in === 1'b0) | ~(lvl2_in === 1'b0) | ~(sprvsr_in === 1'b0));
wire hit_lvl22 = ( |indx2_in === 1'bx) &
(~(lvl0_in === 1'b0) | ~(lvl1_in === 1'b0) | ~(sprvsr_in === 1'b0));
wire hit_cntxt2 = ( |cntxt_in === 1'bx) &
(~(lvl0_in === 1'b0) | ~(lvl1_in === 1'b0) | ~(lvl2_in === 1'b0));
wire hit_lvl0 = (indx0_in === indx0) | ~(lvl0_in === 1'b0) | lvl0 | hit_lvl02;
wire hit_lvl1 = (indx1_in === indx1) | ~(lvl1_in === 1'b0) | lvl1 | hit_lvl12;
wire hit_lvl2 = (indx2_in === indx2) | ~(lvl2_in === 1'b0) | lvl2 | hit_lvl22;
wire hit_cntxt = (cntxt_in === cntxt) | ~(sprvsr_in === 1'b0) | sprvsr | hit_cntxt2;
wire hit_iopte = ~(~(iopte_in === 1'b0) ^ iopte) | co_in ;
wire hit_ptp = co_in | ~(~(ptp_in === 1'b0) ^ ptp) ;
assign hit = ~(valid === 1'b0) & hit_lvl0 & hit_lvl1 & hit_lvl2 & hit_cntxt &
hit_iopte & hit_ptp ;
assign err = hit & ((~prtct[5] & prtct_in[5]) |
(~prtct[4] & prtct_in[4]) |
(~prtct[3] & prtct_in[3]) |
(~prtct[2] & prtct_in[2]) |
(~prtct[1] & prtct_in[1]) |
(~prtct[0] & prtct_in[0])) ;
assign m_ok = hit & (mbit | (~prtct_in[3] & ~prtct_in[0])) ;
endmodule
module sram (
decoded_addr,
do,
di,
we,
flush_op,
miss,
clk
);
// input [63:0] decoded_addr;
input [31:0] decoded_addr;
input [`TLBDATA_WIDTH-1:0] di;
input we, flush_op, miss, clk;
integer i;
output [`TLBDATA_WIDTH-1:0] do;
// synopsys translate_off
// wire [5:0] addrx;
wire [4:0] addrx;
// TLB SRAM instantiated
reg [`TLBDATA_WIDTH-1:0] tlb_data [`TLBENTRIES-1:0] ;
initial begin
// for(i= 0; i<64;i = i + 1)
for(i= 0; i<32;i = i + 1)
tlb_data[i] = 28'bx;
end
// Generate active low WE pulse
wire we_ = ~(we & ~clk);
// Encode address
// assign addrx[5:0] = encode_address(decoded_addr[63:0]);
assign addrx[4:0] = encode_address(decoded_addr[31:0]);
// TLB SRAM read
assign do = (miss | flush_op) ? 28'bx : (we_ ? tlb_data[addrx] : di);
// TLB SRAM write
// implement to latch type
// level senative
always @ (negedge we_) begin
tlb_data[addrx] = di;
end
// speciall hardwire for debuing
/////////////////////////////////////////////////////////////////////
// This function should be in GCB
// encode_address:
//
// Encodes 64 wires into 6 bits, assuming that only one
// of the 64 inputs is high.
// Encodes 32 wires into 5 bits, assuming that only one
// of the 32 inputs is high.
// function [5:0] encode_address;
// input [63:0] decoded_addr;
// reg [5:0] encode_out;
function [4:0] encode_address;
input [31:0] decoded_addr;
reg [4:0] encode_out;
integer i;
begin
encode_out = 0;
// for (i = 0; i < 64; i = i + 1)
for (i = 0; i < 32; i = i + 1)
if (decoded_addr[i] == 1)
encode_out = i;
encode_address = encode_out;
end
endfunction
// synopsys translate_on
endmodule
module CMUX4W(in0_fn,in1_fn,in2_fn,in3_fn,select_fn,out_fna) ;
input [41:0] in0_fn ;
input [41:0] in1_fn ;
input [41:0] in2_fn ;
input [41:0] in3_fn ;
input [1:0] select_fn ;
output [41:0] out_fna ;
wire [41:0] out_fna = CMUX(in0_fn,in1_fn,in2_fn,in3_fn,select_fn);
function [41:0] CMUX ;
input [41:0] in0_fn ;
input [41:0] in1_fn ;
input [41:0] in2_fn ;
input [41:0] in3_fn ;
input [1:0] select_fn ;
reg [41:0] out_fn ;
begin
case (select_fn) //synopsys parallel_case full_case
2'b00: out_fn = in0_fn ;
2'b01: out_fn = in1_fn ;
2'b10: out_fn = in2_fn ;
2'b11: out_fn = in3_fn ;
endcase
CMUX = out_fn ;
end
endfunction
endmodule
module Mflipflop_s_6_old (out, din, scanen, sin, clock) ;
output [5:0] out ;
input [5:0] din ;
input scanen ;
input sin ;
input clock ;
Mflipflop_s Mflipflop_s_5_0 (out[0], din[0], scanen, out[1], clock);
Mflipflop_s Mflipflop_s_5_1 (out[1], din[1], scanen, out[2], clock);
Mflipflop_s Mflipflop_s_5_2 (out[2], din[2], scanen, out[3], clock);
Mflipflop_s Mflipflop_s_5_3 (out[3], din[3], scanen, out[4], clock);
Mflipflop_s Mflipflop_s_5_4 (out[4], din[4], scanen, out[5], clock);
Mflipflop_s Mflipflop_s_5_5 (out[5], din[5], scanen, sin, clock);
endmodule
module Mflipflop_s_8_old (out, din, scanen, sin, clock) ;
output [7:0] out ;
input [7:0] din ;
input scanen ;
input sin ;
input clock ;
Mflipflop_s Mflipflop_s_7_0 (out[0], din[0], scanen, out[1], clock);
Mflipflop_s Mflipflop_s_7_1 (out[1], din[1], scanen, out[2], clock);
Mflipflop_s Mflipflop_s_7_2 (out[2], din[2], scanen, out[3], clock);
Mflipflop_s Mflipflop_s_7_3 (out[3], din[3], scanen, out[4], clock);
Mflipflop_s Mflipflop_s_7_4 (out[4], din[4], scanen, out[5], clock);
Mflipflop_s Mflipflop_s_7_5 (out[5], din[5], scanen, out[6], clock);
Mflipflop_s Mflipflop_s_7_6 (out[6], din[6], scanen, out[7], clock);
Mflipflop_s Mflipflop_s_7_7 (out[7], din[7], scanen, sin, clock);
endmodule
module Mflipflop_s_2_old (out, din, scanen, sin, clock) ;
output [1:0] out ;
input [1:0] din ;
input scanen ;
input sin ;
input clock ;
| This page: |
Created: | Thu Aug 19 11:59:43 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/mc_tlb/rtl/mc_e_tlb.v
|