tri_regen_32 dtag_tri32 ( misc, r_mmu_data, ss_clock,
mmdaten, ss_reset);
/*****************************************************************************/
/* Trigger A control register (PA =0x10003000) */
/* */
/* +------------------+--------------------------------------------+---+---+ */
/* | reserved | Trigger A enables |AND| L | */
/* +------------------+--------------------------------------------+---+---+ */
/* 31 27 26 02 01 00 */
/* */
/* Bit Mnemoic Function */
/* ---- -------- --------- */
/* 00 L Trigger on EDGE (L=0) or LEVEL (L=1) */
/* 01 AND Combine triggers by AND (AND=1) or OR (AND=0) */
/* */
/* Cache triggers */
/* -------------- */
/* 02 IHLD I-cache hold trigger */
/* 03 IMSS I-cache miss trigger */
/* 04 ISTRM I-cache stream trigger */
/* 05 IFTCH I-cache fetch (cache lookup) */
/* 06 DHLD D-cache hold trigger */
/* 07 DMSS D-cache miss trigger */
/* 08 DSTRM D-cache stream trigger */
/* 09 DFTCH D-cache fetch (cache lookup) */
/* 10 WBHLD Write buffer hold trigger */
/* */
/* Memory triggers */
/* --------------- */
/* 11 MBSY Memory interface busy trigger */
/* 12 ABSY AFX interface busy trigger */
/* 13 MPAGE Memory page mode access trigger */
/* 14 MPRCG Memory precharge access trigger */
/* 15 MRMW Memory Read/Modify/Write operation trigger */
/* */
/* System triggers */
/* --------------- */
/* 16 XLTE MMU translation attempt trigger */
/* 17 SRTW SPARC Ref. MMU tablewalk trigger */
/* 18 SUP Supervisor mode access trigger */
/* 19 MMUBP MMU breakpoint trigger */
/* 20 STALL Processor stall trigger */
/* */
/* FPU triggers */
/* ------------ */
/* 21 FPHLD FPU pipeline hold trigger */
/* 22 FPQ FPU Queue full trigger */
/* */
/* DMA triggers */
/* ------------ */
/* 23 DMAR DMA request trigger */
/* 24 DMAT DMA translate trigger */
/* 25 DMAW DMA write trigger */
/* */
/* 26 CNTB Counter B carry out trigger */
/* */
/*****************************************************************************/
wire triga_hld
= ~(pa_reg_dcd & (mm_pa[15:00] == 16'h3000) & mmstben_reg) ;
wire [26:00] trig_ena;
MflipflopR_27 trig_ena_reg_27(trig_ena,misc_in[26:00],ss_clock,triga_hld,ss_reset) ;
/*****************************************************************************/
/* Trigger B control register (PA =0x10003004) */
/* */
/* +------------------+--------------------------------------------+---+---+ */
/* | reserved | Trigger B enables |AND| L | */
/* +------------------+--------------------------------------------+---+---+ */
/* 31 25 24 02 01 00 */
/* */
/* Bit Mnemoic Function */
/* ---- -------- --------- */
/* 00 L Trigger on EDGE (L=0) or LEVEL (L=1) */
/* 01 AND Combine triggers by AND (AND=1) or OR (AND=0) */
/* */
/* Cache triggers */
/* -------------- */
/* 02 IHLD I-cache hold trigger */
/* 03 IMSS I-cache miss trigger */
/* 04 ISTRM I-cache stream trigger */
/* 05 IFTCH I-cache fetch (cache lookup) */
/* 06 DHLD D-cache hold trigger */
/* 07 DMSS D-cache miss trigger */
/* 08 DSTRM D-cache stream trigger */
/* 09 DFTCH D-cache fetch (cache lookup) */
/* 10 WBHLD Write buffer hold trigger */
/* */
/* Memory triggers */
/* --------------- */
/* 11 MBSY Memory interface busy trigger */
/* 12 ABSY AFX interface busy trigger */
/* 13 MPAGE Memory page mode access trigger */
/* 14 MPRCG Memory precharge access trigger */
/* 15 MRMW Memory Read/Modify/Write operation trigger */
/* */
/* System triggers */
/* --------------- */
/* 16 XLTE MMU translation attempt trigger */
/* 17 SRTW SPARC Ref. MMU tablewalk trigger */
/* 18 SUP Supervisor mode access trigger */
/* 19 MMUBP MMU breakpoint trigger */
/* 20 STALL Processor stall trigger */
/* */
/* FPU triggers */
/* ------------ */
/* 21 FPHLD FPU pipeline hold trigger */
/* 22 FPQ FPU Queue full trigger */
/* */
/* DMA triggers */
/* ------------ */
/* 23 DMAR DMA request trigger */
/* 24 DMAT DMA translate trigger */
/* 25 DMAW DMA write trigger */
/* */
/* 26 CYC Cycle count trigger */
/* */
/*****************************************************************************/
wire trigb_hld = ~(pa_reg_dcd & (mm_pa[15:00] == 16'h3004) & mmstben_reg) ;
wire [26:00] trig_enb;
MflipflopR_27 trig_enb_reg_27(trig_enb,misc_in[26:00],ss_clock,trigb_hld,ss_reset) ;
/*****************************************************************************/
/* Assertion control register (PA =0x10003008) */
/* */
/* +---------------------+-----------------------------------------+-------+ */
/* | reserved | Trigger Assertion Control | rsvd | */
/* +---------------------+-----------------------------------------+-------+ */
/* 31 24 23 02 01 00 */
/* */
/* When bit is asserted, INVERT trigger. */
/* */
/* Bit Mnemoic Function */
/* ---- -------- --------- */
/* 00 Reserved (read as zero). */
/* 01 Reserved (read as zero). */
/* */
/* Cache assertions */
/* ---------------- */
/* 02 IHLD I-cache hold invert */
/* 03 IMSS I-cache miss invert */
/* 04 ISTRM I-cache stream invert */
/* 05 IFTCH I-cache fetch (cache lookup) */
/* 06 DHLD D-cache hold trigger */
/* 07 DMSS D-cache miss trigger */
/* 08 DSTRM D-cache stream trigger */
/* 09 DFTCH D-cache fetch (cache lookup) */
/* 10 WBHLD Write buffer hold trigger */
/* */
/* Memory triggers */
/* --------------- */
/* 11 MBSY Memory interface busy trigger */
/* 12 ABSY AFX interface busy trigger */
/* 13 MPAGE Memory page mode access trigger */
/* 14 MPRCG Memory precharge access trigger */
/* 15 MRMW Memory Read/Modify/Write operation trigger */
/* */
/* System triggers */
/* --------------- */
/* 16 XLTE MMU translation attempt trigger */
/* 17 SRTW SPARC Ref. MMU tablewalk trigger */
/* 18 SUP Supervisor mode access trigger */
/* 19 MMUBP MMU breakpoint trigger */
/* 20 STALL Processor stall trigger */
/* */
/* FPU triggers */
/* ------------ */
/* 21 FPHLD FPU pipeline hold trigger */
/* 22 FPQ FPU Queue full trigger */
/* */
/* DMA triggers */
/* ------------ */
/* 23 DMAR DMA request trigger */
/* 24 DMAT DMA translate trigger */
/* 25 DMAW DMA write trigger */
/* */
/*****************************************************************************/
wire trig_asrt_hld = ~(pa_reg_dcd & (mm_pa[15:00] == 16'h3008) & mmstben_reg) ;
wire [23:00] trig_asrt;
MflipflopR_24 trig_asrt_reg_24(trig_asrt,misc_in[25:02],ss_clock,trig_asrt_hld,ss_reset) ;
wire [25:00] assert = {trig_asrt, 2'b0} ; // pad to use same defines
/*****************************************************************************/
/*** Trigger decode logic ***/
parameter LVL = 0,
AND = 1,
IHLD = 2,
IMSS = 3,
ISTRM = 4,
IFTCH = 5,
DHLD = 6,
DMSS = 7,
DSTRM = 8,
DFTCH = 9,
WBHLD = 10,
MBSY = 11,
ABSY = 12,
MPAGE = 13,
MPRCG = 14,
MRMW = 15,
XLTE = 16,
SRTW = 17,
SUP = 18,
MMUBP = 19,
STALL = 20,
FPHLD = 21,
FPQ = 22,
DMAR = 23,
DMAT = 24,
DMAW = 25;
/*****************************************************************************/
/*** registers for late triggers from other blocks ***/
wire r_hold_fetch_f ;
Mflipflop_r_1 hold_fetch_f_1(r_hold_fetch_f,(~hold_fetch_f_l),~ss_reset,ss_clock) ;
wire ifetched = did_ifetch & ~r_hold_fetch_f ;
wire iacc_wp_e_in = iu_mm_iacc_wp_exc_d & ~iu_in_trap ;
MflipflopR_1 iacc_wp_ff_1(iacc_wp_e,iacc_wp_e_in,ss_clock,iu_pipe_hold,ss_reset) ;
wire r_ic_stream ;
Mflipflop_r_1 ic_stream_ff_1(r_ic_stream,ic_stream,~ss_reset,ss_clock) ;
wire r_dc_stream ;
Mflipflop_r_1 dc_stream_ff_1(r_dc_stream,dc_stream,~ss_reset,ss_clock) ;
wire r_dc_shold ;
Mflipflop_r_1 dc_shold_ff_1(r_dc_shold,dc_shold,~ss_reset,ss_clock) ;
wire r_dcmiss_sustain ;
MflipflopR_1 dc_miss_sustain_ff_1(r_dcmiss_sustain,dc_miss_sustain, ss_clock,1'b0,ss_reset) ;
wire r_icmiss_sustain ;
MflipflopR_1 ic_miss_sustain_ff_1(r_icmiss_sustain,ic_miss_sustain, ss_clock,1'b0,ss_reset) ;
wire page_hit = mm_page & mem_issue_req ;
wire r_page_hit ;
Mflipflop_r_1 page_hit_ff_1(r_page_hit,page_hit,~ss_reset,ss_clock) ;
wire precharge = (precharge_early_0 | precharge_early_1) ;
wire r_precharge ;
Mflipflop_r_1 precharge_ff_1(r_precharge,precharge,~ss_reset,ss_clock) ;
wire precharge_trig_in = r_precharge & mem_issue_req ;
wire precharge_trig ;
Mflipflop_r_1 precharge_trig_ff_1(precharge_trig,precharge_trig_in,~ss_reset,ss_clock) ;
wire [2:0] r_p_reply_dec ;
Mflipflop_r_3 r_p_reply_dec_ff_3(r_p_reply_dec,p_reply_dec,~ss_reset,ss_clock) ;
wire afx_busy = (r_dc_par | r_ic_par) & r_fb_space & afx_qbusy & ~r_mbsy ;
wire r_afx_bsy ;
Mflipflop_r_1 afx_busy_ff_1(r_afx_bsy,afx_busy,~ss_reset,ss_clock) ;
wire rmw_req = mem_issue_req & ((mm_mreq == 4'b1001) | (mm_mreq == 4'b1010)) ;
wire r_rmw_req ;
Mflipflop_r_1 rmw_req_ff_1(r_rmw_req,rmw_req,~ss_reset,ss_clock) ;
wire r_va_bp_hit ;
Mflipflop_r_1 va_hit_ff_1(r_va_bp_hit,mmulgc_bp_hit,~ss_reset,ss_clock) ;
wire r_sup_mode ;
Mflipflop_r_1 sup_mode_ff_1(r_sup_mode,iu_sup_mode,~ss_reset,ss_clock) ;
/*** Implement a hold on pcntr_b carry out. Hold until trig_a recognizes. ****/
wire trig_b_co ;
wire trig_b_co_in = pcntr_b_co | (trig_b_co & ~trig_a) ;
Mflipflop_r_1 trig_b_co_ff_1(trig_b_co,trig_b_co_in,~ss_reset,ss_clock) ;
/*** Trigger A decodes *******************************************************/
wire triga_or = (trig_ena[IHLD] & (assert[IHLD] ^ ihold_d1)) |
(trig_ena[IMSS] & (assert[IMSS] ^ r_icmiss_sustain)) |
(trig_ena[ISTRM] & (assert[ISTRM] ^ r_ic_stream)) |
(trig_ena[IFTCH] & (assert[IFTCH] ^ ifetched)) |
(trig_ena[DHLD] & (assert[DHLD] ^ dhold_d1)) |
(trig_ena[DMSS] & (assert[DMSS] ^ r_dcmiss_sustain)) |
(trig_ena[DSTRM] & (assert[DSTRM] ^ r_dc_stream)) |
(trig_ena[DFTCH] & (assert[DFTCH] ^ did_dfetch)) |
(trig_ena[WBHLD] & (assert[WBHLD] ^ r_dc_shold)) |
(trig_ena[MBSY] & (assert[MBSY] ^ r_mbsy)) |
(trig_ena[ABSY] & (assert[ABSY] ^ r_afx_bsy)) |
(trig_ena[MPAGE] & (assert[MPAGE] ^ r_page_hit)) |
(trig_ena[MPRCG] & (assert[MPRCG] ^ precharge_trig)) |
(trig_ena[MRMW] & (assert[MRMW] ^ r_rmw_req)) |
(trig_ena[XLTE] & (assert[XLTE] ^ r_tlb_used)) |
(trig_ena[SRTW] & (assert[SRTW] ^ sr_tw)) |
(trig_ena[SUP] & (assert[SUP] ^ r_sup_mode)) |
(trig_ena[MMUBP] & (assert[MMUBP] ^ r_va_bp_hit)) |
(trig_ena[STALL] & (assert[STALL] ^ ~pipe_moved)) |
(trig_ena[FPHLD] & (assert[FPHLD] ^ fhold_d1)) |
(trig_ena[FPQ] & (assert[FPQ] ^ fhold_fqfull_d1)) |
(trig_ena[DMAR] & (assert[DMAR] ^ dvma_req_x)) |
(trig_ena[DMAT] & (assert[DMAT] ^ r_sxlate_ioreq)) |
(trig_ena[DMAW] & (assert[DMAW] ^ sb_write)) |
(trig_ena[26] & trig_b_co) ;
wire triga_and =(~trig_ena[IHLD] | (assert[IHLD] ^ ihold_d1)) &
(~trig_ena[IMSS] | (assert[IMSS] ^ r_icmiss_sustain)) &
(~trig_ena[ISTRM] | (assert[ISTRM] ^ r_ic_stream)) &
(~trig_ena[IFTCH] | (assert[IFTCH] ^ ifetched)) &
(~trig_ena[DHLD] | (assert[DHLD] ^ dhold_d1)) &
(~trig_ena[DMSS] | (assert[DMSS] ^ r_dcmiss_sustain)) &
(~trig_ena[DSTRM] | (assert[DSTRM] ^ r_dc_stream)) &
(~trig_ena[DFTCH] | (assert[DFTCH] ^ did_dfetch)) &
(~trig_ena[WBHLD] | (assert[WBHLD] ^ r_dc_shold)) &
(~trig_ena[MBSY] | (assert[MBSY] ^ r_mbsy)) &
(~trig_ena[ABSY] | (assert[ABSY] ^ r_afx_bsy)) &
(~trig_ena[MPAGE] | (assert[MPAGE] ^ r_page_hit)) &
(~trig_ena[MPRCG] | (assert[MPRCG] ^ precharge_trig)) &
(~trig_ena[MRMW] | (assert[MRMW] ^ r_rmw_req)) &
(~trig_ena[XLTE] | (assert[XLTE] ^ r_tlb_used)) &
(~trig_ena[SRTW] | (assert[SRTW] ^ sr_tw)) &
(~trig_ena[SUP] | (assert[SUP] ^ r_sup_mode)) &
(~trig_ena[MMUBP] | (assert[MMUBP] ^ r_va_bp_hit)) &
(~trig_ena[STALL] | (assert[STALL] ^ ~pipe_moved)) &
(~trig_ena[FPHLD] | (assert[FPHLD] ^ fhold_d1)) &
(~trig_ena[FPQ] | (assert[FPQ] ^ fhold_fqfull_d1)) &
(~trig_ena[DMAR] | (assert[DMAR] ^ dvma_req_x)) &
(~trig_ena[DMAT] | (assert[DMAT] ^ r_sxlate_ioreq)) &
(~trig_ena[DMAW] | (assert[DMAW] ^ sb_write)) &
(~trig_ena[26] | trig_b_co) ;
wire triga_dcd = trig_ena[AND] ? triga_and : triga_or ;
wire r_triga ;
Mflipflop_r_1 triga_ff_1(r_triga,triga_dcd,~ss_reset,ss_clock) ;
assign trig_a_term = trig_ena[LVL] ? triga_dcd : (triga_dcd & ~r_triga) ;
/*** Special select for IVA breakpoints and watchpoint traps ***/
assign iva_wp_sel = ((wp_trap_en | enbl_scan_bp) &
mmu_brkpt_en[0] & (va_src_sel == 2'b00)) ;
assign trig_a = iva_wp_sel ? iacc_wp_e : trig_a_term ;
/*** Trigger B decodes *******************************************************/
wire trigb_or = (trig_enb[IHLD] & (assert[IHLD] ^ ihold_d1)) |
(trig_enb[IMSS] & (assert[IMSS] ^ r_icmiss_sustain)) |
(trig_enb[ISTRM] & (assert[ISTRM] ^ r_ic_stream)) |
(trig_enb[IFTCH] & (assert[IFTCH] ^ ifetched)) |
(trig_enb[DHLD] & (assert[DHLD] ^ dhold_d1)) |
(trig_enb[DMSS] & (assert[DMSS] ^ r_dcmiss_sustain)) |
(trig_enb[DSTRM] & (assert[DSTRM] ^ r_dc_stream)) |
(trig_enb[DFTCH] & (assert[DFTCH] ^ did_dfetch)) |
(trig_enb[WBHLD] & (assert[WBHLD] ^ r_dc_shold)) |
(trig_enb[MBSY] & (assert[MBSY] ^ r_mbsy)) |
(trig_enb[ABSY] & (assert[ABSY] ^ r_afx_bsy)) |
(trig_enb[MPAGE] & (assert[MPAGE] ^ r_page_hit)) |
(trig_enb[MPRCG] & (assert[MPRCG] ^ precharge_trig)) |
(trig_enb[MRMW] & (assert[MRMW] ^ r_rmw_req)) |
(trig_enb[XLTE] & (assert[XLTE] ^ r_tlb_used)) |
(trig_enb[SRTW] & (assert[SRTW] ^ sr_tw)) |
(trig_enb[SUP] & (assert[SUP] ^ r_sup_mode)) |
(trig_enb[MMUBP] & (assert[MMUBP] ^ r_va_bp_hit)) |
(trig_enb[STALL] & (assert[STALL] ^ ~pipe_moved)) |
(trig_enb[FPHLD] & (assert[FPHLD] ^ fhold_d1)) |
(trig_enb[FPQ] & (assert[FPQ] ^ fhold_fqfull_d1)) |
(trig_enb[DMAR] & (assert[DMAR] ^ dvma_req_x)) |
(trig_enb[DMAT] & (assert[DMAT] ^ r_sxlate_ioreq)) |
(trig_enb[DMAW] & (assert[DMAW] ^ sb_write)) |
(trig_enb[26]) ;
wire trigb_and =(~trig_enb[IHLD] | (assert[IHLD] ^ ihold_d1)) &
(~trig_enb[IMSS] | (assert[IMSS] ^ r_icmiss_sustain)) &
(~trig_enb[ISTRM] | (assert[ISTRM] ^ r_ic_stream)) &
(~trig_enb[IFTCH] | (assert[IFTCH] ^ ifetched)) &
(~trig_enb[DHLD] | (assert[DHLD] ^ dhold_d1)) &
(~trig_enb[DMSS] | (assert[DMSS] ^ r_dcmiss_sustain)) &
(~trig_enb[DSTRM] | (assert[DSTRM] ^ r_dc_stream)) &
(~trig_enb[DFTCH] | (assert[DFTCH] ^ did_dfetch)) &
(~trig_enb[WBHLD] | (assert[WBHLD] ^ r_dc_shold)) &
(~trig_enb[MBSY] | (assert[MBSY] ^ r_mbsy)) &
(~trig_enb[ABSY] | (assert[ABSY] ^ r_afx_bsy)) &
(~trig_enb[MPAGE] | (assert[MPAGE] ^ r_page_hit)) &
(~trig_enb[MPRCG] | (assert[MPRCG] ^ precharge_trig)) &
(~trig_enb[MRMW] | (assert[MRMW] ^ r_rmw_req)) &
(~trig_enb[XLTE] | (assert[XLTE] ^ r_tlb_used)) &
(~trig_enb[SRTW] | (assert[SRTW] ^ sr_tw)) &
(~trig_enb[SUP] | (assert[SUP] ^ r_sup_mode)) &
(~trig_enb[MMUBP] | (assert[MMUBP] ^ r_va_bp_hit)) &
(~trig_enb[STALL] | (assert[STALL] ^ ~pipe_moved)) &
(~trig_enb[FPHLD] | (assert[FPHLD] ^ fhold_d1)) &
(~trig_enb[FPQ] | (assert[FPQ] ^ fhold_fqfull_d1)) &
(~trig_enb[DMAR] | (assert[DMAR] ^ dvma_req_x)) &
(~trig_enb[DMAT] | (assert[DMAT] ^ r_sxlate_ioreq)) &
(~trig_enb[DMAW] | (assert[DMAW] ^ sb_write)) ;
wire trigb_dcd = trig_enb[AND] ? trigb_and : trigb_or ;
wire r_trigb ;
Mflipflop_r_1 trigb_ff_1(r_trigb,trigb_dcd,~ss_reset,ss_clock) ;
assign trig_b = trig_enb[LVL] ? trigb_dcd : (trigb_dcd & ~r_trigb) ;
/*****************************************************************************/
/*** Enable performance counter scan breakpoint (only load through scan) ***/
MflipflopR_1 enbl_scan_bp_ff_1(enbl_scan_bp,1'b0,ss_clock,1'b1,ss_reset) ;
wire [15:00] mmu_brkpt_reg; // forward
// the enable is removed since this flop is not accessable with jtag scan.
// the equivalent function will be performed in rl_clk_stop.
// wire mm_bp_dtct_in = enbl_scan_bp & pcntr_a_co ;
wire mm_bp_dtct_in = pcntr_a_co ;
wire mm_bp_dtct;
Mflipflop_r_1 mm_bp_dtct_ff_1(mm_bp_dtct,mm_bp_dtct_in,~ss_reset,ss_clock) ;
/*** SBUS ID match decode for triggers *************************************/
wire enbl_sbid_mtch = mmu_brkpt_reg[12] ;
wire [2:0] sbid_mtch = mmu_brkpt_reg[15:13] ;
assign sbus_id_hit = ~enbl_sbid_mtch | (sbid_mtch == sb_sbslot) ;
/* */
/*****************************************************************************/
/* MMU Breakpoint Enable Reg (PA =0x1000300c) */
/* */
/* +---------------------------------------+-------------------------------+ */
/* | reserved | MMU Breakpont Eanbles | */
/* +---------------------------------------+-------------------------------+ */
/* 31 12 11 00 */
/* */
/* Bit Mnemonic Function */
/* ---- -------- --------- */
/* 00 VA_EN Enable Virtual Address compares (enable = 1) */
/* */
/* 02:01 VA_SRC Virtual Address Source select */
/* */
/* Value | Source */
/* -------+-------------------------------- */
/* 00 | Instruction Cache Address */
/* 01 | Data Cache Address (also write buffer) */
/* 10 | DVMA Address (for I/O MMU functions) */
/* 11 | Physical Address */
/* */
/* 04:03 VA_TYP Virtual Address request type */
/* */
/* Value | Source */
/* -------+-------------------------------- */
/* 00 | Disabled */
/* 01 | Read (D$ miss or I$ miss or DVMA) */
/* 10 | Write (D$ miss or DVMA) */
/* 11 | LDSTO or DVMA translate */
/* */
/* 06:05 TW_SRC Tablewalk source */
/* */
/* Value | Source */
/* -------+-------------------------------- */
/* 00 | Disabled */
/* 01 | Instruction Address tablewalk */
/* 10 | Data Address tablewalk (write buffer) */
/* 11 | DVMA Address tablewalk */
/* */
/* 07 REQ_EN Memory Request compare enable */
/* */
/* 11:08 MREQ Memory request match field */
/* */
/* Value | Request Type */
/* -------+-------------------------------- */
/* 0000 | --- */
/* 0001 | Read 8-bytes */
/* 0010 | Read 16-bytes */
/* 0011 | --- */
/* 0100 | Read 32-bytes */
/* 0101 | --- */
/* 011x | --- */
/* 1000 | --- */
/* 1001 | Write 1-byte */
/* 1010 | Write 2-bytes */
/* 1011 | Write 4-bytes */
/* 1100 | Write 8-bytes */
/* 1101 | Write 16-bytes */
/* 111x | --- */
/* */
/* 12 SB_EN Sbus ID match enable */
/* */
/* 15:13 SB_ID Sbus ID match field */
/*****************************************************************************/
wire mmu_brkpt_hld = ~(pa_reg_dcd & (mm_pa[15:00] == 16'h300c) & mmstben_reg) ;
MflipflopR_16 mmu_brkpt_ff_16(mmu_brkpt_reg,misc_in[15:0],ss_clock, mmu_brkpt_hld,ss_reset) ;
/*** Virtual Address source select ******/
/*** 00 - Virtual Instruction Address ***/
/*** 01 - Virtual Data Cache Address ***/
/*** 10 - I/O Address ***/
/*** 11 - Physical Address ***/
assign va_src_sel = mmu_brkpt_reg[02:01] ;
/*****************************************************************************/
assign mmu_brkpt_en = mmu_brkpt_reg[11:00] ;
wire [26:00] mmu_brkpt_pad = {10'b0, mmu_brkpt_reg} ;
wire [26:00] trig_asrt_pad = {1'b0, trig_asrt, 2'b0} ;
// Expanded macro begin.
// cmux4(perf_mux, 27, perf_mux_out, trig_ena, /* pa = 0x1000 3000 */ trig_enb, /* pa = 0x1000 3004 */ trig_asrt_pad, /* pa = 0x1000 3008 */ mmu_brkpt_pad, /* pa = 0x1000 300c */ mm_pa[03:02])
function [ 27:1] perf_mux ;
input [ 27:1] in0_fn ;
input [ 27:1] in1_fn ;
input [ 27:1] in2_fn ;
input [ 27:1] in3_fn ;
input [1:0] select_fn ;
reg [ 27:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
2'b00: out_fn = in0_fn ;
2'b01: out_fn = in1_fn ;
2'b10: out_fn = in2_fn ;
2'b11: out_fn = in3_fn ;
default: out_fn = 65'hx;
endcase
perf_mux = out_fn ;
end
endfunction
assign perf_mux_out = perf_mux( trig_ena, /* pa = 0x1000 3000 */ trig_enb, /* pa = 0x1000 3004 */ trig_asrt_pad, /* pa = 0x1000 3008 */ mmu_brkpt_pad, /* pa = 0x1000 300c */ mm_pa[03:02]) ;
// Expanded macro end.
endmodule
/*****************************************************************************/
/**** TEMPORARY modules for RS-flops ****************************************/
/*****************************************************************************/
![[Up: rl_mmu_regs sfsr_reg]](v2html-up.gif)
module rsflop_sfsr(out,in,clock,hold,reset,global_reset) ;
/*
** this module allows you to instantiate S1rsff using a syntax
** similar to the REGR macro
*/
output [14:00] out ;
input [14:00] in;
input clock, hold, reset, global_reset ;
rsflop sfsr_ff14 (out[14],in[14],clock,hold,reset,global_reset);
rsflop sfsr_ff13 (out[13],in[13],clock,hold,reset,global_reset);
rsflop sfsr_ff12 (out[12],in[12],clock,hold,reset,global_reset);
rsflop sfsr_ff11 (out[11],in[11],clock,hold,reset,global_reset);
rsflop sfsr_ff10 (out[10],in[10],clock,hold,reset,global_reset);
rsflop sfsr_ff09 (out[09],in[09],clock,hold,reset,global_reset);
rsflop sfsr_ff08 (out[08],in[08],clock,hold,reset,global_reset);
rsflop sfsr_ff07 (out[07],in[07],clock,hold,reset,global_reset);
rsflop sfsr_ff06 (out[06],in[06],clock,hold,reset,global_reset);
rsflop sfsr_ff05 (out[05],in[05],clock,hold,reset,global_reset);
rsflop sfsr_ff04 (out[04],in[04],clock,hold,reset,global_reset);
rsflop sfsr_ff03 (out[03],in[03],clock,hold,reset,global_reset);
rsflop sfsr_ff02 (out[02],in[02],clock,hold,reset,global_reset);
rsflop sfsr_ff01 (out[01],in[01],clock,hold,reset,global_reset);
rsflop sfsr_ff00 (out[00],in[00],clock,hold,reset,global_reset);
endmodule // rsflop_sfsr
module rsflop_afsr(out,in,clock,hold,reset,global_reset) ;
/*
** this module allows you to instantiate S1rsff using a syntax
** similar to the REGR macro
*/
output [09:00] out ;
input [09:00] in;
input clock, hold, reset, global_reset ;
rsflop afsr_ff09 (out[09],in[09],clock,hold,reset,global_reset);
rsflop afsr_ff08 (out[08],in[08],clock,hold,reset,global_reset);
rsflop afsr_ff07 (out[07],in[07],clock,hold,reset,global_reset);
rsflop afsr_ff06 (out[06],in[06],clock,hold,reset,global_reset);
rsflop afsr_ff05 (out[05],in[05],clock,hold,reset,global_reset);
rsflop afsr_ff04 (out[04],in[04],clock,hold,reset,global_reset);
rsflop afsr_ff03 (out[03],in[03],clock,hold,reset,global_reset);
rsflop afsr_ff02 (out[02],in[02],clock,hold,reset,global_reset);
rsflop afsr_ff01 (out[01],in[01],clock,hold,reset,global_reset);
rsflop afsr_ff00 (out[00],in[00],clock,hold,reset,global_reset);
endmodule // rsflop_sfsr
module rsflop_mfsr(out,in,clock,hold,reset,global_reset) ;
/*
** this module allows you to instantiate S1rsff using a syntax
** similar to the REGR macro
*/
output [07:00] out ;
input [07:00] in;
input clock, hold, reset, global_reset ;
rsflop mfsr_ff07 (out[07],in[07],clock,hold,reset,global_reset);
rsflop mfsr_ff06 (out[06],in[06],clock,hold,reset,global_reset);
rsflop mfsr_ff05 (out[05],in[05],clock,hold,reset,global_reset);
rsflop mfsr_ff04 (out[04],in[04],clock,hold,reset,global_reset);
rsflop mfsr_ff03 (out[03],in[03],clock,hold,reset,global_reset);
rsflop mfsr_ff02 (out[02],in[02],clock,hold,reset,global_reset);
rsflop mfsr_ff01 (out[01],in[01],clock,hold,reset,global_reset);
rsflop mfsr_ff00 (out[00],in[00],clock,hold,reset,global_reset);
endmodule // rsflop_mfsr
module rsflop_merr(out,in,clock,hold,reset,global_reset) ;
/*
** this module allows you to instantiate S1rsff using a syntax
** similar to the REGR macro
*/
output [03:00] out ;
input [03:00] in;
input clock, hold, reset, global_reset ;
rsflop merr_ff03 (out[03],in[03],clock,hold,reset,global_reset);
rsflop merr_ff02 (out[02],in[02],clock,hold,reset,global_reset);
rsflop merr_ff01 (out[01],in[01],clock,hold,reset,global_reset);
rsflop merr_ff00 (out[00],in[00],clock,hold,reset,global_reset);
endmodule // rsflop_merr
| This page: |
Created: | Thu Aug 19 12:02:53 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/rl_mmu_regs.v
|