Mflipflop_r_1 acc_err_tw_ff_1(acc_err_tw_hld,acc_err_tw,~ss_reset,ss_clock) ;

    assign r_tlb_used = (r_io_tlb | (r_dc_tlb & r_dc_miss & ~r_trap_w) |
			 (r_ic_tlb & r_ic_miss)) & ~tw_par & ~enbl_soft_tw;

/*** Need to disqualify probe signals during other tablewalks bug#670 ****/
    assign ok_2_probe = ~(ic_tlb_tw | io_tlb_tw | wr_tlb_tw);

    assign hld_mreq_reg = ~(ld_par | ld_mreq_tw | ldst_st );

/*****************************************************************************/
/***** D-Cache interface signals  ********************************************/


// Added ~mmu_bypass to qualify cache-able status of each enable
    assign dcen_int = (pcr_dcen & (pcr_mmuen | pcr_ac) &
            (mmu_bypass | (~tlb_miss & tlb_c_bit)));

    assign dabort_in = (r_trap_w & dc_miss_sustain & ~tw_tlb_nxt) |
    			(r_dc_tlb & r_dc_miss & (priv_err_x | prtct_err_x) &
				((read_w & ~wb_valid_x) | st_miss_x)) |
			(r_wr_tlb & (priv_err_x | prtct_err_x)) |
			(dc_tlb_tw & ~probe & (tw_err | r_acc_err_tw)) |
			dacc_miss | cntrl_spc_err  ;

/*** Decode the Data Error Write Buffer strobe   *****************************/
wire derr_wbstb_in = dabort_in & last_st_w ;

wire derr_wbstb ;
Mflipflop_r_1 derr_wbstb_ff_1(derr_wbstb,derr_wbstb_in,~ss_reset,ss_clock) ;

/*****************************************************************************/
/***** I-Cache interface signals   *******************************************/

// **** mmu_bypass is already gated  - problem?? ****

    assign icen_int = (pcr_icen & (pcr_mmuen | pcr_ac) &
            (mmu_bypass | (~tlb_miss & tlb_c_bit)));

/*** cbit_in is used for cacheable bit for AFSR - needs to reflect  **********/
/***          current translation.                                         ***/

// Changed cache allocate default scheme for 2nd tapeout
// Old scheme was
//     ~(dc_tlb_state & st_miss_w & sup_nalloc)
//

    assign cbit_in = (ic_tlb_state & icen_int) | 
		((dc_tlb_state | wr_tlb) & dcen_int & ~mmu_asi_op &
		 ~(dc_tlb_state & st_miss_w & ~(sup_nalloc & ~r_sup_mode))) |
		(ic_par_state & ipar_cbit) |
		(dc_par_state & dpar_cbit );

/* generate asi bypass for data path */

    assign bypass_mmu_asi = bypass_mmu_asi_w & dc_tlb_state ;

/****************************************************************************/

// define mreq operations

parameter   [2:0]    NOP        = 3'b000,
                     RD64       = 3'b001,
                     RD128      = 3'b010,
                     RD256      = 3'b100,
                     WR8        = 3'b001,
                     WR16       = 3'b010,
                     WR32       = 3'b011,
                     WR64       = 3'b100,
                     WR128      = 3'b101;

parameter	     READ	= 1'b0,
		     WRITE	= 1'b1;

/* function drives mreq_rdy */


function mem_write;

    input r_io_tlb;
    input ic_in_par;
    input dc_in_par;
    input read_w;
    input write_w;
    input ldsto_w;
    input [1:0] size_w;
    input wb_valid_t;
    input tw_read_req;
    input tw_write_req;
    input [3:0] r_sb_ioreq;
    input ldst_st;
    input ss_reset;

    if (ss_reset) begin
        mem_write = NOP;
        end
    else begin
    case (1'b1) // synopsys parallel_case
    ((dc_in_par & wb_valid_t) | ldst_st): 
        mem_write = WRITE;

    (dc_in_par & ~wb_valid_t & (read_w | write_w)): begin
        mem_write = READ;
        end
    (ic_in_par): begin
        mem_write = READ;
        end
    (tw_read_req): begin
        mem_write = READ;
        end
    (tw_write_req): begin
        mem_write = WRITE;
        end
    default: begin
    if (r_io_tlb) begin
        case (r_sb_ioreq) /* synopsys parallel_case */
            SRD64: begin
                mem_write = READ;
                end
            SRD128: begin
                mem_write = READ;
                end
            SRD256: begin
                mem_write = READ;
                end
            SWR8: begin
                mem_write = WRITE;
                end
            SWR16: begin
                mem_write = WRITE;
                end
            SWR32: begin
                mem_write = WRITE;
                end
            SWR64: begin
                mem_write = WRITE;
                end
            SWR128: begin
                mem_write = WRITE;
                end
            SXLATE: begin
                mem_write = READ;
                end
            default: begin
                mem_write = READ;
            end
        endcase
        end
        else mem_write = READ;
        end
     endcase
     end
endfunction

    assign { mreq_rdy[3] }
        = mem_write (r_io_tlb, ic_in_par, dc_in_par, 
        read_w, write_w, ldsto_w, size_w, wb_valid_t, 
	 tw_read_req, tw_write_req, r_sb_ioreq, ldst_st, 
         ss_reset);


function [2:0] wrt_size;

    input r_io_tlb;
    input ic_in_par;
    input dc_in_par;
    input read_w;
    input write_w;
    input ldsto_w;
    input [1:0] size_w;
    input [1:0] wb_3_size;
    input wb_valid_t;
    input par_cbit;
    input tw_read_req;
    input tw_write_req;
    input [3:0] r_sb_ioreq;
    input ldst_st;
    input ss_reset;

    if (ss_reset) begin
        wrt_size = NOP;
        end
    else begin
    case (1'b1) // synopsys parallel_case
    ((dc_in_par & wb_valid_t) | ldst_st): begin
        case (wb_3_size) // synopsys full_case parallel_case
            2'b00:  begin
                wrt_size = WR8;
                end
            2'b01:  begin
                wrt_size = WR16;
                end
            2'b10:  begin
                wrt_size = WR32;
                end
            2'b11:  begin
                wrt_size = WR64;
                end
            endcase
        end
    (dc_in_par & ~wb_valid_t & (read_w | write_w) & ~ldst_st): begin
        wrt_size = RD128;
        end
    (ic_in_par): begin
        wrt_size = RD256;
        end
    (tw_read_req): begin
        wrt_size = RD64;
        end
    (tw_write_req): begin
        wrt_size = WR32;
        end
    default: begin
    if (r_io_tlb) begin
        case (r_sb_ioreq) /* synopsys parallel_case */
            SRD64: begin
                wrt_size = RD64;
                end
            SRD128: begin
                wrt_size = RD128;
                end
            SWR8: begin
                wrt_size = WR8;
                end
            SWR16: begin
                wrt_size = WR16;
                end
            SWR32: begin
                wrt_size = WR32;
                end
            SWR64: begin
                wrt_size = WR64;
                end
            SWR128: begin
                wrt_size = WR128;
                end
            SXLATE: begin
                wrt_size = NOP;
                end
            default: begin
                wrt_size = NOP;
            end
        endcase
        end
        else wrt_size = NOP;
        end  // default
     endcase
     end
endfunction

    assign { wrt_rdy[2:0] }
        = wrt_size (r_io_tlb, ic_in_par, dc_in_par, 
        read_w, write_w, ldsto_w, size_w, wb_3_size, wb_valid_t,
        par_cbit,
	 tw_read_req, tw_write_req, r_sb_ioreq, ldst_st, 
         ss_reset);

function [2:0] read_size;

    input r_io_tlb;
    input r_ic_in_par;
    input r_dc_in_par;
    input read_w;
    input write_w;
    input ldsto_w;
    input [1:0] size_w;
    input [1:0] wb_3_size;
    input wb_valid_x;
    input par_cbit;
    input tw_read_req;
    input tw_write_req;
    input [3:0] r_sb_ioreq;
    input ldst_st;
    input ss_reset;

    if (ss_reset) begin
        read_size = NOP;
        end
    else begin
    case (1'b1) // synopsys parallel_case
    ((r_dc_in_par & wb_valid_x) | ldst_st): begin
        case (wb_3_size) // synopsys full_case parallel_case
            2'b00:  begin
                read_size = WR8;
                end
            2'b01:  begin
                read_size = WR16;
                end
            2'b10:  begin
                read_size = WR32;
                end
            2'b11:  begin
                read_size = WR64;
                end
            endcase
        end
    (r_dc_in_par & ~wb_valid_x & (read_w | write_w) & par_cbit): begin
        read_size = RD128;
        end
    (r_dc_in_par & ~wb_valid_x & read_w & ~par_cbit): begin
        read_size = RD64;
        end
    (r_ic_in_par & par_cbit): begin
        read_size = RD256;
        end
    (r_ic_in_par & ~par_cbit): begin
        read_size = RD64;
        end
    (tw_read_req): begin
        read_size = RD64;
        end
    (tw_write_req): begin
        read_size = WR32;
        end
    default: begin
    if (r_io_tlb) begin
        case (r_sb_ioreq) /* synopsys parallel_case */
            SRD64: begin
                read_size = RD64;
                end
            SRD128: begin
                read_size = RD128;
                end
            SRD256: begin
                read_size = RD256;
                end
            SWR8: begin
                read_size = WR8;
                end
            SWR16: begin
                read_size = WR16;
                end
            SWR32: begin
                read_size = WR32;
                end
            SWR64: begin
                read_size = WR64;
                end
            SWR128: begin
                read_size = WR128;
                end
            SXLATE: begin
                read_size = NOP;
                end
            default: begin
                read_size = NOP;
            end
        endcase
        end
        else read_size = NOP;
        end   // default
     endcase
     end
endfunction

    assign { read_rdy[2:0] }
        = read_size (r_io_tlb, r_ic_in_par, r_dc_in_par, 
        read_w, write_w, ldsto_w, size_w, wb_3_size, wb_valid_x,
        par_cbit,
	 tw_read_req, tw_write_req, r_sb_ioreq, ldst_st, 
         ss_reset);

assign {mreq_rdy[2:0]} = mem_issue_req ? read_rdy : wrt_rdy ;

// ARAY
//assign mm_fb_size = r_io_tlb ? dma_size :
//      (((r_dc_in_par & wb_valid_x) | ldst_st) ? wb_3_size :
//              (par_cbit ? {2'b11} : size_w)) ;
 
assign mm_fb_size = (r_ic_in_par & mm_fb_req) ? 2'b11 :
                        r_io_tlb ? dma_size :
        (((r_dc_in_par & wb_valid_x) | ldst_st) ? wb_3_size :
                (par_cbit ? {2'b11} : size_w)) ;


/*****************************************************************************/
/***** MMU Breakpoint debug logic ********************************************/

    wire enbl_va_mtch = mmu_brkpt_en[00] ;

    wire enbl_mmreq_mtch = mmu_brkpt_en[07] ;

    wire [3:0] mreq_mtch = mmu_brkpt_en[11:08] ;

/*** Virtual address memory op type match                           ******/
/***  00 - disabled                             ***/
/***  01 - read (w_stage) or fetch (f_stage)    ***/
/***  10 - write (w_stage)                      ***/
/***  11 - ldsto (w_stage)                      ***/

    wire [1:0] va_type_bp = mmu_brkpt_en[04:03] ;

/*** Tablewalk source matching                                      ******/
/***  00 - disabled                                ***/
/***  01 - Instruction tablewalk during ic_tlb_tw  ***/
/***  10 - Data tablewalk during dc_tlb_tw         ***/
/***  11 - I/O tablewalk during io_tlb_tw          ***/

    wire [1:0] tw_src_bp = mmu_brkpt_en[06:05] ;

    wire va_type_hit = (~va_type_bp[1] & ~va_type_bp[0]) |
                (~va_type_bp[1] &  va_type_bp[0] & (read_w | r_srd_ioreq)) |
                (va_type_bp[1] & ~va_type_bp[0] & (write_w | r_swr_ioreq)) |
                (va_type_bp[1] &  va_type_bp[0] & (ldsto_w | r_sxlate_ioreq));

    wire tw_src_hit = (~tw_src_bp[1] & ~tw_src_bp[0]) | 
                      (~tw_src_bp[1] &  tw_src_bp[0] & ic_tlb_tw) |
                       (tw_src_bp[1] & ~tw_src_bp[0] & dc_tlb_tw) |
                       (tw_src_bp[1] &  tw_src_bp[0] & io_tlb_tw) ;

    wire mmreq_hit = (~enbl_mmreq_mtch |
			 (r_mem_issue_req & (mm_mreq == mreq_mtch))) ;

    wire va_hit = enbl_va_mtch & dp_bp_hit & va_type_hit;

    assign mmulgc_bp_hit = va_hit & mmreq_hit & tw_src_hit & sbus_id_hit ;

JBUFDA  slow_buf1(wb_3_asi[1],wb_3_asi_buf[1]);
JBUFDA  slow_buf0(wb_3_asi[0],wb_3_asi_buf[0]);
JBUFC  slow_buf2(mm_sbsize_unbuf[1],buf_term1);
JBUFC  slow_buf3(mm_sbsize_unbuf[0],buf_term0);
JBUFD  slow_buf4(buf_term1,mm_sbsize[1]);
JBUFD  slow_buf5(buf_term0,mm_sbsize[0]);


endmodule


... (truncated)
module rsflop(out,in,clock,hold,reset,global_reset) ;

/*
** this module allows you to instantiate S1rsff using a syntax
** similar to the REGR macro
*/

output out ;
input in, clock, hold, reset, global_reset ;

wire logic_0 = 1'b0 ;
wire logic_1 = 1'b1 ;

ASFFRHA dff (.H(hold & ~(reset|global_reset)),.D(in | reset),.Q(out),.CK(clock),
                .SM(1'b0),.SI(1'b0),.R(~(reset|global_reset)));

endmodule