/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)rl_mmu_regs.v
***
****************************************************************************
****************************************************************************/
// @(#)rl_mmu_regs.v 1.192 9/9/93
/******************************************************************************/
// rl_mmu_regs.v
//
// Description:
// This module describes the mmu special registers,
// and the datapath the allow them to be written and
// read. The registers contained in this module are:
// PCR - processor control register
// SFSR - Synchronous Fault Status Register
// IO_CR - IO control register
// AFSR - Asynchronous Fault Status Register
// SSCR - Sbus Status/Control Registers (3)
//
// Dependencies:
// This module is instantiated by the m_mmu_cntl.v module.
//
/******************************************************************************/
![[Up: m_mmu_cntl mmu_regs]](v2html-up.gif)
module rl_mmu_regs
(
enbl_br_fold, /* enable for br folding */
mmu_cr, /* MMU Control register output*/
io_range, /* IO Control register output*/
mmu_bypass, /* decode of bypass conditions*/
r_p_reply_dec, /* */
hld_ibar,
tlb_addr,
mm_fbpage_en,
hld_afar, /* AFAR hold enable */
hld_mfar, /* MFAR hold enable */
afar_write,
mfar_write,
sfar_write,
sfar_read,
dp_mux1_sel,
virt_ptp2,
pamux_rd_sel,
tlb_miss, /* tlb_miss_raw gated with mmu_bypass*/
tlb_hit, /* acc_ok gated with mmu_bypass*/
tlb_m_miss, /* m_miss gated with mmu_bypass*/
tlb_err, /* tb_error gated with mmu_bypass*/
mm_dacc_err, /* Data access error (parity error)*/
mm_dacc_exc, /* Data access exception*/
mm_dacc_miss, /* Data access MMU miss*/
mm_sb_err, /* Error occured during IO DMA */
mm_lvl15_int_l, /* Level 15 interrupt */
mm_rfr_cntl,
mm_oddpar,
mm_parity_en,
mm_sbae, /* SBus Arb Enables from MID. */
mm_rom_module_speed,
hold_sfar,
boot_out_30, /* PA[30] non-datapath mux output */
io_mmu_bp,
probe_err,
r_tw_err,
tw_err,
priv_err_x,
prtct_err_x,
io_tlb_err,
flush_iopte,
flush_ioall,
mm_bp_dtct,
boot_mode,
mmu_en_e,
r_acc_err_tw,
mm_sscr_ba8,
par_cbit,
ipar_cbit,
dpar_cbit,
mop_c_bit,
mop_mreq,
tw_perr,
iacc_miss,
dacc_miss,
enbl_soft_tw,
io_mmu_en,
sup_nalloc,
misc,
mm_page_hit_en,
mm_fs_perr,
mm_fs_lvl,
mm_fs_iae,
mm_fs_xerr,
mm_fs_mmiss,
mm_fs_sbe,
mm_fs_sto,
mm_fs_sptct,
ld_pcntr_a,
ld_pcntr_b,
trig_a,
trig_b,
iva_wp_sel,
sel_brkpt_mux,
vaf_en_hld,
va_bp_hld,
va_src_sel,
mm_dacc_wp,
wb_err,
mm_cache_stat,
mmu_brkpt_en,
afx_qlvl,
r_mem_issue_req,
sbus_id_hit,
r_tlb_compare,
r_sup_mode,
mm_go_standby,
/** Inputs **/
turn_off_standby,
bm_sel, // if set, boot from SBus, else AFX
cntrl_spc_err,
marb_busy,
mm_dabort,
r_dc_par,
r_ic_par,
normal_asi_w,
r_tlb_used,
misc_in,
dvma_req_x,
r_mbsy,
mmdaten,
mmu_daten,
pipe_moved,
read_w,
ldd_w,
hld_mmu_cr, /* MMU_CR hold enable*/
hld_sfsr, /* SFSR hold enable*/
rd_sfsr, /* SFSR read decode*/
hld_trcr, /* TLB RCR hold enable*/
tw_trcr_hld, /* TLB RCR hold enable from tw state machine*/
dp_perr, /* indicates parity error on current mop*/
sb_err_type, /* Sbus error type*/
sb_wrt_err, /* Sbus CPU write error*/
sb_errsize, /* Sbus error size indication*/
hold_par, /* Load PAR signal */
cbit_in, /* Cacheable bit from PTE*/
tlb_acc_raw, /* tlb access field */
mmstben_reg, /* data on mdata valid to read*/
mmstben_aarb, /* data on misc valid to store */
mmreg_rd_asi, /* data on misc valid for load */
mmreg_rd_cs, /* data on misc valid for load */
bypass_mmu_asi, /* ASI decode indicates to bypass mmu*/
asi_dcd3, /* ASI decode = 03 (from asi_cntl)*/
asi_dcd4, /* ASI decode = 04 (from asi_cntl)*/
asi_dcd6, /* ASI decode = 06 (from asi_cntl)*/
r_dva_12_8, /* reg'd iu_dva bits 12:08 */
r_dva_7_2, /* reg'd iu_dva bits 07:02 */
mm_pa, /* Physical address output for ASI reads*/
cxr, /* CXR for ASI read operations*/
tlb_lvl, /* reflects level of current TLB operation*/
pa_mux_rd, /* 32-bit read bus from pa_mux datapath*/
data_acc_s,
tw_par, /* tlb walk in progress*/
tlb_miss_raw, /* raw tlb_miss signal from TLB*/
m_miss, /* raw m_miss signal from TLB*/
acc_ok, /* raw acc_ok signal from TLB*/
c_en, /* tlb input address select*/
tw_write, /* table walk write in progress*/
data_op, /* current translation for data op */
io_op, /* current translation for IO op */
tw_addr_err, /* Internal Address error */
tw_xlat_err, /* Translation access error */
hld_sfar,
sb_sbslot, /* sbus slot select 3-bit field */
iu_pipe_hold,
tw_err_lvl,
tlb_flush,
wb_valid_x,
st_miss_x,
mem_issue_req,
tw_init_par,
tw_prb_err,
probe_invalid,
probe,
probe_done,
sb_ioa,
io_range_sel,
sb_write,
r_srd_ioreq,
r_sxlate_ioreq,
sb_va_val_l,
ic_tlb,
ic_tlb_state,
r_ic_tlb,
r_tlb_miss,
r_dc_tlb,
r_wr_tlb,
dc_tlb,
dc_tlb_state,
wr_tlb,
r_ic_tlb_pnd,
r_mstb_l,
mm_dccfstb,
mmulgc_bp_hit,
iwait_state,
mm_mreq,
io_issue_req,
io_tlb_tw,
root_tw,
pt1_tw,
pt2_tw,
tw_pte_chk,
dc_tlb_tw,
wr_tlb_tw,
ic_tlb_tw,
asi_dcd9_w,
io_tw_wrt,
sr_tw_wrt,
sb_cyc_pnd,
dmiss_for_m,
ipar_valid,
dpar_valid,
ic_par_state,
dc_par_state,
mm_dstat_avail,
mm_istat_avail,
dc_in_par,
r_dc_in_par,
r_ic_in_par,
r_sb_par,
mmu_asi_op,
cam_reg_hld,
r_ic_miss,
r_dc_miss,
dc_miss_sustain,
ic_miss_sustain,
iu_sfs_sup,
iu_sfs_perr,
iu_sfs_xerr,
iu_sfs_mmiss,
iu_sfs_iae,
iu_sfs_sbe,
iu_sfs_sto,
iu_sfs_prtct,
iu_sfs_priv,
iu_sfs_lvl,
iu_mm_iacc_wp_exc_d,
r_sb_ic_op, /* Last PIO op was for an I-cache miss */
tb_error,
r_io_space,
r_cntl_space,
r_pci_space,
mm_iabort,
mm_cpsb_wrt,
pio_data_rcvd,
r_drd_c1, /* Marb state DRD_C1 reg'd */
dc_stream, /* Performance trigger */
ic_stream, /* Performance trigger */
ihold_d1, // MMU perf counter trigger
dhold_d1, // MMU perf counter trigger
dc_shold, // MMU perf counter trigger wb full
did_ifetch, // MMU perf counter trigger
did_dfetch, // MMU perf counter trigger
fhold_d1, // MMU perf counter trigger
fhold_fqfull_d1, // MMU perf counter trigger
iu_sup_mode, // MMU perf counter trigger
mm_page, // MMU perf counter trigger
sr_tw, // MMU perf counter trigger
pcntr_a_co, // MMU perf counter trigger
pcntr_b_co, // MMU perf counter trigger
p_reply_dec, // AFX queue status
precharge_early_0,
precharge_early_1,
odd_wd,
sel_cache_stat,
w_sp_sel, // Speed select (for mmu status)
w_div_ctl, // Divide by cntl (mmu status)
mc_afx_to, // AFX timeout indicator
afx_qbusy,
r_fb_space,
ldtlb_data_tw,
iu_in_trap,
hold_fetch_f_l, // ~refetch_g (see BUG #589)
ss_clock,
ss_reset,
ss_reset_any,
ss_scan_mode
);
output enbl_br_fold; /* enable for br folding */
output mm_fbpage_en; /* enable for afx page hits */
output [31:00] mmu_cr; /* MMU Control register output*/
output [2:0] io_range; /* IO Control register output bit [4:2]*/
output [1:0] mm_page_hit_en; /* Page hit register enables */
output mmu_bypass; /* decode of bypass conditions*/
output hld_ibar; /* HOLD enable for IBAR*/
output [5:0] tlb_addr; /* TLB address (5-bits)*/
output hld_afar; /* Hold enable for AFAR */
output hld_mfar; /* Hold enable for MFAR */
output afar_write; /* Input mux select for AFAR*/
output mfar_write; /* Input mux select for MFAR*/
output sfar_write; /* Input mux select for AFAR*/
output sfar_read; /* Input mux select for AFAR*/
output [4:0] dp_mux1_sel; /* mux selects for TLB/ITBR read mux*/
output [4:0] pamux_rd_sel; /* mux selects for physical read mux*/
output tlb_miss; /* tlb_miss_raw gated with mmu_bypass*/
output tlb_hit; /* acc_ok gated with mmu_bypass*/
output tlb_m_miss; /* m_miss gated with mmu_bypass*/
output tlb_err; /* tb_error gated with mmu_bypass*/
output mm_dacc_err; /* Data access error (parity error)*/
output mm_dacc_exc; /* Data access exception*/
output mm_dacc_miss; /* Data access MMU miss*/
output [3:0] mm_rfr_cntl;
output mm_oddpar;
output virt_ptp2;
output mm_parity_en;
output mm_sb_err; /* Error occurred during IO DMA */
output mm_lvl15_int_l; /* Level 15 interrupt */
output [5:0] mm_sbae; /* Sbus Arb. enable bits from MID */
output [3:0] mm_rom_module_speed;
output hold_sfar;
output boot_out_30; /* PA[30] non datapath mux output */
output io_mmu_bp; /* IO Bypass mode */
output probe_err;
output r_tw_err;
output tw_err;
output priv_err_x;
output prtct_err_x;
output io_tlb_err;
output flush_iopte;
output flush_ioall;
output mm_bp_dtct; /* MMU breakpoint detect */
output boot_mode;
output mmu_en_e;
output r_acc_err_tw;
output [4:0] mm_sscr_ba8;
output par_cbit;
output ipar_cbit;
output dpar_cbit;
output mop_c_bit;
output [3:0] mop_mreq;
output tw_perr;
output iacc_miss;
output dacc_miss;
output enbl_soft_tw;
output io_mmu_en;
output sup_nalloc;
output [1:0] mm_fs_perr; // Instruction Fault status parity err
output [1:0] mm_fs_lvl; // Instruction Fault status PTE level
output mm_fs_iae; // Instr Fault Invalid Address Error
output mm_fs_xerr; // Instr Fault translation error
output mm_fs_mmiss; // Instr Fault TLB miss (software tw)
output mm_fs_sbe; // Instr Fault Sbus Error
output mm_fs_sto; // Instr Fault Sbus timeout
output mm_fs_sptct; // Instr Fault protection exception
output [2:0] r_p_reply_dec; // AFX queue status (# of entries)
output ld_pcntr_a; // Load performance counter A
output ld_pcntr_b; // Load performance counter B
output trig_a; // Trigger for perf counter A
output trig_b; // Trigger for perf counter B
output iva_wp_sel;
output sel_brkpt_mux;
output vaf_en_hld;
output va_bp_hld;
output [1:0] va_src_sel;
output mm_dacc_wp; // Watchpoint trap output
output wb_err; // Write buffer error
output mm_cache_stat; // Cacheability status for both caches
output [11:00] mmu_brkpt_en; // MMU Breakpoint enable reg
output afx_qlvl; // AFX Queue level register output
output r_mem_issue_req;
output sbus_id_hit;
output r_tlb_compare; // cycle after TLB lookup (compare)
output r_sup_mode;
output mm_go_standby; // programmable bit in parallel to external standby pin
output [31:00] misc;
// changed to 2 bits. if non-zero boot from pci
input turn_off_standby; // turn off programmable bit because of pci activity.
input [1:0] bm_sel; // if bit 1, boot from pci bus, else AFX
input cntrl_spc_err;
input marb_busy;
input dvma_req_x;
input mm_dabort;
input normal_asi_w;
input [31:00] misc_in;
input mmdaten;
input mmu_daten;
input read_w;
input r_dc_par;
input r_ic_par;
input ldd_w;
input hld_mmu_cr; /* MMU_CR hold enable*/
input hld_sfsr; /* SFSR hold enable*/
input rd_sfsr; /* SFSR read decode*/
input hld_trcr; /* TLB RCR hold enable*/
input tw_trcr_hld; /* TLB RCR hold enable from tw state machine*/
input [1:0] dp_perr; /* indicates parity error on current mop*/
input [1:0] sb_err_type; /* Sbus error type*/
input sb_wrt_err; /* SbusPU wrt error*/
input [2:0] sb_errsize; /* Sbus error size indication*/
input hold_par;
input cbit_in; /* Cacheable bit from PTE*/
input [2:0] tlb_acc_raw; /* tlb access field */
input mmstben_reg; /* data on misc valid to read*/
input mmstben_aarb; /* data on misc valid for store */
input mmreg_rd_asi; /* data on misc valid for load */
input mmreg_rd_cs; /* data on misc valid for load */
input bypass_mmu_asi; /* ASI decode indicates to bypass mmu*/
input asi_dcd3; /* ASI decode that indicates a probe/flush */
input asi_dcd4; /* ASI decode that indicates a DVA register access*/
input asi_dcd6; /* ASI decode that indicates a TLB or ITBR access*/
input [12:08] r_dva_12_8; /* reg'd iu_dva bits 12:08 */
input [7:2] r_dva_7_2; /* reg'd iu_dva bits 07:02 */
input [30:0] mm_pa; /* Physical address output for ASI reads*/
input [7:0] cxr; /* CXR for ASI read operations*/
input [2:0] tlb_lvl; /* current TLB level (note: what about ITBR error?)*/
input [31:00] pa_mux_rd; /* read data from pa_mux datapath*/
input [2:0] data_acc_s; /* encoded access type field for SFSR*/
input tw_par; /* tlb walk in progress*/
input tlb_miss_raw; /* raw tlb_miss signal from TLB*/
input m_miss; /* raw m_miss signal from TLB*/
input acc_ok; /* raw acc_ok signal from TLB*/
input c_en; /* tlb input address select*/
input tw_write; /* table walk write in progress*/
input data_op; /* current translation for data op */
input io_op; /* current translation for IO op */
input tw_addr_err; /* Internal Address error */
input tw_xlat_err; /* Translation access error */
input hld_sfar; /* hld SFAR ASI decode */
input [2:0] sb_sbslot; /* sbus slot select */
input iu_pipe_hold;
input wb_valid_x;
input st_miss_x;
input [1:0] tw_err_lvl;
input tlb_flush; /* signal for TLB PTE flush next cycle */
input mem_issue_req; /* indicates a memory request made */
input tw_init_par; /* table walk in INIT_PAR state */
input tw_prb_err; /* Probe error during tablewalk */
input probe_invalid; /* Invalid Probe entry */
input probe;
input probe_done; /* Probe DOne */
input [31:24] sb_ioa;
input [7:1] io_range_sel;
input sb_write;
input r_mbsy;
input r_tlb_used;
input r_srd_ioreq;
input r_sxlate_ioreq;
input sb_va_val_l;
input cam_reg_hld;
input ic_tlb;
input ic_tlb_state;
input r_ic_tlb;
input r_tlb_miss;
input r_dc_tlb;
input r_wr_tlb;
input dc_tlb;
input dc_tlb_state;
input wr_tlb;
input r_ic_tlb_pnd;
input r_mstb_l;
input mm_dccfstb;
input mmulgc_bp_hit;
input iwait_state;
input pipe_moved;
input [3:0] mm_mreq;
input io_issue_req;
input io_tlb_tw;
input root_tw;
input pt1_tw;
input pt2_tw;
input tw_pte_chk;
input dc_tlb_tw;
input wr_tlb_tw;
input ic_tlb_tw;
input asi_dcd9_w;
input io_tw_wrt; // IO Tablewalk sm TLB write state
input sr_tw_wrt; // IU Tablewalk sm TLB write state
input sb_cyc_pnd; // PIO cycle pending in SBC
input dmiss_for_m; // Force Dmiss for modified bit case
input ipar_valid;
input dpar_valid;
input ic_par_state;
input dc_par_state;
input mm_dstat_avail;
input mm_istat_avail;
input dc_in_par;
input r_dc_in_par;
input r_ic_in_par;
input r_sb_par;
input mmu_asi_op; // ASI op in progress
input r_ic_miss; // Reg'd ic_miss
input r_dc_miss; // Reg'd dc_miss
input dc_miss_sustain; // Reg'd dc_miss
input ic_miss_sustain; // Reg'd dc_miss
input iu_sfs_sup; // IU fault status supervisor bit
input [1:0] iu_sfs_perr; // IU fault status Parity error
input iu_sfs_xerr; // IU fault status translation error
input iu_sfs_mmiss; // IU fault status TLB miss (software tw)
input iu_sfs_iae; // IU fault status Invalid Address Error
input iu_sfs_sbe; // IU fault status Sbus error
input iu_sfs_sto; // IU fault status Sbus timeout
input iu_sfs_prtct; // IU fault status protection exception
input iu_sfs_priv; // IU fault status privilege exception
input [1:0] iu_sfs_lvl; // IU fault status PTE level field
input iu_mm_iacc_wp_exc_d; // IU instr watchpoint trap trigger
input r_sb_ic_op; // Last PIO op was for an I-cache miss
input tb_error; // TLB error output (raw)
input r_io_space; // PAR contains I/O space address
input r_cntl_space; // PAR contains Control space address
input r_pci_space;
input mm_iabort; // I-cache translation aborted
input mm_cpsb_wrt; // PIO write
input pio_data_rcvd; // PIO read data received
input r_drd_c1; // Marb state DRD_C1 reg'd
input dc_stream; // D$ streaming (perf. trigger)
input ic_stream; // I$ streaming (perf. trigger)
input ihold_d1; // MMU perf counter trigger
input dhold_d1; // MMU perf counter trigger
input dc_shold; // MMU perf counter trigger wb full
input did_ifetch; // MMU perf counter trigger
input did_dfetch; // MMU perf counter trigger
input fhold_d1; // MMU perf counter trigger
input fhold_fqfull_d1; // MMU perf counter trigger
input iu_sup_mode; // MMU perf counter trigger
input mm_page; // MMU perf counter trigger
input sr_tw; // MMU perf counter trigger
input pcntr_a_co; // MMU perf counter trigger
input pcntr_b_co; // MMU perf counter trigger
input [2:0] p_reply_dec; // AFX queue status (# of entries)
input precharge_early_0;
input precharge_early_1;
input odd_wd; /* Last memory op for an odd word */
input sel_cache_stat; /* MMU register select decode */
input mc_afx_to; /* AFX timeout indicator */
input afx_qbusy; /* AFX Queue busy */
input r_fb_space;
input ldtlb_data_tw;
input [2:0] w_sp_sel; // Speed select (for mmu status)
input [1:0] w_div_ctl; // Divide by cntl (mmu status)
input iu_in_trap;
input hold_fetch_f_l; // Holds fetch logic
input ss_clock;
input ss_reset;
input ss_reset_any;
input ss_scan_mode;
/*************************************************************************/
/****** Register definitions ******/
/*************************************************************************/
wire asi_err_cntl ; // forward
wire pa_reg_dcd ; // forward
wire wr_bypass ; // forward
wire trig_a_term ; // forward
wire [31:00] mfsr;
wire par_asi_vld; //forward
wire iacc_wp_e ; //forward
wire enbl_scan_bp; // forward (MMU scan brkpt enable)
/* */
/*************************************************************************/
/* MMU Control Register (currently 32-bits). */
/*****************************************************************************/
/* PCR register definition */
/* */
/* +-----+-----+--+--+--+-----+--+--+--+--+--+---------+--+--+--+----+--+--+ */
/* | IMPL| VER |ST|WP|BF| PMC |PE|PC|AP|AC|BM| RFR CNTL|IE|DE|SN|rsvd|NF|EN| */
/* +-----+-----+--+--+--+-----+--+--+--+--+--+---------+--+--+--+----+--+--+ */
/* 31 28 27 24 23 22 21 20 19 18 17 16 15 14 13 10 09 08 07 06 02 1 00 */
/* */
/* */
/* mmu_cr_rega definition (power-on reset only) */
/* +-----------+--+--+--+-----+--+--+--+--+--+---------+-----+--+----+--+--+ */
/* | |ST|WP|BF| PMC |PE|PC|AP|AC| | RFR CNTL| |SN| |NF| | */
/* +-----------+--+--+--+-----+--+--+--+--+--+---------+-----+--+----+--+--+ */
/* 14 13 12 11 10 09 08 07 06 05 02 01 00 */
/* */
/* mmu_cr_regw definition (watchdog reset or power_on reset) */
/* +--------------------------------------+--+---------+--+--+----------+--+ */
/* | |BM| |IE|DE| |EN| */
/* +--------------------------------------+--+---------+--+--+----------+--+ */
/* 03 02 01 00 */
/* mmu_cr_reg definition */
/* +-----------+--+--+--+-----+--+--+--+--+--+---------+--+--+--+----+--+--+ */
/* | |ST|WP|BF| PMC |PE|PC|AP|AC|BM| RFR CNTL|IE|DE|SN| |NF|EN| */
/* +-----------+--+--+--+-----+--+--+--+--+--+---------+--+--+--+----+--+--+ */
/* 18 17 16 15 14 13 12 11 10 09 08 05 04 03 02 01 00 */
/* */
/*****************************************************************************/
/*** mmu_cr_in for PCR that isn't reset on soft resets *******************/
wire [14:00] mmu_cr_in = {misc_in[23:15],
misc_in[13:10],
misc_in[07],
misc_in[01]};
wire [14:00] mmu_cr_rega;
MflipflopR_15 mmu_cr_rega_15( mmu_cr_rega, mmu_cr_in[14:00], /* data loaded from the MDATA bus*/ ss_clock,hld_mmu_cr,ss_reset) ; /* load enable for MMU_CR*/
/*** reset_any should ONLY be used for: mmu_en, dc_en, ic_en, boot mode. */
wire [3:0] mmu_cr_inw = {~misc_in[14],misc_in[09:08],
misc_in[00]};
wire [3:0] mmu_cr_regw;
MflipflopR_4 mmu_cr_regw_4( mmu_cr_regw, mmu_cr_inw[3:0], /* data loaded from the MDATA bus*/ ss_clock,hld_mmu_cr,ss_reset_any) ; /* load enable for MMU_CR*/
wire scalared [18:00] mmu_cr_reg = {mmu_cr_rega[14:06],mmu_cr_regw[3],
mmu_cr_rega[05:02],mmu_cr_regw[2:1],
mmu_cr_rega[01:00],mmu_cr_regw[00]};
wire mmu_en_e = mmu_cr_reg[0];
/*** Second register to sync updating PCR with pipeline execution ******/
wire [18:00] mmu_cr_out;
MflipflopR_19 mmu_cr_19( mmu_cr_out, mmu_cr_reg[18:00], /* data loaded from mmu_cr_reg */ ss_clock,iu_pipe_hold,ss_reset) ; /* iu_pipe_hold load enable */
wire scalared [31:00] mmu_cr = {4'b0000, // IMPLIMENTATION # 0
4'b0100, // VERSION # 4
mmu_cr_out[18:11],
mmu_cr_out[10],
~mmu_cr_out[09],
mmu_cr_out[08:02],
5'b0,mmu_cr_out[1:0]};
assign mm_rfr_cntl = mmu_cr_reg[08:05]; //Non-piped version for Memif
assign mm_oddpar = mmu_cr_reg[12] ; // Non-piped version
assign enbl_br_fold = mmu_cr_out[16];
wire [2:0] at_t;
wire [2:0] data_acc_t ; // forward
/*** Boot Mode decode ****************************************************/
/*** This is on when the PCR.bm bit is set AND an instruction ***/
/*** space access is being made (from either the I$ or D$). ***/
wire instr_space = (dc_tlb_state & data_acc_t[1]) | ic_tlb_state ;
// Changed boot_mode to switch only when pipe moves see BUG #559
// old model used the line below to change boot_mode with ASI_OP
// but this may cause a problem if we have an I$ miss during the
// W-stage of the ASI_OP
// assign boot_mode = mmu_cr[14] & ~mmu_cr_reg[9] &
//
assign boot_mode = mmu_cr[14] &
instr_space & ~bypass_mmu_asi &
(ic_tlb_state | dc_tlb_state) ;
/*************************************************************************/
assign mm_page_hit_en = mmu_cr[20:19];
assign mm_fbpage_en = mmu_cr[16];
/*** Software tablewalk enable *****************************************/
// change these to switch at pipe move time.
// assign enbl_soft_tw = mmu_cr[23] & mmu_cr_rega[14] ;
assign enbl_soft_tw = mmu_cr[23] ;
assign mm_parity_en = mmu_cr_reg[13] ;
/*** Watchpoint trap enable **********************************************/
// change these to switch at pipe move time.
// wire wp_trap_en = mmu_cr[22] & mmu_cr_rega[13];
wire wp_trap_en = mmu_cr[22];
/*** Supervisor mode NON-cache allocate for STore misses *****************/
assign sup_nalloc = mmu_cr[07] ;
wire [1:0] r_perr;
Mflipflop_r_2 perr_ff_2(r_perr,dp_perr,~ss_reset,ss_clock) ;
wire perr_dcd = dp_perr[1] | dp_perr[0] ;
wire r_perr_dcd = r_perr[1] | r_perr[0] ;
/* */
/*****************************************************************************/
/*** TLB Replacement Control Register (TRCR[5:0]) also TLB addr mux. ***/
/*** ***/
/*** TLB Replacement Control Register is incremented every clock to ***/
/*** produce a psuedorandom replacement address. The counter is a ***/
/*** standard 6-bit incrementer. ***/
/*** ***/
/*** forced bit 5 of wrap ctl, and addr to tlb to zero ***/
/*****************************************************************************/
/* TRCR register definition */
/* */
/* +--------+-----+------+----+------+--------+----+-+--------+----+-+-----+ */
/* | rsvd | BUS |MEMSP |VPTP| rsvd | PTP LK | IOL|0|WRAP CTL| CTL|0| ADDR| */
/* +--------+-----+------+----+------+--------+----+-+--------+----+-+-----+ */
/* 31 25 24 23 22 21 20 19 17 16 14 13 11 10 07 06 05 04 00 */
/* */
/*****************************************************************************/
/***** Register definition for the tc control bit. */
wire trcr_cntl_out;
MflipflopR_1 trcr_cntl_1(trcr_cntl_out,misc_in[6],ss_clock,hld_trcr,ss_reset) ;
/***** Register definition for the roll over point */
wire[5:0] roll_cntl_out;
MflipflopR_6 roll_cntl_6(roll_cntl_out,{1'b0,misc_in[11:07]},ss_clock,hld_trcr,ss_reset) ;
/***** Register definition for the i/o lock control bit. */
wire io_lock_cntl_out;
MflipflopR_1 io_lock_cntl_1(io_lock_cntl_out,misc_in[13],ss_clock,hld_trcr,ss_reset) ;
/***** Register definition for the roll over point */
wire[2:0] ptp_lock_cntl_out;
MflipflopR_3 ptp_lock_cntl_3(ptp_lock_cntl_out,misc_in[16:14], ss_clock,hld_trcr,ss_reset) ;
/***** Register definition for Alternate Cache-ability ACC bits *****/
wire virt_ptp2;
MflipflopR_1 virt_ptp2_ff_1(virt_ptp2,misc_in[20],ss_clock,hld_trcr,ss_reset) ;
/*****************************************************************************/
/* check for roll over point, and init to 0,1,2, or 3 if rollover found) */
/* init to 0 if no PTP locking */
/* init to 1 if PTP0 locked down */
/* init to 2 if PTP1 locked down */
/* init to 3 if PTP2 locked down */
wire [5:0] trcr_addr_out;
wire [5:0] trcr_incr_out = {1'b0, (trcr_addr_out[4:0] + 5'b1)} ;
/*****************************************************************************/
/*** reset the counter if we get to 48 with io lock mode or if we reach ***/
/*** the wrap point as set in the trcr reg. ***/
wire sel_incr = ~(((trcr_addr_out == roll_cntl_out) & (|roll_cntl_out)) |
((trcr_addr_out == 6'b101111) & io_lock_cntl_out));
wire[5:0] trcr_init = 6'b0;
wire [5:0] trcr_mux1_out;
// Expanded macro begin.
// cmux2(trcr_mux1, 6, trcr_mux1_out[5:0], trcr_init, trcr_incr_out, /* output of incrementer.*/ sel_incr)
function [6:1] trcr_mux1 ;
input [6:1] in0_fn ;
input [6:1] in1_fn ;
input select_fn ;
reg [6:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
trcr_mux1 = out_fn ;
end
endfunction
assign trcr_mux1_out[5:0] = trcr_mux1( trcr_init, trcr_incr_out, /* output of incrementer.*/ sel_incr) ;
// Expanded macro end.
/* A mux (2:1) selects the TRCR input from either misc_in or the counter.*/
wire [5:0] trcr_mux_out;
// Expanded macro begin.
// cmux2(trcr_mux, 6, trcr_mux_out[5:0], misc_in[5:0], /* data input*/ trcr_mux1_out, /* output of incrementer/ init mux */ hld_trcr)
function [6:1] trcr_mux ;
input [6:1] in0_fn ;
input [6:1] in1_fn ;
input select_fn ;
reg [6:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
trcr_mux = out_fn ;
end
endfunction
assign trcr_mux_out[5:0] = trcr_mux( {1'b0, misc_in[4:0]}, /* data input*/ trcr_mux1_out, /* output of incrementer/ init mux */ hld_trcr) ;
// Expanded macro end.
/* hold enable for trcr.*/
/* Control for loading trcr_addr register. */
wire hld_trcr_addr = ((trcr_cntl_out & hld_trcr) | tw_trcr_hld);
/***** Register definition for the address portion of TRCR. */
MflipflopR_6 trcr_addr_ff_6(trcr_addr_out,trcr_mux_out,ss_clock, hld_trcr_addr,ss_reset) ;
/*** select the appropriate tlb addr for tw writes ************************/
/*** This function checks to see what kind of TLB write op is going ***/
/*** to be done. Then it makes sure that the tlb addr is properly set ***/
/*** for that operation. ***/
wire [5:0] r_tlb_addr;
function [5:0] tlb_addr_sel;
input [5:0] trcr_addr_out;
input io_tlb_tw;
input root_tw;
input pt1_tw;
input pt2_tw;
input io_lock_cntl_out;
input [2:0] ptp_lock_cntl_out;
input probe;
input tw_trcr_hld;
input trcr_cntl_out;
input [5:0] r_tlb_addr;
begin
case(1'b1)
/*** force upper 2 bits for io lock mode *****************************/
(io_tlb_tw & io_lock_cntl_out & ~tw_trcr_hld & ~trcr_cntl_out):
tlb_addr_sel = {2'b11, trcr_addr_out[3:0]};
/*** force to 0 for root level write & ptp0 lock *********************/
(~io_tlb_tw & root_tw & ptp_lock_cntl_out[0] &
~probe & ~tw_trcr_hld & ~trcr_cntl_out):
tlb_addr_sel = 6'b0;
/*** force to 1 for level 1 write & ptp1 lock ************************/
(pt1_tw & ptp_lock_cntl_out[1] & ~probe & ~tw_trcr_hld &
~trcr_cntl_out):
tlb_addr_sel = 6'b000001;
/*** force to 2 for level 2 write & ptp2 lock ************************/
(pt2_tw & ptp_lock_cntl_out[2] & ~probe & ~tw_trcr_hld &
~trcr_cntl_out):
tlb_addr_sel = 6'b000010;
/*** force to 8 on PTE write with ptp0 lock and count of 0 ***********/
(ptp_lock_cntl_out[0] & ~root_tw & ~tw_trcr_hld &
~trcr_cntl_out & (trcr_addr_out == 6'b0)):
tlb_addr_sel = 6'b000011;
/*** force to 9 on PTE write with ptp1 lock and count of 1 ***********/
(ptp_lock_cntl_out[1] & ~pt1_tw & ~tw_trcr_hld &
~trcr_cntl_out & (trcr_addr_out == 6'b1)):
tlb_addr_sel = 6'b000100;
/*** force to 10 on PTE write with ptp2 lock and count of 2 ***********/
(ptp_lock_cntl_out[2] & ~pt2_tw & ~tw_trcr_hld &
~trcr_cntl_out & (trcr_addr_out == 6'b10)):
tlb_addr_sel = 6'b000101;
/*** force old value if tw_trcr_hld is on ***************************/
(~trcr_cntl_out & tw_trcr_hld):
tlb_addr_sel = r_tlb_addr;
default:
tlb_addr_sel = trcr_addr_out;
endcase
end
endfunction
wire [5:0] tlb_addr_in = tlb_addr_sel(trcr_addr_out, io_tlb_tw, root_tw,
pt1_tw, pt2_tw, io_lock_cntl_out,
ptp_lock_cntl_out, probe, tw_trcr_hld,
trcr_cntl_out, r_tlb_addr);
Mflipflop_r_6 tlb_addr_ff_6(r_tlb_addr,tlb_addr_in,~ss_reset,ss_clock) ;
/***** Mux (2:1) that produces TLB addr from trcr_out OR dva[7:2]. */
wire [5:0] tlb_addr;
// Expanded macro begin.
// cmux2(tlb_addr_mux, 6, tlb_addr, tlb_addr_in, r_dva_7_2[7:2], asi_dcd6)
function [6:1] tlb_addr_mux ;
input [6:1] in0_fn ;
input [6:1] in1_fn ;
input select_fn ;
reg [6:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
tlb_addr_mux = out_fn ;
end
endfunction
assign tlb_addr = tlb_addr_mux( tlb_addr_in, r_dva_7_2[7:2], asi_dcd6) ;
// Expanded macro end.
// wire [24:0] tlb_rcr = {w_div_ctl, w_sp_sel[1:0], changed speed select to boot mode select
wire [24:0] tlb_rcr = {w_div_ctl, bm_sel[1:0],
virt_ptp2,3'b0,ptp_lock_cntl_out,io_lock_cntl_out,
roll_cntl_out, trcr_cntl_out, trcr_addr_out};
/* */
/*****************************************************************************/
/*** AFX Queue control and status registers ***/
/*** This is a 1-bit register that defines when the AFX Queue is "full" ***/
/*** for Processor reads (stalls read request until "empty"). ***/
wire hld_afx_qlvl = ~(pa_reg_dcd & (mm_pa[15:00] == 16'h4000) &
mmstben_reg);
wire afx_qlvl;
MflipflopR_1 afx_qlvl_ff_1(afx_qlvl,misc_in[00],ss_clock,hld_afx_qlvl,ss_reset) ;
/*********************************************************************************/
/* MID register (contains SBAE in bits [20:16]) */
/* */
/* +---------------------+--------------+----------------------------------+ */
/* | reserved | SBAE[4:0] | reserved (reads as 0x0008) | */
/* +---------------------+--------------+----------------------------------+ */
/* 31 22 21 16 15 00 */
/* */
/* Changed to the following */
/* +-------------+--------------+----------+--------+--------+-----------------+ */
/* | reserved | SBAE[4:0] | reserved | clk_sp | ROM_sp | (reads as 0x8) | */
/* +-------------+--------------+----------+--------+--------+-----------------+ */
/* 31 22 21 16 15 11 10 08 07 04 03 00 */
/* */
/* Changed to the following */
/* +-------------+--------------+----------+--------+--------+-----------------+ */
/* | reserved | SBAE[4:0] | rsrvd |sb| clk_sp | ROM_sp | (reads as 0x8) | */
/* +-------------+--------------+----------+--------+--------+-----------------+ */
/* 31 22 21 16 15 12 11 10 08 07 04 03 00 */
/* */
/*********************************************************************************/
reg turn_off_standby_ss ;
always@(posedge ss_clock)
if (ss_reset)
turn_off_standby_ss <= #1 1'h1 ;
else
turn_off_standby_ss <= #1 turn_off_standby ;
assign pa_reg_dcd = (mm_pa[30:16] == 15'h1000) & par_asi_vld ;
wire hld_mid = ~(pa_reg_dcd & (mm_pa[15:00] == 16'h2000) & mmstben_reg);
wire hld_mid_standby = ~(pa_reg_dcd & (mm_pa[15:00] == 16'h2000) & mmstben_reg) &
~turn_off_standby_ss ;
wire [5:0] mid_out;
wire mm_go_standby;
wire mm_go_standby_in = turn_off_standby_ss ? 1'b0 : misc_in[11] ;
MflipflopR_1 mid_1(mm_go_standby, mm_go_standby_in, ss_clock, hld_mid_standby, ss_reset) ;
MflipflopR_6 mid_6(mid_out,({5'b0, misc_in[16]}),ss_clock,hld_mid,ss_reset) ;
// MflipflopR_6 mid_6(mid_out, misc_in[21:16], ss_clock,hld_mid,ss_reset) ;
// mm_go_standby
// adding a bit to the mid register to allow a programmable standby operation by the cpu.
// Changed mm_rom_module_speed to always reset to 4'hf
// Changed mm_go_standby to macro register, and force hld_mid off and input to zero durring
// time while turn_off_standby is active.
// Note: the reset to this mm_go_standby bit is questionable, and may need watchdog resets.
reg [3:0] mm_rom_module_speed ;
always@(posedge ss_clock)
| This page: |
Created: | Thu Aug 19 12:02:48 1999 |
| From: |
../../../sparc_v8/ssparc/mmu/m_mmu_cntl/rtl/rl_mmu_regs.v
|