What's New on The Virtex Web Site

Technical Briefs     Bandwidth (Virtex-E)   I/O Bandwidth Scalable to 200 Gbps   Eight High Performance DLLs   Maximizing Bandwidth Using Double Data Rate Memory   SelectI/O+ Technology   Differential Signaling: LVPECL, LVDS, Bus LVDS   True Dual-Port Embedded Block Memory   Packaging, Software & Intellectual Property System Tools    Power Estimator SelectLink Design Tool ZBT SRAM Timing Calculator to view the  PDF files below.

Customer Testimonials Applied Signal Apptitude Packet Engines (Alcatel) Performance Technologies Qualcomm Tektronix Tech Topic SelectLink(tm) Technology Low Voltage Differential Signaling (LVDS) High Speed Transceiver Logic (HSTL) Virtex Delay Locked Loop (DLL) Virtex series demonstration and prototype platforms now available for customers!

Application Notes & Reference Designs
 

Title Version Size Reference Design Date XAPP211: PN Generators Using the SRL Macro 1.0 64K Reference Design 2/4/00 XAPP233: Multi-channel 622 MHz LVDS Data Transfer With Virtex-E Devices 1.0 330K Reference Design 12/22/99 XAPP235: Virtex-E Package Compatibility Guide  1.1 29K 1 11/15/99 XAPP232: Virtex-E LVDS Drivers and Receivers: Interface Guidelines 1.0 175K 1 10/5/99 XAPP230: The LVDS I/O Standard 1.1 69K 1 11/16/99 XAPP205: Data-Width Conversion FIFOs using Virtex Block SelectRAM Memory 1.1 41K Verilog 10/25/99 XAPP204: CAM in Block Select RAM  1.1 102K VHDL 10/1/99 XAPP200:  Double Data Rate SDRAM 1.2 76K VHDL, Verilog 10/12/99 XAPP158: Powering Virtex FPGAs 1.1 35K 1 11/16/99 XAPP139: Virtex Configuration and Readback through Boundary Scan 1.0 88K 1 10/28/99 XAPP133:  Using the Virtex SelectI/O 1.2 115K  1 10/11/99 XAPP132:  Using the Virtex Delay-Locked Loop 1.4 73K  1 10/11/99

Press Releases

Title	Date
Sales of Xilinx Virtex FPGAs Surpass $100 Million	February 14, 2000
New Xilinx SelectLink Technology Supports 80 Gigabits Per Second Interface Between FPGAs	February 7, 2000
Xilinx, Los Alamos Laboratory Team Up On Space-Based Reconfigurable Data Processing	January 26, 2000
ComStruct VME/C6420 With Xilinx Virtex-Based PMC Provides Powerful Solution For 3G And Signal Intelligence	January 25, 2000
Xilinx Offeres Suite Of Low cost Prototyping Boards For Developing Virtex FPGAs	December 16, 1999
Xilinx Releases 16 New Parameterizable Cores On IP Center For Viretx Series	November 30, 1999
DARPA Chooses Xilinx to Develop Tools for Internet Reconfigurable Logic	November 16, 1999
Xilinx and Applied Telecom Announce Inverse Multiplexer ATM Solution for Virtex-E FPGAs	November 15, 1999
Xilinx Launches Silicon Xpresso Design Reuse Initiative For Programmable Logic	November 1, 1999
Xilinx And AllianceCORE Partners Showcase New Virtex-E System-Level Solutiond At DSP World	November 1, 1999
Xilinx FPGAs Provide Spring Tide Networks With Alternative to ASICs	October 25, 1999

More Information Virtex Overview  System Memory  System Performance/Bandwidth System Interface System Design Tools Data Sheets Application Notes

Product Information Software IP Center Hard Copy Literature Request