Accellera SV-EC Technical Committee

SystemVerilog Extensions Committee

The SV-EC is the subcommittee of the Accellera SystemVerilog Technical Committee tasked with
maintaining and extending the System Verilog language.
The primary extension the committee is currently working towards is to add
native testbench support to System Verilog.
The committee is also responsible for releasing the SystemVerilog 3.1 specification.

Chair: David W. Smith, Synopsys
Co-Chair: Stefen Boyd, Boyd Technology

Links

mailto:sv-ec@eda.org
SV-EC Email Reflector Archives

SV

Post-3.1 Issues
SV Chairs and Champions Response

SV LRM

SystemVerilog 3.1 LRM (Approved by TCC and SV Committees)

SystemVerilog 3.1 Ballot Draft Specification (for Board)
Results for all committes on sending Ballot Draft to the board
LRM Issues and Changes to Draft 6
LRM Issues and Changes to Draft 5
LRM Issues and Changes to Draft 4
SystemVerilog 3.1 Draft 6 Specification
SystemVerilog 3.1 Draft 5 Specification
SystemVerilog 3.1 Draft 4 Specification
SystemVerilog 3.1 Draft 3 Specification
SystemVerilog 3.1 Draft 3 BNF (Hypertext version)

Milestones and Meeting Schedule

Meeting Minutes

SV-EC LRM Documentation

Action Items
LRM 3.1 Changes
Requests from other committees
Extensions and Proposals
Issues for Review

SV-EC Documentation

SV-EC Operating Guidelines

SystemVerilog 3.0 Specification

Testbench Donation
Testbench Clarification
Testbench Clarification Presentation
SystemVerilog Testbench Extension Version 2.2

Scheduling Semantics Documentation

Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics (paper)
Achieving Determinism in SystemVerilog 3.1 Scheduling Semantics (presentation)

Email Reflector Subscriptions

To subscribe to the SV-EC email reflectors,
please send an email to majordomo@eda.org with the following in the body of the email:

subscribe sv-ec <email address>