// REGFILE SPECIFIERS FROM IR PIPE (FOR COMPARISONS)

output hld_dirreg;		// another DIR hold
output hld_dirreg_rf;		// another DIR hold
//output hld_drs1_reg;		// hold d_rs1 register

/* don't need cuz Mir is in Mdecode now
input [4:0] d_rs1;		// RS1 in Decode
input [4:0] d_rs2;		// RS2 in Decode, also low 5 bits of disp22

input [4:0] e_rd;		// RD in Execute
input [4:0] w_rd;		// RD in W (logical)
input [7:0] w_rdp;		// RD (physical) in Write
 */

// CWP's

input [2:0] cwpm_;		// CWP master (active low)
input [2:0] ecwpm_;

/* don't need cuz Mir is in Mdecode now
output hnop_into_ex;		// force HNOP into E stage
output htrap_into_ex;		// force HTRAP into E stage
output clr_e_iexc_nop;
 */

output TRAP;			// trap detected NOW
output [7:0] trapcode;		// W cycle trap encoding for TT
//output iu_trapd_iaer;		// tell MMU if IU has an iacc err
input resultMSB;		// MSB of result
input [6:0] result_lo;		// least sig. 7 bits used for ticc TT #

//input sgnA;			// bit[33] of alu src1 input
//input sgnB;			// ditto for alu src2 input
input high_2_1;			// sgn bit of 34 bit add
output idiv_shiftin_low;	//
input alu_s1m_0;		// low order bit of alu src1 input

output byte_mark0_e;
output byte_mark1_e;
output byte_mark2_e;
output byte_mark3_e;

output sadr_tbr;		// select address from TBR
//output sadr_aa;			// select address from address adder
output sadr_jmprett;		// select address from ALU
output sadr_zero;		// select 0 for address

output hld_dpc;			// hold the value of DPC
output hld_dum_dpc;
//output rtrap_hldpc;		// hold pc chain for 1 cycle for R traps
//output cheat_pcfwd;		// cheat and move PC's around in case
				// of a jmp and iacc trap in its delay slot

output alus1_b1m;		// alu src1 controls - bypass 1
output alus1_b2m;		// bypass 2
output alus1_b3m;		// bypass 3
output alus1_datam;		// data bypass

output alus1_rfm_b3m;		// regfile
output alus1_setm;		// sethi data

output alus2_b1m;		// alu src2 controls - bypass 1
output alus2_b2m;		// bypass 2
output alus2_b3m;		// bypass 3
output alus2_datam;		// data bypass

output byp_res3;
output byp_wr3;
output byp_rf3;

//output alus2_rfm_im_b3m;	// regfile
output a2top_default;
output rs2_passit;		// select main data thru MUX
output alu_s2_reg_hold;		// hold alu src2 register

input [5:0] alu_s2m_5_0;	// src2 reg for ALU - bits 5 to 1 only
input [3:0] src2m_lo;		// low 4 bits of RF B port

output rs1_pass;		// pass RF src1 to register
output spc_mux_default;		// also pass RF src1 to reg.  diff mux
output rs1_clear;		// clear RF src1 to register
output rs1_double;		// sll 1 RF src1 to register
output nrs1_negate;		// negate RF src1 to register
output nrs1_negate_l;		// same but active low
output sel_srl2_mult;		// select srl2 result to register
output rs2_clear;		// clear RF src2 to register
output nsel_w_mult;		// select W result to alu
output nsel_w_mult_l_b;		// not select W result and b
output nsel_w_mult_l_not_b;	// not select W result and invert b

output sel_sll1_divalu;		// Shift alu result 1 left WITH W
output sel_sll1_divalu_l;	// not Shift alu result 1 left WITH W

output msign_bit;		// op in D is signed mult
input src1m_msb;		// op in D is signed mult
output dsign_bit2;		// op in D is signed div
input rf2_imm_data_msb;		// op in D is signed div
output dsign_bit1;		// op in D is signed div
output hold_Wreg;		// hold result register

output eopc_hidiv3;		// HIDIV3 is in E

output use_hi_y;		// use y for sgn ext bit[33:32] alu src1 -idiv
output use_hi_alu;		// use alu output - idiv
output use_hi_rs1_default;	// use default - idiv

output use_hi_rs2;		// use RF B for sgn ext bit[33:32] alu src2-id
output use_low_rs1;		// use low bit of src1 register - idiv
output use_hi_rs2_default;	// use default - idiv
output not_rs2_rs1_default;	// not the above 3 select

output alus1_b2_shift;		// idiv corr step - Shift bypasss2 select
output sel_rs1_shiftin;		// idiv loop step - Shift aluout select

// input [1:0] which_byte_;	// lsb's of address for store alignment

/* don't need cuz Mir is in Mdecode now
output result_r0;		// force %g0 into rd_rslt
 */

output alu_ADD;			// ALU control
output alu_AND;
output alu_XNOR;

//output [4:0] shift_cnt;		// BARREL SHIFTER CONTROL
output shift_left;
output arith_shift;

input [2:0] ym;	// Y register

input [3:0] alu_cc_next;	// alu cc direct from alu
input ccN_noninv;		// non-inverted ccN input from Mexec
input ccZ_noninv;		// non-inverted ccZ input from Mexec
input [3:0] ccm;	// cc direct from alu

output ne_mulsm;
output next_e_not_negmul;

output hld_y;			// Y register controls
output wr_y;
output wr_mulscc;
output n_ymsb;

output carry_in;		// carry in to ALU

output pass_hi_rs1;		// pass high bit of alu src1 (was clr_hi_rs1)

output det_divovf;		// idiv overflow

output tagged_ovf;		// detect tagged ovf
output alu_sub;			// Used to invert Carry out on subtracts

input [1:0] alu_s1s_lsb2;	// alu_s1s[1:0] from datapath (exec.v)

output rs_from_alu;
output rs_from_else;
output rs_from_sh;
output force_neg;			// for signed (neg) idiv ovf
output force_pos;			// for signed (pos) idiv ovf

output e_rdpsrm;			// special mux control
output e_rdwimm;
output e_rdym;
output e_rdtbrm;
output e_jmpcallm;
output sel_pcspec_l;
output rdtpcm;

output w_wrpsr;			// CWP and CC control

output hold_cc;			// hold CC's
output load_cc;			// load CC's from ALU
output write_cc;		// write CC's (wrpsr)
output restore_cc;		// restore CC's on trap of setcc instr.

output clret_sets;		// ET controls
output setet_ps2s;
output write_etps;
output hold_ets;

output s_into_ps;		// PS controls
output hold_ps;

output hld_pilefec;		// clock hold for PIL, EF, and EC

output cwp_inc;
output [2:0] wcwpm1;             // w - stage cwp - 1 (for WRPSR)
output [2:0] cwpp1;              // cwp + 1 (for WRPSR)
output [2:0] cwpm1;              // cwp - 1 (for WRPSR)
input [2:0] wcwp;              	// 
input [2:0] cwp;              	// 
output cwp_dec;
output cwp_hold;
output ecwp_next;
output cwp_recirc;

output hld_wim;			// WIM clock hold
input [7:0] wimm;		// early master latched wim

output hld_tba;			// hold control for TBA
output hld_tt;			// hold control for TT
output n_hld_tt_scan;		// not hold control for TT and not ss_scan_mode

/* don't need cuz Mir is in Mdecode now
output write_r15;		// RD control into W stage
output write_r18;
 */

/*
output m3b3;                     // select for mux3 from byte 3
output m3b2;                     // select for mux3 from byte 2
output m3b1;                     // select for mux3 from byte 1
output m3b0;                     // select for mux3 from byte 0
output m20;                      // select for mux2 from 0
output m2b2;                     // select for mux2 from byte 2
output m2b0;                     // select for mux2 from byte 0
output m2s0;                     // select for mux2 from sign 0
output m2s2;                     // select for mux2 from sign 2
output m0m10;                    // select for mux0 & 1 from 2
output m0m1b0b1;                 // select for mux0 & 1 from byte 0 byte 1
output m0m1s0;                   // select for mux0 & 1 from sign 0
output m0m1s2;                   // select for mux0 & 1 from sign 2
output m0m1m2s1;                 // select for mux0 & 1 & 2 from sign 1
output m0m1m2s3;                 // select for mux0 & 1 & 2 from sign 3
*/
output wr_lddatam_l;             // select for write from result


//output crossover_dm;		// rd -> rs1 for STD
//output crossover_sm;		// rd -> rs1 for all other stores
//output no_crossover;		// don't do a crossover
//output pcrossoverm;		// pipelined version of crossover for STD

/* don't need cuz Mir is in Mdecode now
output d_rd_hstd_sel;
 */
output word_store_d;
output half_store_d;
output byte_store_d;

/* don't need cuz Mir is in Mdecode now
output clear_rd0m;		// rd_ex & 0x1e for LDD and STD
output set_rd0m;		// rd_ex | 1
 */

input s;			// Supervisor bit from PSR
input ns;			// next supervisor bit
input psm;			// Previous Supervisor bit from PSR
input et;			// Enable trap bit from PSR
input ef;			// Enable FPU bit
input [3:0] pil;		// Processor Interrupt Level from PSR

input [4:0] alu_out_lsb5;	// least significant 5 bits of alu output

input mm_dacc_exc_w;		// W cycle data access exception
input mm_dacc_err_w;		// W cycle data access error

input mm_dacc_mmu_miss_w;
input mm_dacc_wp_w;

output iu_mm_iacc_wp_exc_d;	// IU detected potential WP trap in D

input start_itag_inv;
input q3_iae, q3_ptc, q2_iae, q2_ptc, q1_iae, q1_ptc;
output stop_fetch;
output did_fetch;		// for MMU performance counters

output this_s;
output sup_ex_trap;

input FEXC;			// FPU Exception input

input iwait_f;
input dwait_w_for_flush;

// signals for MMU
output ld_op_e;
output ld_op_e_mmu;
output ld_op_d;
output sgnd_ld_e;
output st_op_e;
output st_op_e_mmu;
output st_op_d;
//output flush_ic_e;
//output flush_ic_d_raw;
output fpu_mem_e;
output [1:0] size_e;

output hld_car_mar;			// CAR hold control
output hld_lgens;

//output hld_mar;			// hold MAR register

output rf_we_w;			// register file write enable

output error_mode;		// Error state - pipelined a bit
output ER_SDOUT;		// entry into error state

input [1:0] pfcc;		// latched FCC bits
input pfccv;			// on-chip fccv

input ss_clock;			// system clock

input hold;			// chip hold
input hold_noic;
input hold_ic;
// input extend_tag_miss;
input enbl_br_fold;

output w_hhn_2;

output lta_hold;

output reset;			// synchronized reset 3
//output enbl_fetch;

output iu_iflush_e;		// IFLUSH in E
output valid_decode;

output select_FP_DOUT;		// during st, use FP data, not IU
output sel_ldstb_1;
output select_IU_DOUT;		// during st, use IU data
output IU_in_trap;		// Tell CC that we are trapping
output IU_in_trap4fpu;		// Tell FPU that we are trapping
output IU_in_trap4dc;		// ditto to D$
// output iu_inst_trap_w;		// Tell MMU we have inst related trap

output FXACK;			// ack FP exceptions for FPU
//output iu_help_w;		// help inst in W

// output iu_fetch_f;		// fetch in F stage

input ss_reset;         // asynchronous reset input
input [3:0] IRL;        // Interrupt Request Level Input to IU

/* don't need cuz Mir is in Mdecode now
input [5:0] e_asim;     // E state ASI
 */

output [5:0] iu_asi_e;  // Address Space Identifier for E

// stuff for queue and pc generation
output sel_lta_fpc;
output sel_idpc_fpc;
output sel_post_reset;
output sel_p_fpc;
output sel_alt_tag;
output sel_i1pfpc_fpc;
output sel_i2dpc_fpc;
output fetch_ic_even;
output fetch_ic_odd;
output fetch_TOQ;
output fetch_alt;
output fetch_SIQ;
output ncant_unload;
output hold_alt;
output fold_annul;
//output untaken_empty_ilock;
output sel_shift1;
output sel_shift2;
output sel_shift3;
output sel_fold1;
output sel_fold2;
output sel_even1;
output sel_odd1;
output hold_q1;
output sel_even2;
output sel_odd2;
output hold_q2;
output sel_even3;
output sel_odd3;
output hold_q3;
output hold_q4;
output hld_backup;
output take_icdata;
output sel_old_aa;
output hld_dir2;
output sel_last_gen;
// output sel_ll_gen;
// output sel_inc_last_gen;
output recirc2_default;
output sel_inc_ll_gen;
output sel_inc_dpc;
output sel_inc_alttag;
output sel_gpc;
output sel_recirc;
output sel_recirc_inc;
output sel_lgen_iva;
output sel_gpc_ic;
output sel_recirc_ic;
output sel_recirc_inc_ic;
output sadr_zero_ic;
output force_ifill;
output flush_ic_e;
output force_dva;
output sel_lgen_ica;
//output sadr_fold_aa;

output fwd_wpc;
output use_tpc;
output fwd_tpcm4;
input [31:22] toq_entry_bits;
input [31:22] nq1_entry_hi;
input [10:2] iexc_for_br;
input [10:2] niexc1_hi;
input [10:2] iexc_for_int_hi;
input fpc_low;
input nlta_low;
input ndpc_low;
input nalttag_low;
input ic_force_ifill_g, mm_istat_avail;
input i_dva_req;

output iu_event;		// special event opcode detected

output [4:0] nbrs1_decm;
output [7:0] brs3_d;
output [7:0] nr_rdp;
output [21:0] in_dec_lo22;
output d_imm_l;
output iu_sfs_sup;
output [1:0] iu_sfs_perr;
output iu_sfs_xerr;
output iu_sfs_mmiss;
output iu_sfs_iae;
output iu_sfs_sbe;
output iu_sfs_sto;
output iu_sfs_prtct;
output iu_sfs_priv;
output [1:0] iu_sfs_lvl;
output [1:0] w_op;
output w_op3_5;
output w_op3_3;
output w_op3_2;
output w_op3_0;
input [31:0] inst_for_int;
input [11:0] ndec_inst_traps;
input [2:0] ncwpm_l;


input ss_scan_mode;         // scan mode
input Mdecode_scan_in;
output Mdecode_scan_out;

// FORWARD DECLARATIONS

	wire sm = s;
	wire [5:1] alu_s2m_5_1 = alu_s2m_5_0[5:1];
	wire [4:0] alu_s2i_cnt = alu_s2m_5_0[4:0];
	wire bicc_taken;
	wire [5:0] help_ctr;
	wire e_load, e_hldd;
	wire ndet_divovf;
//	REGWIRE det_divovf;
	wire det_divovf;

	wire [2:0] d_hop;
	wire [5:0] d_hop2;
	wire [8:0] d_hop3;
	wire [10:0] d_opcode;
	wire [2:0] d_hhn;
	wire [2:0] e_hop;
	wire [5:0] e_hop2;
	wire [8:0] e_hop3;
	wire [10:0] e_opcode;
	wire e_help;
	wire [2:0] e_hhn;
	wire [2:0] w_hhn;
	wire [2:0] w_hop;
	wire [8:0] w_hop3;
	wire [10:0] w_opcode;

	wire alus1_b2_shift;
	wire sel_rs1_shiftin;

	wire e_jmprett;
//	wire jmp_ilock;

	wire sel_srl2_mult;
	wire w_trap;
	wire nERROR;
	wire null_fetch;
	wire fetch_;
	wire en_rfexc;
	wire fcc_ilock;
	wire d_brcall;
	wire d_jmprettmem;
	wire e_jmprettmem;
	wire hold;
	wire [2:0] next_d_hhn;
	wire hnop_into_ex;
	wire htrap_into_ex;
	wire valid_decode;
	wire ANNUL;
//	wire rdtpc;
	wire ifetchm_;		// early master latched version of ifetchm_
	wire e_call;		// execute cycle of a call instr.

	wire d_nop;
	wire interlock;		// repeat current decode for various reasons

	wire trap_cyc1;
	wire trap_cyc2;
	wire d_trap;		// 1st or 2nd cycle// used to be reg
	wire trapw_int;		// trap interrupt
	wire trapw_dae;		// Data Access Exception

	wire shift_passm;	// used as a pass control for shifter
	wire [3:0] int_req_lev; // interrupt request level
	wire [3:0] pint_req_lev; // same, but piped

	wire mispredicted;
	wire fold_annul;
	wire fold_annul2;
	wire fold_annul3;
	wire fold_annul4;
	wire fold_annul5;
	wire fold_annul6;
	wire fold_annul7;

	wire [4:0] d_rd, r_rd;

	wire [2:0] iu_inst_ft;
	wire [1:0] iu_inst_lvl;

// forward declarations necessitated by moving Mir to Mdecode

	wire [31:0] in_dec;
	wire [1:0] d_op = in_dec[31:30];
	wire d_anl = in_dec[29];
	wire [3:0] d_cond = in_dec[28:25];
	wire [5:0] d_op3 = in_dec[24:19];
	wire d_imm = in_dec[13];
	wire [5:4] d_asi = in_dec[10:9];
	wire [4:0] d_rs2 = in_dec[4:0];
	wire [21:0] in_dec_lo22 = in_dec[21:0];
	wire [1:0] e_op, w_op;
	wire [5:0] e_op3, w_op3;
	wire [4:0] d_rs1;
	wire [4:0] e_rd, w_rd;
	wire [7:0] w_rdp;
	wire [5:0] e_asim;

	wire [4:0] d_rd_basic = ({d_anl, d_cond});

Mpipec_im_id pipec_im_id (
        d_opcode,
        e_opcode,
        hold,
	imul_idiv_ilock,
        ss_clock,
        valid_decode,
	valid_decode_nilock,
        w_opcode,
// outs
        dhop3_idivbasic,
        dhop3_idivbasic_op,
        dhop3_imulbasic,
        dhop3_imulbasic_op,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv2_op,
        dopc_hidiv3_op,
        dopc_hidivcc3,
        dopc_himul0_op,
        dopc_himul1_op,
        dopc_himul2_op,
        dopc_himulcc2,
        ehop3_idivbasic,
        ehop3_imulbasic,
        eopc_hidiv1,
        eopc_hidiv3,
        eopc_himul0,
        hidiv_in_d,
        himul_in_d,
        sel_sll1_divalu_l,
        signed_div,
        signed_mult,
	wopc_himul1
	);


Mpipec_br_vald pipec_br_vald (
        TRAP,
        bicc_taken,
        d_anl,
        d_cond,
        d_hop2,
        d_nop,
        d_trap,
        del_resetm,
	e_help,
	fold_annul5,
        hold,
        interlock,
	interlock_vald,
	iacc_exc_mmumiss_d,
	mispredicted,
	pfcc,
        reset,
        ss_clock,
        trapd_iaer,
	untaken_empty_ilock,
// outs
        ANNUL,
	nANNUL,
        bcop_taken,
	fcc_taken,
        hnop_into_ex,
	clr_e_iexc_nop,
        valid_decode,
        valid_decode_nilock
	);

Mpipec_help_ilock pipec_help_ilock(
        ANNUL,
	ER_SDOUT,
        ERROR_nop,
        b1_eq_src1,
        b1_eq_src2,
        d_imm,
        d_opcode,
        d_rs1,
        d_rs2,
        d_trap,
        dhop3_idivbasic_op,
        dhop3_imulbasic_op,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv2_op,
        dopc_himul0_op,
        dopc_himul1_op,
	drd_eq_erd,
        e_hldd,
        e_load,
	e_no_write,
        e_hop,
        e_rdpsr_op,
        e_rdtbr_op,
        e_rdwim_op,
	e_rdy_op_forilock,
        ef,
	dfrd_eq_efrd,
	fold_annul6,
        hold,
	iacc_exc_mmumiss_d,
	mispredicted,
        ndet_divovf,
        pfccv,
	r_no_write,
        rd_ex_g0,
        reset,
        ss_clock,
	untaken_empty_ilock,
	sv_rest_fold_ilock,
        valid_decode,
        valid_decode_nilock,
	w_no_write,
// outs
        d_nop,
        fcc_ilock,
        gen_help,
	gen_help_op,
        help_ctr,
	imul_idiv_ilock,
        interlock,
	interlock_vald,
        iu_fetch_f,
        next_d_hhn
	);



	assign htrap_into_ex = d_trap;
//	wire iu_help_w = w_hhn[2];


Mir_control ir_control(
        TRAP,
        ss_clock,
        d_op,
        d_op3,
	d_rd_basic,
        hnop_into_ex,
        hold,
        htrap_into_ex,
        next_d_hhn,
        valid_decode,
	gen_help,
	interlock,
	valid_decode_nilock,
// synopsys translate_off
        w_op,
        w_op3,
// synopsys translate_on
	d_rd_hstd_sel,
	d_rd,
	word_store_d,
	half_store_d,
	byte_store_d,
        clear_rd0m,
	d_hhn,
	e_hhn,
        set_rd0m,
        w_hhn,
	hld_dirreg,
	hld_dirreg_rf
	);

	assign d_opcode = {d_hhn[2], d_op, d_op3, d_hhn[1:0]};
						// complete opcode
	wire d_help = d_opcode[10];		// help bit
	assign d_hop = d_opcode[10:8];	// h + op
	assign d_hop2 = d_opcode[10:5];	// h + op + op2
	assign d_hop3 = d_opcode[10:2];	// h + op + op3

	assign e_opcode	= {e_hhn[2], e_op, e_op3, e_hhn[1:0]};
						// complete opcode
	assign e_help = e_opcode[10];		// help bit
	assign e_hop = e_opcode[10:8];	// h + op
	assign e_hop2 = e_opcode[10:5];	// h + op + op2
	assign e_hop3 = e_opcode[10:2];	// h + op + op3

	assign w_opcode = {w_hhn[2], w_op, w_op3, w_hhn[1:0]};
						// complete opcode
	assign w_hop = w_opcode[10:8];	// h + op
	assign w_hop3 = w_opcode[10:2];	// h + op + op3
	wire w_op3_5 = w_op3[5];
	wire w_op3_3 = w_op3[3];
	wire w_op3_2 = w_op3[2];
	wire w_op3_0 = w_op3[0];

	wire w_hhn_2 = w_hhn[2];

	wire [7:0] d_rs1pm;
	wire [7:0] d_rs2pm;

Mdata_rf data_rf (
        ANNUL,
        TRAP,
	alus2_datam,
	cwpm_,
        d_nop,
        d_opcode,
        d_rs1,
        d_rs2,
        d_trap,
        del_resetm,
        dhop3_idivbasic_op,
        dhop3_imulbasic_op,
	fold_annul6,
	mispredicted,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv2_op,
        dopc_himul0_op,
        dopc_himul1_op,
        dopc_himul2_op,
        hold,
        interlock,
	iacc_exc_mmumiss_d,
	reset,
	rs2_clear,
        ss_scan_mode,
        ss_clock,
        trap_cyc2,
        w_opcode,
//outs
        alu_s2_reg_hold,
        d_rs1pm,
        d_rs2pm,
        e_no_write,
        r_no_write,
        result_r0,
        rf_we_w,
	rs2_passit,
        w_no_write,
        wr_lddatam_l
	);

Mdata_byp1_1 data_byp1_1(
	d_hop3,
        d_imm,
        d_rs1,
        d_rs2,
	d_rd,
        e_call,
        e_no_write,
        e_rd,
	hold,
	ss_clock,
	valid_decode,
// outs
        alus1_b1m,
        alus1_set,
        alus1_setm,
        alus2_b1m,
        b1_eq_src1,
        b1_eq_src2,
	byp_res3,
	drd_eq_erd,
	dfrd_eq_efrd,
	nbyp_res3,
        rd_ex_g0
	);

Mdata_byp1_2 data_byp1_2(
        alus1_b1m,
        alus1_set,
        alus2_b1m,
	nbyp_res3,
	cwpm_,
        d_imm,
        d_rs1pm,
        d_rs2pm,
	d_rd,
        det_divovf,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv3_op,
        help_ctr,
        signed_div,
        w_hop3[8:5],
        w_no_write,
        w_rdp,
// outs
        alus1_b2m,
        alus2_b2m,
        b2_eq_src1,
        b2_eq_src2,
	byp_wr3,
	byp_rf3,
        rd_wr_g0,
// misc
	hold,
	ss_clock
	);

Md_r_reg_cmp d_r_reg_cmp (
	src1_match,
	src2_match,
	r_rd,
	ecwpm_,
	cwpm_,
	w_rd,
	d_rs1,
	d_rs2,
	ss_clock,
	hold
	);


Mdata_byp2 data_byp2 (
        TRAP,
        alus1_b1m,
        alus1_set,
        alus2_b1m,
        b2_eq_src1,
        b2_eq_src2,
        d_imm,
        d_opcode,
        det_divovf,
        dopc_hidiv3_op,
        dopc_himul0_op,
        dopc_himul1_op,
        dopc_himul2_op,
        e_hop3,
	fold_annul5,
        help_ctr,
        hold,
        r_no_write,
        r_rd,
        rd_wr_g0,
	src1_match,
	src2_match,
        ss_clock,
        valid_decode,
// outs
        alus1_b3m,
        alus1_datam,
        alus2_b3m,
        alus2_datam,
        e_hldd,
        e_ldd,
        e_load,
        write_r15
	);



//	wire write_r17 = TRAP;
	wire write_r18 = trap_cyc1;

Malu_control alu_control(
        TRAP,
	alu_cc_next[0],
        alu_cc_next[2],
        alu_s1m_0,
	alu_s1s_lsb2,
	alu_s2m_5_0[0],
        alu_s2m_5_1,
        alus1_b1m,
        alus1_b2m,
	alus1_datam,
        alus1_set,
        alus2_b1m,
        alus2_b2m,
	alus2_datam,
	ccm[0],
        ss_clock,
        d_imm,
        d_opcode,
	d_rs2[3:0],
        dhop3_idivbasic_op,
        dhop3_imulbasic_op,
        dopc_hidiv0_op,
        dopc_hidiv1_op,
        dopc_hidiv2_op,
        dopc_hidiv3_op,
        dopc_himul0_op,
        dopc_himul1_op,
	e_hop3,
        ehop3_imulbasic,
        eopc_hidiv3,
        eopc_himul0,
	nfold_annul,
        help_ctr,
        hidiv_in_d,
        high_2_1,
	idiv_shiftin_low,
        himul_in_d,
        hold,
        nERROR,
	rd_wr_g0,
	trap_cyc1,
        reset,
        resultMSB,
	result_lo[0],
	dsign_bit2,
        rf2_imm_data_msb,
	dsign_bit1,
	setcc,
        signed_div,
        signed_mult,
	msign_bit,
	src1m_msb,
	src2m_lo,
	ss_scan_mode,
        valid_decode,
	valid_decode_nilock,
        w_hop3,
        wopc_himul1,
        ym,
        alu_ADD,
        alu_AND,
        alu_XNOR,
        alu_sub,
        tagged_ovf,
        alus1_b2_shift,
        alus1_rfm_b3m,
	a2top_default,
        carry_in,
	pass_hi_rs1,
        det_divovf,
        ne_mulsm,
	next_e_not_negmul,
        hld_y,
        hold_Wreg,
//      hold_rs2,
        n_ymsb,
        ndet_divovf,
        rs1_clear,
        rs1_double,
        nrs1_negate,
	nrs1_negate_l,
        rs1_pass,
	spc_mux_default,
        rs2_clear,
        rs_from_alu,
        rs_from_else,
	rs_from_sh,
        sel_rs1_shiftin,
        sel_srl2_mult,
        nsel_w_mult,
	nsel_w_mult_l_b,
	nsel_w_mult_l_not_b,
        wr_y,