| (dopc_hidiv0_op & help_ctr[1]==1'b1)
		}
		;

//                d_opcode==HIFLUSH0
//              | d_opcode==HSTA0

/*
 * was part of bit 0
		  d_opcode==HSTDF0
		| d_opcode==HSTD0 | d_opcode==HSTDA0
		| d_opcode==HSTDFQ0
 */

/*
 * See after Mpipe_control instanciation for iu_help_w
// Generate a signal iu_help_w whiich says there is a help in W

	wire iu_help_w = w_hhn2;
 *
 */


// LOAD INTERLOCK LOGIC

	wire d_nod_st_op = 
		  d_hop3==`STB | d_hop3==`STBA
		| d_hop3==`STH | d_hop3==`STHA
		| d_hop3==`ST | d_hop3==`STA
		;

	wire d_all_ist_op =
		  d_nod_st_op
		| d_hop3==`STD | d_hop3==`STDA
		;

	// these ilock terms don't really need to include
	// the dependant store terms.  however, for timing
	// from the D$, ldalgn, to RF mux, to d$if mux to d$
	// is too long, so interlock.
	wire load_ilock = e_load & ~rd_ex_g0 & ~(d_opcode==`HLDA) &
			( 	  b1_eq_src1
				| b1_eq_src2 & ~d_imm
			   	| drd_eq_erd & d_all_ist_op
			)
			;
	
	wire ldd_ilock =
		e_hldd &
			(
			  b1_eq_src1
			| b1_eq_src2 & ~d_imm
			| drd_eq_erd & d_nod_st_op
			);

/*
 * Modify for SUNERGY
 *
	// Co-processor cc's invalid interlock
	// when FPU is present and enabled
	// a BFCC in decode
	// interlocks until the pfccv (pcccv) line becomes active
	// when FPU is present and enabled and FHOLD asserted
	// a FPOP or FPCMP in decode
	// interlocks until the FHOLD line becomes inactive. 

	// NOTE - FPU interface has changed so that FHOLD is
	// no longer qualified in the fpu.  we qualify it here
	// in the iu with valid_decode_fpu. -

	// NOTE 2 - we no longer have to qualify it with
	// valid_decode_fpu.
 *
 */

	assign fcc_ilock = 
		  d_hop2==`BFCC
		& ~pfccv & ef
		;


//	wire fhold_ilock;
//	assign fhold_ilock =
//		  FHOLD
//		& ef
//		;

/*
 * New FP interlock cases - in the event a ldf/lddf is followed
 * by a dependant stf/stdf, we interlock.  the interlock determination
 * is done across only the high 4 bits of the rd fields so
 * we may be a bit pessimisstic.  in addition, there is a dependancy
 * on ldfsr/stdfq followed by any FPops.  these dependancies are
 * set by the FPU.
 */

	wire d_stf = d_hop3==`STF | d_hop3==`STDF;
	wire d_fp_op_mem_cmp =
		  d_hop3 == `FPOP
		| d_hop3 == `FPCMP
		| d_hop3[8:4]==`MEMF
		;

	wire d_ldf = valid_decode & (d_hop3==`LDF | d_hop3==`LDDF);
	wire e_ldf;
	Mflipflop_1 e_ldf_reg_1(e_ldf,d_ldf,ss_clock,hold) ;

	wire d_ldfsr_stdfq = valid_decode & (
		  d_hop3==`LDFSR | d_hop3==`STDFQ);
	wire e_ldfsr_stdfq;
	Mflipflop_1 e_ldfsr_stdfq_reg_1(e_ldfsr_stdfq,d_ldfsr_stdfq,ss_clock,hold) ;

	wire fp_ldst_ilock =
		  e_ldf & dfrd_eq_efrd & d_stf
		| e_ldfsr_stdfq & d_fp_op_mem_cmp
		;

/*
 * New interlock case for SUNERGY.  On calls, if the delay slot
 * of the call uses r15 (%o7), interlock for one cycle.  This was
 * not necessary for Suntan since Suntan was able to use bypass 1
 * because of the Master/Slave architecture.  Puma is register
 * based so it cannot use bypass 1.
 */

	wire e_hopcall = e_hop==`CALL;
	wire call_use_ilock =
		  e_hopcall
		& ((d_rs1 == 5'd15) | (d_rs2 == 5'd15));

/*
 * Another new interlock case for SUNERGY.  Puma must interlock
 * on a branch followed by a jump. 
 * Note: RETT is preceeded by JMP so it does not have this ilock.
 */

//	wire d_jmp_ilock = d_hop3==JMP & valid_decode;
//	REGWIRE jmp_ilock;
//	REG(jmp_ilock_reg,1,jmp_ilock,d_jmp_ilock,ss_clock,hold)

/*
 * Another icky interlock case for SUNERGY.  If a read special
 * register instruction (eg: rd y, rd wim) destination register
 * is used as a source by the next instr, you cannot use
 * bypass 1.  You must use bypass 2, so interlock.
 */

	wire rd_spec_ilock =
		((e_rdpsr_op | e_rdwim_op
		| e_rdy_op_forilock | e_rdtbr_op)
		& (b1_eq_src1 | (b1_eq_src2 & ~d_imm)));


/*
 * The REAL new interlock case for IMUL/IDIV - this one causes
 * two interlocks to occur on EVERY imul and idiv.  This is
 * basically for the same reason as above: to "correct" the
 * src1 and src2 data.  Note that only 2 are required now, rather
 * than the above max of 3.  this is because bypass3 data comes
 * out on the same pins as the RF out.
 *
 */

	wire imul_idiv_ilock =
		  (dhop3_imulbasic_op | dhop3_idivbasic_op)
		& (~e_no_write | ~w_no_write | ~r_no_write)
		;

/*
 * new interlock case - added for the benefit of the MMU and cache.
 * if the MMU detects a i_acc_exc, we should disable fetching
 * and interlock until the bad instruction hits W.

	REGWIRE mm_iacc_exc_ilock1;
	REG(mm_iacc_exc_ilock_reg1,1,mm_iacc_exc_ilock1, 		iacc_exc_mmumiss_d, ss_clock,hold)

	wire nmm_iacc_exc_ilock2 = mm_iacc_exc_ilock1 & ~fold_annul;

	REGWIRE mm_iacc_exc_ilock2;
	REG(mm_iacc_exc_ilock_reg2,1,mm_iacc_exc_ilock2, 		nmm_iacc_exc_ilock2, ss_clock,hold)

	wire mm_iacc_exc_ilock = nmm_iacc_exc_ilock2 | mm_iacc_exc_ilock2;
 */

/*
 * ilock case for T+ - if an untaken branch is in E and the queue
 * is empty, interlock the pipe.  currently, the determination is
 * done in Mpc_cntl
	wire untaken_empty_ilock =
		Msystem.ssparc.iu.iuchip.pc_cntl.untaken_empty_ilock;
 */

/*
 * INTERLOCK!!!
 */
	wire d_help = d_hop3[8];
	// this term is to kill interlock if the targ of a folded
	// branch is not to be executed (ie: it was mispredicted).
	// kill interlock if inst is in D.
	wire kill_nohelp_d_il = ~d_help & mispredicted;

	wire lotsa_ilock =
		  fcc_ilock | fp_ldst_ilock
		| call_use_ilock
		| rd_spec_ilock | imul_idiv_ilock
		| sv_rest_fold_ilock
		;
// don't need this one anymore
//		| mm_iacc_exc_ilock

	assign interlock =
		~reset & ~d_trap & ~d_nop & ~iacc_exc_mmumiss_d &
		 (untaken_empty_ilock |
		   (~kill_nohelp_d_il &
			 (load_ilock | ldd_ilock |
			 	(~ANNUL & lotsa_ilock)
			 )
		   )
		 );
//			 | jmp_ilock

// this version of interlock is used only for valid_decode

	wire interlock_vald =
		~reset & (
			  untaken_empty_ilock
			| load_ilock | ldd_ilock
			| lotsa_ilock
			);


/*
 * not needed
	wire no_imid_ilock =
		  load_ilock | ldd_ilock
		| call_use_ilock
		| rd_spec_ilock
//		| jmp_ilock
		| mm_iacc_exc_ilock
		| fcc_ilock
		| fhold_ilock
		| untaken_empty_ilock
		;
 */

/*
 * To prevent a logic loop to the FPC via valid_decode, the FPC
 * needs a version of valid_decode that does not include
 * the fhold_ilock term.  Note that the fcc_ilock is OK.

	wire interlock_fpu =
		 untaken_empty_ilock |
		 (~kill_nohelp_d_il &
			(load_ilock | ldd_ilock |
			(~ANNUL &
				 ( fcc_ilock
				 | fp_ldst_ilock
				 | fhold_ilock
				 | rd_spec_ilock
				 | call_use_ilock
				 )
			))
		 );
//			 | jmp_ilock
 */


// D_NOP REGISTER

	// when necessary, the instruction buffers will dispatch
	// a nop by loading the following register

	wire next_d_nop;
	wire d_nop_reg_sdin;
	Mflipflop_1 d_nop_reg_1(d_nop, next_d_nop, ss_clock, hold) ;

// DETERMINE NEXT_D_NOP (issue nops due to instruction Starvation)

	assign next_d_nop = reset | ERROR_nop;


endmodule



module Mtrap_control(
        FEXC,
	nERROR,
        ss_clock,
	fold_annul,
        hold,
        pint_req_lev,
        reset,
        result,
        trapd_cpd,
        trapd_fpd,
        trapd_iae,
        trapd_iaer,
	trapd_immum,
	trapd_iwp,
        trapd_ilgl,
        trape_algn,
        trape_ilgl,
        trape_priv,
        trape_ticc,
        trape_wo,
        trape_wu,
	mm_dacc_exc_w,
	mm_dacc_err_w,
	mm_dacc_mmu_miss_w,
	mm_dacc_wp_w,
//      trapw_dae,
//	trapw_daer,
//	trapw_dmmum,
        trapw_fpe,
        trapw_int,
        trapw_tag,
	trape_divz,
        FXACK,
        IU_in_trap,
	IU_in_trap4fpu,
	IU_in_trap4dc,
        TRAP,
        d_trap,
        fp_exc,
        trap_cyc1,
        trap_cyc2,
        trapcode,
        w_trap,
	wo_trap_w,
	wu_trap_w
	);

input FEXC;
input nERROR;
input ss_clock;
input fold_annul;
input hold;
input [3:0] pint_req_lev;
input reset;
input [6:0] result;
input trapd_cpd;
input trapd_fpd;
input trapd_iae;
input trapd_iaer;
input trapd_immum;
input trapd_iwp;
input trapd_ilgl;
input trape_algn;
input trape_ilgl;
input trape_priv;
input trape_ticc;
input trape_wo;
input trape_wu;
input mm_dacc_exc_w;
input mm_dacc_err_w;
input mm_dacc_mmu_miss_w;
input mm_dacc_wp_w;
//input trapw_dae;
//input trapw_daer;
//input trapw_dmmum;
input trapw_fpe;
input trapw_int;
input trapw_tag;
input trape_divz;
output FXACK;
output IU_in_trap;
output IU_in_trap4fpu;
output IU_in_trap4dc;
output TRAP;
output d_trap;
output fp_exc;
output trap_cyc1;
output trap_cyc2;
output [7:0] trapcode;
output w_trap;
// output iu_inst_trap_w;
output wo_trap_w;
output wu_trap_w;

//FORWAD DEC.
	wire trap_cyc1, trap_cyc2, d_trap;
	wire trapw_tag;


//---------------------------------------------------------------------------
// TRAP CONTROL (ALGORITHMS)

// FEXC state machine

	wire fp_exc = FEXC & ~reset;

// GENERATE TRAP

	// COMBINE DECODE TRAPS

	// remove trapd_iwp since MMU changed the way it wants
	// to do iwp traps
	wire dec_trap =
		  trapd_iae | trapd_iaer | trapd_ilgl | trapd_fpd | trapd_cpd
		| trapd_immum // | trapd_iwp
		;

	wire dex_trap;
	Mflipflop_1 d_traps_ff_1(dex_trap, dec_trap, 		ss_clock, hold) ;

	// COMBINE EXECUTE TRAPS

	wire ex_trap =
		  (dex_trap & ~fold_annul)
		| trape_ilgl | trape_priv | trape_wo
		| trape_wu | trape_algn | trape_ticc
		| trape_divz
		;

	wire exw_trap;
	Mflipflop_1 e_traps_ff_1(exw_trap, ex_trap, 		ss_clock, hold) ;

	// COMBINE WRITE TRAPS

	// also, force TRAP=0 on reset and in 2 cycles following a TRAP

	wire trapw_dae = mm_dacc_exc_w;
	wire trapw_daer = mm_dacc_err_w;
	wire trapw_dmmum = mm_dacc_mmu_miss_w;
	wire trapw_dwp = mm_dacc_wp_w;

	assign w_trap =
		  (exw_trap | trapw_dae | trapw_daer | trapw_fpe
		| trapw_tag | trapw_int | trapw_dmmum | trapw_dwp);
/*
 * Removed for SUNERGY Puma - no RF parity errors
		| trapw_rfe);
 *
 */

// TRAP STATE MACHINE

	wire TRAP = w_trap & ~reset & ~d_trap;
		/* & ~ss_scan_mode */

	wire ntrap_cyc1 = TRAP;

	// OLD wire ntrap_cyc1 = TRAP | latchedFEXC | latchedCEXC;

	Mflipflop_1 trap_1_ff_1(trap_cyc1, ntrap_cyc1, 		ss_clock, hold) ;

	Mflipflop_1 trap_2_ff_1(trap_cyc2, trap_cyc1, 		ss_clock, hold) ;

	wire nd_trap = ntrap_cyc1 | trap_cyc1;

	Mflipflop_1 d_trap_mas_1( d_trap, nd_trap, ss_clock, hold) ;

/*
 * not for warthog
// Detect R cycle traps.  need to handle PC's differently for
// these.  beware!!!

	wire r_trap =
		  TRAP
		& (trapr_dae | trapr_daer | trapr_dmmum)
		;

	wire rtrap_hldpc = r_trap | hold;

 */

// Let FPC know that we have detected TRAP, or in trap cyc1 or 2.

	wire IU_in_trap = TRAP | trap_cyc1 | trap_cyc2;
	wire IU_in_trap4fpu = IU_in_trap;
	wire IU_in_trap4dc = IU_in_trap;

//-------------------------------------------------------------------------
// ENCODE AND PRIORITIZE TRAPS

// PIPELINE TRAP SIGNALS TO W CYCLE

	// high bit of input to de_trap_reg tied off since
	// now all WP traps happen through the dwp trap signal.
	// mmu changed their minds on how to do this.  this
	// register is kept to be consistent with the 
	// gate level netlist.
	wire [6:0] de_traps_almost;
	wire [6:0] de_trap_reg_mux_out;
	assign de_trap_reg_mux_out =
		({1'b0, trapd_immum, trapd_iaer, trapd_cpd, 			trapd_fpd,trapd_ilgl, trapd_iae});
	Mflipflop_7 de_trap_reg_7( de_traps_almost, de_trap_reg_mux_out, ss_clock, hold) ;
	wire [6:0] de_traps = de_traps_almost & {7{~fold_annul}};

	wire [6:0] dw_traps;
	Mflipflop_7 dw_trap_reg_7( dw_traps, de_traps, ss_clock, hold) ;


	wire iae = dw_traps[0];
	wire ilgl = dw_traps[1];
	wire fpd = dw_traps[2];
	wire cpd = dw_traps[3];
	wire iaer = dw_traps[4];
	wire immum = dw_traps[5];
	wire iwp_det = dw_traps[6];

	wire [6:0] ew_traps;
	wire [6:0] ew_trap_mux_out;
	assign ew_trap_mux_out =
		({trape_divz, trape_ticc, trape_algn, trape_wu,
			trape_wo, trape_priv, trape_ilgl});
	Mflipflop_7 ew_trap_reg_7( ew_traps, ew_trap_mux_out, ss_clock, hold) ;

	
	wire ilgl2 = ew_traps[0];
	wire priv = ew_traps[1];
	wire wo = ew_traps[2];
	wire wu = ew_traps[3];
	wire algn = ew_traps[4];
	wire ticc = ew_traps[5];
	wire divz = ew_traps[6];

	// added to fix IOMMU bug
	wire wo_trap_w = ew_traps[2];
	wire wu_trap_w = ew_traps[3];

// RENAME W CYCLE TRAPS FOR CONVENIENCE

	wire dae = trapw_dae;
	wire daer = trapw_daer;
	wire dmmum = trapw_dmmum;
	wire dwp_det = trapw_dwp;
	wire wfpe = trapw_fpe;


/*
 * No R cycle FPexc detecs in Puma/Martini
	wire rfpe = trapr_fpe;
 *
 */

/*
 * No CP in SUNERGY Puma
	wire wcpe = trapw_cpe;
	wire rcpe = trapr_cpe;
 *
 */

	wire tag = trapw_tag;

	wire int = trapw_int;

/*
 * No RF parity errors in SUNERGY Puma
	wire rfe = trapw_rfe;
 *
 */

// PRIORITY ENCODE TT VALUE and indicate to MMU if trap is inst related

//	wire iu_inst_trap_w = immum | iaer | iae;

	wire [7:0] trapcode;

	Mtrapcode trapcode_mod (
	wfpe, dae, daer, dmmum, immum, iwp_det, dwp_det,
	iae, ilgl, divz, ilgl2, priv, fpd,
	iaer, cpd, wo, wu, algn, tag, ticc, int,
	hold, pint_req_lev, result, nERROR,
	trapcode, FXACK);

endmodule



module Mtrap_detection(
        ANNUL,
        TRAP,
        ccm_V,
        alu_out_lsb5,
        bicc_taken,
	alu_cc_zero,
        ss_clock,
        cwpm_,
        d_hop3,
        d_imm,
	ehop3_idivbasic,
	mm_iacc_exc_d,
//	mm_iacc_err_par,
	mm_iacc_err_tlb_d,
	mm_iacc_wp_exc_d,
	parity_error_d,
	mm_iacc_mmu_miss_d,
        d_nop,
        d_trap,
        e_hop3,
        ef,
        et,
	fold_annul,
        fp_exc,
        hold,
	mispredicted,
//      mm_dacc_exc_w,
//	mm_dacc_err_w,
//	mm_dacc_mmu_miss_w,
        int_req_lev,
        interlock,
        pil,
        reset,
        s,
	trapcode,
        trap_cyc1,
        valid_decode,
	w_wrpsr,
        wimm,
        ERROR_nop,
        ER_SDOUT,
	error_mode,
	iu_event,
        nERROR,
        trapd_cpd,
        trapd_fpd,
        trapd_iae,
        trapd_iaer,
	trapd_immum,
	trapd_iwp,
        trapd_ilgl,
        trape_algn,
        trape_ilgl,
        trape_priv,
        trape_ticc,
        trape_wo,
        trape_wu,
//      trapw_dae,
//	trapw_daer,
//	trapw_dmmum,
        trapw_fpe,
        trapw_int,
        trapw_tag,
	trape_divz
	);

input ANNUL;
input TRAP;
input ccm_V;
input [4:0] alu_out_lsb5;
input bicc_taken;
input alu_cc_zero;
input ss_clock;
input [2:0] cwpm_;
input [8:0] d_hop3;
input d_imm;
input ehop3_idivbasic;
input mm_iacc_exc_d;
//input mm_iacc_err_par;
input mm_iacc_err_tlb_d;
input mm_iacc_wp_exc_d;
input parity_error_d;
input mm_iacc_mmu_miss_d;
input d_nop;
input d_trap;
input [8:0] e_hop3;
input ef;
input et;
input fold_annul;
input fp_exc;
input hold;
input mispredicted;
//input mm_dacc_exc_w;
//input mm_dacc_err_w;
//input mm_dacc_mmu_miss_w;
input [3:0] int_req_lev;
input interlock;
input [3:0] pil;
input reset;
input s;
input [7:0] trapcode;
input trap_cyc1;
input valid_decode;
//input [2:0] w_hop;
input w_wrpsr;
input [7:0] wimm;
output ERROR_nop;
output ER_SDOUT;
output error_mode;
output iu_event;
output nERROR;
output trapd_cpd;
output trapd_fpd;
output trapd_iae;
output trapd_iaer;
output trapd_immum;
output trapd_iwp;
output trapd_ilgl;
output trape_algn;
output trape_ilgl;
output trape_priv;
output trape_ticc;
output trape_wo;
output trape_wu;
//output trapw_dae;
//output trapw_daer;
//output trapw_dmmum;
output trapw_fpe;
output trapw_int;
output trapw_tag;
output trape_divz;


//FORWARD DEC.
wire r_data_acc;

	wire d_help = d_hop3[8];
	wire [2:0] d_hop = d_hop3[8:6];
	wire [5:0] d_hop2 = d_hop3[8:3];

	wire [5:0] e_hop2 = e_hop3[8:3];
	wire [2:0] e_hop = e_hop3[8:6];
	wire e_help = e_hop3[8];


        // ERROR STATE
           
        // error state is entered when a trap occurs and ET=0.
        // It can only be cleared by an external reset.

        // This flip-flop also terminates the scan chain.

        wire ER_SDOUT;

        assign nERROR =
                ~reset & (ER_SDOUT | (TRAP & ~et));

	Mflipflop_1 ER_SDOUT_reg_1( ER_SDOUT, nERROR,                 ss_clock, 1'b0) ;		// used to be held by hold

	wire nnerror_mode;
	Mflipflop_1 nnerror_mode_reg_1(nnerror_mode,ER_SDOUT,ss_clock,hold) ;

	wire nerror_mode;
	Mflipflop_1 nerror_mode_reg_1(nerror_mode,nnerror_mode,ss_clock,hold) ;

	wire error_mode;
	Mflipflop_1 error_mode_reg_1(error_mode,nerror_mode,ss_clock,hold) ;


        // must delay forcing NOP into the pipe until trap sequence
        // is completed

        wire ERROR_nop = ER_SDOUT & ~trap_cyc1;
 


// TRAP DETECTION

// detect INSTRUCTION ACCESS EXCEPTION in decode

	// Note that mm_iacc_exc_d (d_mexc) MUST be qualified with ~d_nop.

	wire trapd_iae = mm_iacc_exc_d & ~d_nop
		& ~interlock & ~ANNUL & ~d_trap
		& ~mispredicted;

// detect INSTRUCTION ACCESS MMU MISS EXCEPTION in decode

	wire trapd_immum = mm_iacc_mmu_miss_d & ~d_nop
		& ~interlock & ~ANNUL & ~d_trap
		& ~mispredicted;

// detect INSTRUCTION ACCESS WATCHPOINT TRAP in decode

	// this doesn't drive anything anymore, but here for
	// consistency.  MMU changed the way they want to do
	// iwp traps
	wire trapd_iwp = mm_iacc_wp_exc_d & ~d_nop
		& ~interlock & ~ANNUL & ~d_trap
		& ~mispredicted;


// detect INSTRUCTION ACCESS ERROR in decode

	wire trapd_iaer = (parity_error_d | mm_iacc_err_tlb_d)  & ~d_nop
		& ~interlock & ~ANNUL & ~d_trap
		& ~mispredicted;



// detect ILLEGAL INSTRUCTION in decode
// (there is also Write stage detection logic for WRPSR and illegal CWP value)

	wire ilgl_opcode = ~(
		  d_help

		| d_hop==`CALL

		| d_hop2==`SETHI | d_hop2==`BICC | d_hop2==`BFCC | d_hop2==`BCCC

		| d_hop3==`LDSB | d_hop3==`LDSBA | d_hop3==`LDUB | d_hop3==`LDUBA
		| d_hop3==`LDSH | d_hop3==`LDSHA | d_hop3==`LDUH | d_hop3==`LDUHA
		| d_hop3==`LD | d_hop3==`LDA
		| d_hop3==`LDD | d_hop3==`LDDA

		| d_hop3==`SWAP | d_hop3==`SWAPA
		| d_hop3==`LDSTB | d_hop3==`LDSTBA

		| d_hop3==`STB | d_hop3==`STBA | d_hop3==`STH | d_hop3==`STHA
		| d_hop3==`ST | d_hop3==`STA
		| d_hop3==`STD | d_hop3==`STDA

		| d_hop3==`LDF
		| d_hop3==`LDDF
		| d_hop3==`LDFSR

		| d_hop3==`STF
		| d_hop3==`STDF
		| d_hop3==`STFSR
		| d_hop3==`STDFQ

		| d_hop3==`LDC
		| d_hop3==`LDDC
		| d_hop3==`LDCSR

		| d_hop3==`STC
		| d_hop3==`STDC
		| d_hop3==`STCSR
		| d_hop3==`STDCQ

		| d_hop3==`ADD | d_hop3==`ADDCC | d_hop3==`ADDX | d_hop3==`ADDXCC
		| d_hop3==`TADDCC | d_hop3==`TADDCCTV
		| d_hop3==`SUB | d_hop3==`SUBCC | d_hop3==`SUBX | d_hop3==`SUBXCC
		| d_hop3==`TSUBCC | d_hop3==`TSUBCCTV
		| d_hop3==`MULSCC

		| d_hop3==`UMUL | d_hop3==`UMULCC
		| d_hop3==`SMUL | d_hop3==`SMULCC

		| d_hop3==`UDIV | d_hop3==`UDIVCC
		| d_hop3==`SDIV | d_hop3==`SDIVCC

		| d_hop3==`AND | d_hop3==`ANDCC | d_hop3==`ANDN | d_hop3==`ANDNCC
		| d_hop3==`OR | d_hop3==`ORCC | d_hop3==`ORN | d_hop3==`ORNCC
		| d_hop3==`XOR | d_hop3==`XORCC | d_hop3==`XNOR | d_hop3==`XNORCC

		| d_hop3==`SLL | d_hop3==`SRL | d_hop3==`SRA

		| d_hop3==`SAVE | d_hop3==`RESTORE

		| d_hop3==`JMP

		| d_hop3==`TICC

		| d_hop3==`RDTBR | d_hop3==`RDWIM | d_hop3==`RDPSR | d_hop3==`RDY
		| d_hop3==`WRTBR | d_hop3==`WRWIM | d_hop3==`WRPSR | d_hop3==`WRY

		| d_hop3==`FPOP | d_hop3==`FPCMP
		| d_hop3==`CPOP | d_hop3==`CPCMP

		| d_hop3==`RETT
		| d_hop3==`IFLUSH

		)
		;

	wire trapd_ilgl_op =
		  (d_hop3==`RETT & et)		// RETT with traps enabled
		| (d_hop3[8:4]==`MEMA & d_imm)	// ASI load/store with i=1
		;

	wire trapd_ilgl = valid_decode & (ilgl_opcode | trapd_ilgl_op)
		& ~mispredicted;


// detect FLOATING-POINT DISABLED in decode

	wire trapd_fpd_op =
		  (d_hop2==`BFCC)
		| (d_hop3[8:4]==`MEMF)
		| (d_hop3==`FPOP | d_hop3==`FPCMP)
		;
	wire trapd_fpd = valid_decode & ~ef & trapd_fpd_op
		& ~mispredicted;


// detect COPROCESSOR DISABLED in decode
	wire trapd_cpd_op =
		  (d_hop2==`BCCC)
		| (d_hop3[8:4]==`MEMC)
		| (d_hop3==`CPOP | d_hop3==`CPCMP)
		;
	wire trapd_cpd = valid_decode & trapd_cpd_op
		& ~mispredicted;


/*
 * New stuff - this is used to detect IU 'events.'  event
 * information is passed to the clock controller and others
 * for weird control stuff.  i don't know what it all does
 * exactly, but i do know if i detect this particular
 * opcode (i picked it, so i guess it's my responsibity)
 * i need to tell everyone.  BTW, it's only supposed to
 * go on if a register accessible only by scan is outputing
 * a 1.
 *
 * In addition to detecting the plain iu_event, there is
 * also a need for detecting the iu_error condition.  again
 * we use a scan only accessible register to enable this
 * event.
 */

	wire det_iu_event_op = e_hop3==`EVENT;

	wire det_iu_event_e =
		  det_iu_event_op
		& ~TRAP & ~reset
		& ~fold_annul;

	wire iu_event_w;
	Mflipflop_1 iu_event_w_reg_1(iu_event_w,det_iu_event_e,ss_clock,hold) ;

//     this reg is accessible only by scan
	wire enable_event;
	wire nenable_event = enable_event & ~reset;
	Mflipflop_1 event_reg_1(enable_event,nenable_event,ss_clock,1'b0) ;

	wire iuer_enable;
	wire niuer_enable = iuer_enable & ~reset;
	Mflipflop_1 iuer_enable_reg_1(iuer_enable,niuer_enable,ss_clock,1'b0) ;

	wire pER_SDOUT;
	Mflipflop_1 piu_error_reg_1(pER_SDOUT,ER_SDOUT,ss_clock,1'b0) ;

// change the below to remove the iuer_enable,  This bit is no longer
// accessable via the jtag controller (only internal scan).  This
// function will be done by a single flop in rl_clk_stop which is connected
// to the jtag scan chain.
//	wire iuer_event = ER_SDOUT & iuer_enable & ~pER_SDOUT;
	wire iuer_event = ER_SDOUT & ~pER_SDOUT;

// change the below to remove the iuer_enable,  This bit is no longer
// accessable via the jtag controller (only internal scan).  This
// function will be done by a single flop in rl_clk_stop which is connected
// to the jtag scan chain.
//	wire niu_event = iu_event_w & enable_event
	wire niu_event = iu_event_w 
			 & TRAP & (trapcode == 8'h2) & ~hold
		| iuer_event;

	wire iu_event;
	Mflipflop_1 iu_event_reg_1(iu_event,niu_event,ss_clock,1'b0) ;


// detect ILLEGAL INSTRUCTION in execute
// (the only case here is WRPSR with illegal CWP value)

/*
ifndef EXPAND
	wire ilgl_cwp = alu_out_lsb5 > 6;

else
*/

/*
 * for tsunami's 7 register windows
	wire ilgl_cwp = alu_out_lsb5[4] |
			alu_out_lsb5[3] |
			alu_out_lsb5[2] &alu_out_lsb5[1] & alu_out_lsb5[0];
 */

	wire ilgl_cwp = alu_out_lsb5[4] | alu_out_lsb5[3];

//endif



	wire e_wrpsr = e_hop3==`WRPSR;

	wire trape_ilgl = e_wrpsr & ilgl_cwp
		& ~fold_annul;



// detect PRIVILEGED INSTRUCTION in execute

	wire trape_priv_op =
		  e_hop3[8:4]==`MEMA
		| e_hop3==`RDTBR | e_hop3==`RDWIM | e_hop3==`RDPSR
		| e_hop3==`WRTBR | e_hop3==`WRWIM | e_hop3==`WRPSR
		| e_hop3==`STDFQ | e_hop3==`STDCQ
		| e_hop3==`RETT
		;

	wire trape_priv =  ~s & trape_priv_op
		& ~fold_annul;



// detect WINDOW OVERFLOW and WINDOW UNDERFLOW in Execute

	wire [2:0] real_cwp = ~cwpm_;
	wire wim_cwp0;
    // Expanded macro begin.
    // cmux4(wim_cwp_mux0,  1,  wim_cwp0, 		wimm[0], 		wimm[1], 		wimm[2], 		wimm[3],  real_cwp[1:0])
    function [ 1:1] wim_cwp_mux0 ;
        input [ 1:1] in0_fn ;
        input [ 1:1] in1_fn ;
        input [ 1:1] in2_fn ;
        input [ 1:1] in3_fn ;