|
|
|
|
|
|
Xilinx Answer #7105 : Mentor: pld_edif2tim gives Error: Unable to resolve reference "my_bus_7_0_" of type "portRef"
Xilinx Answer #6897 : Mentor: I can not check nor convert my old 4K (4000 non-E) schematic design to 4KE or 4KX using A1.5 or later Xilinx software
Xilinx Answer #6555 : Mentor-Xilinx Interface 2.1i: After choosing Quicksim for my simulation in the Xilinx GUI and implementing, I don't see the time_sim.edn for back-end simulation
Xilinx Answer #6453 : Initializing Mentor Quicksim simulation: Net name for the global reset signal for CPLD's (9500)
Xilinx Answer #5713 : pld_men2edif ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections
Xilinx Answer #5348 : Mentor: How to bring up the the pld_* help menu Mentor PDF docs that are installed.
Xilinx Answer #5199 : Mentor: Can I bring a non Mentor design into Quicksim II for a Board Level Timing Simulation?
Xilinx Answer #5197 : Mentor: Possible solution to RAM not simulating correctly in Quicksim II
Xilinx Answer #5090 : Running Mentor programs pld_* I see version M1.5.19 even though I just installed M1.5i (M1.5.25)
Xilinx Answer #4706 : MENTOR (Convert Design) after retargetting design, design is empty.
Xilinx Answer #4500 : Mentor Quicksim M1.5: Which Simulation Program Template to use.
Xilinx Answer #4393 : Mentor Graphics: PLD_DA: How to enter a TIG constraint
Xilinx Answer #4159 : Mentor Graphics/M1/A1 - Recommendations for improving Cross probing into hierarchy
Xilinx Answer #3747 : M1.3 Mentor calc_sot tutorial is missing VHDL source files
Xilinx Answer #3046 : M1: QuickSim functional simulation of a Mentor schematic with instantiated EDIF (without XNF)(From Coregen 1.5 or later, or other sources)
Xilinx Answer #3037 : M1 PLD_EDIF2SIM/XNF2SIM/EDIF2TIM: Error: Could Not find the External part "$SIMPRIMS/___"
Xilinx Answer #2899 : M1: QuickSim functional simulation of a Mentor schematic with instantiated XNF (From Coregen 1.4 or other sources)
Xilinx Answer #2886 : M1 Design Architect: LogiBLOX fails with "newer symbol database version has been encountered"
Xilinx Answer #2847 : M1 QuickHDL: VHDL/VITAL RAMs do not simulate properly or respond to stimuli on HP-UX systems
Xilinx Answer #2639 : Mentor Graphics Library for XACTstep 5.2.1: DECODE16, DECODE8, and DECODE4 library macros are missing DECODE attribute
Xilinx Answer #2581 : Design Architect: Can the generic libraries (gen_lib) be used to in Xilinx schematics?
Xilinx Answer #2560 : M1: Board-level schematic simulation methodology for QuickSim
Xilinx Answer #2485 : M1 QVHCOM: Could not open library simprim/logiblox/unisim, unknown identifier
Xilinx Answer #2478 : M1 QuickHDL: How to compile the HDL simprim, LogiBLOX, Unisim, and Coregen libraries (VHDL and Verilog)
Xilinx Answer #2100 : M1 PLD_EDIF2TIM: Error: Cannot find library specified "SIMPRIMS"
Xilinx Answer #2069 : QuickSim II: Output of XBLOX BUS_IFxx component is X
Xilinx Answer #1896 : M1 QuickSim: GSR (global set/reset) port removed from XC4000EX library
Xilinx Answer #1844 : Mentor schematic: Adding an INIT property to a CPLD flip-flop
Xilinx Answer #1843 : QuickSim: Mode pins (MDO, MD1, MD2) cannot be used in board-level simulation.
Xilinx Answer #1562 : QuickSim: MODEL property expected but not found, NULL model will be inserted
Xilinx Answer #1441 : Timsim8 ends with return code 100 (XNFBA error 256) on non-Mentor XBLOX design
Xilinx Answer #1311 : men2xnf8/enwrite: Pin mapping from part interface to superseding interface not possible
Xilinx Answer #1262 : Quicksim II: Could not find a registered simulation model, NULL model will be inserted
Xilinx Answer #1246 : Fncsim8/XBLXGS fails under Mentor B.x with "Unresolved Propagate symbol"
Xilinx Answer #1245 : Gen_sch8 fails under Mentor B.x with "Unresolved Propagate symbol"
Xilinx Answer #1076 : Quicksim II: Obsolete-library RAMs and ROMs output X's in XACT 5.2
Xilinx Answer #1074 : Timsim8: "return code 1" from segmentation fault under Solaris
Xilinx Answer #1022 : Quicksim II: No-connects appear on Fncsim8-created schematic containing XBLOX
Xilinx Answer #1013 : Gen_sch8 error: Bad status 79501087 from ddp__add_instance
Xilinx Answer #1010 : Timsim8/PLD_DVE_BA gives "Delete operation on object failed"
Xilinx Answer #997 : Using XACT 5.2.1 with Mentor Graphics' B.x release
Xilinx Answer #913 : PLD_Men2XNF8 5.x: "test: unknown operator"
Xilinx Answer #905 : Mentor/EDIF2XNF: purple LOC properties on PADs are lost, gold properties are fine
Xilinx Answer #895 : XBLXGS 5.x fails on Solaris with "crt1:bad open" or "libbase: can't open file"
Xilinx Answer #894 : Gen_sch8 5.x fails on Solaris with "crt1:bad open" or "libbase: can't open file"
Xilinx Answer #893 : QuickSim/Solaris: Could not load object file xxx.ss5_b, no such file or directory
Xilinx Answer #798 : Retargeting a design in Mentor Design Architect (Convert Design)
Xilinx Answer #786 : Fncsim8/XBLXGS fails under Mentor B.x with "call to undefined procedure"
Xilinx Answer #768 : Gen_sch8/XBLXGS: ld.so: libeddm.so.1/libbase_lib.so.14: not found
Xilinx Answer #766 : How to delete a design viewpoint in Mentor 8
Xilinx Answer #762 : EDIF2XNF error 6, "module.eds" not found in directory: possible causes
Xilinx Answer #739 : Gen_sch8 fails under Mentor B.x with "call to undefined procedure"
Xilinx Answer #735 : PLD_DMGR error in Solaris 2.x: font could not be loaded, loading failed
Xilinx Answer #692 : EDIF2XNF: LOC or other I/O properties lost (ENWrite net bundles)
Xilinx Answer #619 : XACT 5.x QuickSim: Board-level simulation for Xilinx FPGAs and CPLDs
Xilinx Answer #618 : Timsim8/PLD_DVE_BA: "WARNING: Unknown design object" on Autologic design
Xilinx Answer #557 : XBLXGS 5.x: possible cause of error "Bad status 79500182 from ddp_perform_check"
Xilinx Answer #547 : MEN2XNF8 5.x: Could not find a registered simulation model with label: 'xc____'
Xilinx Answer #509 : Mentor Graphics 8.x on Sun workstations: F1 key gives Sun help instead of Mentor functions
Xilinx Answer #463 : PLD_DVE/PLD_DVE_Sim 5.x appears to hang
Xilinx Answer #456 : Mentor Autologic: inserting PADs instead of PORTs causes XNFPrep ERROR 3527
Xilinx Answer #429 : PLD_DA/EDIF2XNF 5.x: LOC properties placed on pads do not appear in netlist
Xilinx Answer #396 : EDIF2XNF 5.x: Error 3, port name not found on external library primitive for cell
Xilinx Answer #391 : PLD_DA/Design Architect: "Error: Attempt to connect failed (for child of schematic named schematic)"
Xilinx Answer #390 : GEN_SCH8 5.x: Can't open shared lib /tools/idea/lib/libC.sl
Xilinx Answer #329 : XACT 5.x Design Architect: calling up old design gives "cannot determine version" error
Xilinx Answer #308 : Mentor 8: Using XACT 5 Timespec, TNM on an old library XC3000A/XC4000 design
Xilinx Answer #292 : Mentor Version 8 Interface User Guide (April 1994): erroneous statement on page 11-63
Xilinx Answer #155 : PLD_DA Check: Unable to evaluate property, unable to resolve lca_technology
Xilinx Answer #141 : QuickSim: Unable to resolve expression symbol lca_technology, NULL model will be inserted
Xilinx Answer #130 : Mentor 8.x: PLD_DA can't instantiate components, parts come up blank. Can select comps, but not place them. Component $LCA/<device>/<component> does not exist
Xilinx Answer #105 : Initializing Mentor QuickSim simulation: Net names for the global reset signal