parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRECLKC8I.v,v 1.1 1995/10/31 01:59:04 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRECLKC8I ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIBUF.v,v 1.1 1995/04/29 02:45:27 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIBUF (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
buf
(Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIBUFBZ.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIBUFBZ (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL$Z = 1;
parameter
CMOS_TO_TTL$PO = 1;
parameter
CLOAD$Z = 85;
parameter
CLOAD$PO = 85;
buf (A_int, A);
nand #(0.0,0.0)
(PO, A_int, PI);
buf #(0.0, 0.0)
(Z, A_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIBUFF.v,v 1.1 1996/03/26 02:27:45 samir Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIBUFF (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
buf
(Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIBUFN.v,v 1.1 1995/04/29 02:45:29 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIBUFN (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
not
(Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIBUFNF.v,v 1.1 1996/03/26 02:27:49 samir Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIBUFNF (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
not
(Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREICPTN.v,v 1.1 1996/03/29 01:32:56 samir Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREICPTN (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
nand #(0.0, 0.0)
(PO, AN, PI);
not
(AN, A);
not #(0.0, 0.0)
(Z, AN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREICPTNF.v,v 1.1 1996/03/26 02:27:53 samir Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREICPTNF (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
nand #(0.0, 0.0)
(PO, AN, PI);
not
(AN, A);
not #(0.0, 0.0)
(Z, AN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIIDDTN.v,v 1.1 1995/10/31 01:59:05 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIIDDTN (IDDTN,PO,A,PI);
output IDDTN,PO;
input A,PI;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$IDDTN = 0;
parameter
CLOAD$PO = 0;
nand #(0.0, 0.0)
(PO, IDDTN_int, PI);
not
(IDDTN_int, A);
buf #(0.0, 0.0)
(IDDTN, IDDTN_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBRPS.v,v 1.1 1995/10/31 01:59:06 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBRPS ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBRPW.v,v 1.1 1995/10/31 01:59:08 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBRPW ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBRS.v,v 1.1 1995/10/31 01:59:09 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBRS ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBRW.v,v 1.1 1995/10/31 01:59:10 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBRW ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBS.v,v 1.1 1995/10/31 01:59:11 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBS ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBTRPS.v,v 1.1 1995/10/31 01:59:13 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBTRPS ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBTRPW.v,v 1.1 1995/10/31 01:59:14 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBTRPW ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBTRS.v,v 1.1 1995/10/31 01:59:16 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBTRS ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBTRW.v,v 1.1 1995/10/31 01:59:18 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBTRW ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBTS.v,v 1.1 1995/10/31 01:59:19 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBTS ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBTW.v,v 1.1 1995/10/31 01:59:20 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBTW ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREIOBW.v,v 1.1 1995/10/31 01:59:22 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREIOBW ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREOSCIM70.v,v 1.1 1995/10/31 01:59:23 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREOSCIM70 ( ZI, A);
output ZI;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZI = 0;
not #(0.0, 0.0)
( ZI, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRESCHMITC.v,v 1.1 1995/04/29 02:45:44 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRESCHMITC (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
buf
(Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRESCHMITCF.v,v 1.1 1996/03/26 02:27:56 samir Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRESCHMITCF (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
buf (Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRESCHMITCN.v,v 1.1 1995/04/29 02:45:46 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRESCHMITCN (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
not
(Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRESCHMITCNF.v,v 1.1 1996/03/26 02:28:00 samir Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRESCHMITCNF (Z,PO,A,PI);
output Z,PO ;
input A,PI ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
not (Z_int, A);
nand #(0.0, 0.0)
(PO, Z_int, PI);
buf #(0.0, 0.0)
(Z, Z_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PROCMONA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PROCMONA ( Z, A, E, S, N);
output Z;
input A, E, S, N;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and ( AE, A, E);
nor ( NAE, A, E);
or ( OAE, AE, NAE);
nand ( NAEN, A, E);
xnor ( XNAE, NAEN, OAE);
CSL_MUX21 #(0.0, 0.0)
M1 (Z, N, XNAE, S);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PROC_DRV.v,v 1.1 1995/10/31 01:59:24 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PROC_DRV
( Z,A,EN);
output Z
;
input A
, EN
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
buf
( EN_int, EN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: RBDEPCIF.v,v 1.1 1995/08/01 00:13:51 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module RBDEPCIF
(IO,ZI,PO,A,EN,TN,PI);
output ZI
,PO
;
input A
,EN
,TN
,PI
;
inout IO
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$ZI = 0;
parameter
CLOAD$PO = 0;
not (ENN, EN);
nand
(TN_ENN, TN, ENN);
nand #(0.0, 0.0)
(PO, PI, ZI_int);
buf
(ZI_int, IO);
bufif0 #(0.0, 0.0)
(IO, A, TN_ENN);
buf #(0.0, 0.0)
(ZI, ZI_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: RBDEPCI5F.v,v 1.1 1996/05/14 20:06:37 libmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
![[Up: PCI_BI pci_bidi_slot]](v2html-up.gif)
module RBDEPCI5F
( IO,ZI,PO,A,EN,TN,PI ) ;
inout IO
;
output ZI
,PO
;
input A
,EN
,TN
,PI
;
not (ENN, EN);
nand (TN_ENN, TN, ENN);
buf (ZI_int, IO);
bufif0 #(0.0, 0.0)
(IO, A, TN_ENN);
buf #(0.0, 0.0)
(ZI, ZI_int);
nand #(0.0, 0.0)
(PO, PI, ZI_int);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: RBDEPCI25F.v,v 1.1 1996/08/29 01:12:00 libmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module RBDEPCI25F
( IO,ZI,PO,A,EN,TN,PI ) ;
inout IO
;
output ZI
,PO
;
input A
,EN
,TN
,PI
;
not (ENN, EN);
nand (TN_ENN, TN, ENN);
buf (ZI_int, IO);
bufif0 #(0.0, 0.0) (IO, A, TN_ENN);
buf #(0.0, 0.0) (ZI, ZI_int);
nand #(0.0, 0.0) (PO, PI, ZI_int);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: SCN4IMA.v,v 1.10 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module SCN4IMA
(DOUT,INST,TDO,DINP,MODE,TDI,SHIFT,TCK,UPDATE,SETN);
output DOUT
,INST
,TDO
;
input DINP
,MODE
,TDI
,SHIFT
,TCK
,UPDATE
,SETN
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$DOUT = 0;
parameter
CLOAD$INST = 0;
parameter
CLOAD$TDO = 0;
reg
notifier1
, notifier2
;
CSL_MUX21 #(0.0, 0.0)
M1 (DOUT, DINP, INST, MODE);
CSL_MUX21 #(0.0, 0.0)
M2 (i1
, DINP, TDI, SHIFT);
CSL_FD3_Q #(0.0, 0.0)
M3 (TDO, i1, TCK, 1'b1, 1'b1, notifier1);
not (UPDATEN,UPDATE);
CSL_LD5 #(0.0, 0.0)
M4 (INST, TDO, UPDATEN
, SETN, notifier2);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: SRLC1A.v,v 1.2 1995/02/02 02:50:32 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module SRLC1A
(Q1, Q1N, Q2, Q2N, D, C1, SI, TC, C2);
output Q1
, Q1N
, Q2
, Q2N
;
input D
, C1
, SI
, TC
, C2
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Q1 = 0;
parameter
CLOAD$Q1N = 0;
parameter
CLOAD$Q2 = 0;
parameter
CLOAD$Q2N = 0;
reg
notifier1
;
reg
notifier2
;
buf #(0.0, 0.0)
(Q1, Q1T);
buf #(0.0, 0.0)
(Q2, Q2T);
not #(0.0, 0.0)
(Q1N, Q1T);
not #(0.0, 0.0)
(Q2N, Q2T);
CSL_SRLC0
M1 (Q1T_int
, D, C1, SI, TC);
CSL_NOTI
(Q1T, Q1T_int, notifier1);
CSL_LD3
M2 (Q2T
, Q1T
, C2, 1, notifier2);
This page: |
Created: | Thu Aug 19 12:01:33 1999 |
| From: |
../../../sparc_v8/lib/rtl/csl_lib.v
|