endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD4PUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD4PUDR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD4PUFDR.v,v 1.2 1996/04/03 18:14:14 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD4PUFDR
(IO,Z,A,EN,TN);
output Z
;
input A
,EN
,TN
;
inout IO
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
not (ENN, EN);
nand
(TN_ENN, TN, ENN);
buf #(0.0, 0.0)
(Z, IO);
bufif0 #(0.0, 0.0)
(IO, A, TN_ENN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD6DR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD6DR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD6FDR.v,v 1.2 1996/04/03 18:14:14 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
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module BD6FDR
(IO,Z,A,EN,TN);
output Z
;
input A
,EN
,TN
;
inout IO
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
not (ENN, EN);
nand
(TN_ENN, TN, ENN);
buf #(0.0, 0.0)
(Z, IO);
bufif0 #(0.0, 0.0)
(IO, A, TN_ENN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD6PDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD6PDDR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD6PDFDR.v,v 1.2 1996/04/03 18:14:14 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD6PDFDR
(IO,Z,A,EN,TN);
output Z
;
input A
,EN
,TN
;
inout IO
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
not (ENN, EN);
nand
(TN_ENN, TN, ENN);
buf #(0.0, 0.0)
(Z, IO);
bufif0 #(0.0, 0.0)
(IO, A, TN_ENN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD6PUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD6PUDR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD6PUFDR.v,v 1.2 1996/04/03 18:14:14 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD6PUFDR
(IO,Z,A,EN,TN);
output Z
;
input A
,EN
,TN
;
inout IO
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
not (ENN, EN);
nand
(TN_ENN, TN, ENN);
buf #(0.0, 0.0)
(Z, IO);
bufif0 #(0.0, 0.0)
(IO, A, TN_ENN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD8DR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD8DR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD8PDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD8PDDR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD8PUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BD8PUDR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_SKEW = 0.1;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BDPCI.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module BDPCI
( IO,ZI,PO,A,EN,TN,PI ) ;
inout IO
;
output ZI
,PO
;
input A
,EN
,TN
,PI
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$PO = 0;
parameter
CLOAD$ZI = 0;
parameter
CLOAD$IO = 85;
not (T, TN);
nor
(IEN, T, EN);
nand #(0.0, 0.0)
(PO, PI, IO_int_n);
buf #(0.0, 0.0)
(ZI, IO_int_n);
buf
(IO_int_n, IO);
bufif1 #(0.0, 0.0)
(IO, A, IEN);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: BHD1A.v,v 1.4 1995/02/02 19:03:47 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BHD1A
( A ) ;
inout A
;
parameter
CMOS_TO_TTL = 0;
trireg
A;
buf (A_int, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BTS4A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BTS4A
( Z,A,E);
output Z
;
input A
, E
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
bufif1 #(0.0, 0.0)
( Z, A, E);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BTS4B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BTS4B
( Z,A,E);
output Z
;
input A
, E
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
bufif1 #(0.0, 0.0)
( Z, A, E);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BTS4C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BTS4C
( Z,A,E);
output Z
;
input A
, E
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
bufif1 #(0.0, 0.0)
( Z, A, E);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BTS5A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BTS5A
( Z,A,E);
output Z
;
input A
, E
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
notif1 #(0.0, 0.0)
( Z, A, E);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BTS5B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BTS5B
( Z,A,E);
output Z
;
input A
, E
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
notif1 #(0.0, 0.0)
( Z, A, E);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BTS5C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BTS5C
( Z,A,E);
output Z
;
input A
, E
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
notif1 #(0.0, 0.0)
( Z, A, E);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFA
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFB.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFB
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFC
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFD.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFD
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFE.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFE
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFF.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFF
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BUFL.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BUFL
( Z, A);
output Z
;
input A
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ25DR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BZ25DR
(IO,Z,AP,AN);
output Z
;
input AN
,AP
;
inout IO
;
trireg F
;
parameter
CMOS_TO_TTL$IO = 0;
parameter
CLOAD$IO = 85;
parameter
CLOAD$Z = 0;
parameter LCBG10P_BZ_SKEW = 0.5;
wire B
;
reg notifier
;
initial
@B notifier = 1'b0;
buf (AN_int, AN);
buf (AP_int, AP);
always @ (posedge B)
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
begin
#LCBG10P_BZ_SKEW
if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
notifier = ~notifier;
end
xor (B, AN_int, AP_int);
CSL_IO_SKEW (IENB, B, notifier);
and (G, B, AN_int);
CSL_MUX21 (IEN, IENB, 1'bx, G);
pmos (F, 1'b1, AP_int);
nmos (F, 1'b0, AN_int);
bufif1 #(0.0, 0.0) (IO, F, IEN);
buf (IO_int, IO);
buf #(0.0, 0.0) (Z, IO_int);
endmodule
`endcelldefine
`nosuppress_faults
This page: |
Created: | Thu Aug 19 12:01:23 1999 |
| From: |
../../../sparc_v8/lib/rtl/csl_lib.v
|