`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND4A.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND4A ( Z, A, B,C,D);
output Z;
input A, B, C,D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND4C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND4C ( Z, A, B,C,D);
output Z;
input A, B, C,D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND5A.v,v 1.1 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND5A ( Z, A, B,C,D,E);
output Z;
input A, B, C,D, E;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D,E);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND5C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND5C ( Z, A, B,C,D,E);
output Z;
input A, B, C,D, E;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D,E);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND6A.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND6A ( Z, A, B,C,D,E,F);
output Z;
input A, B, C,D, E, F;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D,E,F);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND6C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND6C ( Z, A, B,C,D,E,F);
output Z;
input A, B, C,D, E, F;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D,E,F);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND8A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND8A ( Z, A, B,C,D,E,F,G,H);
output Z;
input A, B, C,D, E, F, G, H;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D,E,F, G, H);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND8C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND8C ( Z, A, B,C,D,E,F,G,H);
output Z;
input A, B, C,D, E, F, G, H;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C,D,E,F, G, H);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NND2A.v,v 1.1 1995/10/14 00:14:26 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NND2A ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    not  (BN, B);
    nand (ZT, A, BN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NND2C.v,v 1.1 1995/10/14 00:14:27 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NND2C ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    not  (BN, B);
    nand (ZT, A, BN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR2A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR2A ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR2B.v,v 1.1 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR2B ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR2C.v,v 1.1 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR2C ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR2L.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR2L ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR3A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR3A ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR3B.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR3B ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR3C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR3C ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR3L.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR3L ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR4A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR4A ( Z, A, B, C, D);
output Z;
input A, B, C, D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR4C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR4C ( Z, A, B, C, D);
output Z;
input A, B, C, D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR5A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR5A ( Z, A, B, C, D, E);
output Z;
input A, B, C, D, E;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D, E);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR5C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR5C ( Z, A, B, C, D, E);
output Z;
input A, B, C, D, E;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D, E);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR6A.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR6A ( Z, A, B, C, D, E, F);
output Z;
input A, B, C, D, E, F;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D, E, F);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR6C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR6C ( Z, A, B, C, D, E, F);
output Z;
input A, B, C, D, E, F;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D, E, F);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR8A.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR8A ( Z, A,B,C,D,E,F,G,H);
output Z;
input A, B, C, D, E, F, G, H;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D, E, F, G, H);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NR8C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NR8C ( Z, A, B, C, D, E, F, G, H);
output Z;
input A, B, C, D, E, F, G, H;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nor #(0.0, 0.0)
    ( Z, A, B, C, D, E, F, G, H);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OA21A.v,v 1.1 1995/10/14 00:14:29 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OA21A ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    or (CT0, A, B);
    and ( ZT, CT0, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OA21C.v,v 1.1 1995/10/14 00:14:31 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OA21C ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    or (CT0, A, B);
    and ( ZT, CT0, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OA222A.v,v 1.1 1995/11/09 20:42:25 vdkmgr Exp $
 
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module OA222A ( Z, A, B, C, D, E, F);
output Z;
input A, B, C, D, E, F;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;
 
    buf #(0.0, 0.0)
    ( Z, ZT);
    or (CT0, A, B);
    or (CT1, C, D);
    or (CT2, E, F);
    and ( ZT, CT0, CT1, CT2);
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OA222C.v,v 1.1 1996/01/13 03:32:39 libmgr Exp $
 
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module OA222C ( Z, A, B, C, D, E, F);
output Z;
input A, B, C, D, E, F;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;
 
    buf #(0.0, 0.0)
    ( Z, ZT);
    or (CT0, A, B);
    or (CT1, C, D);
    or (CT2, E, F);
    and ( ZT, CT0, CT1, CT2);
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OA22A.v,v 1.1 1995/11/09 20:42:26 vdkmgr Exp $
 
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module OA22A ( Z, A, B, C, D);
output Z;
input A, B, C, D;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;
 
    buf #(0.0, 0.0)
    ( Z, ZT);
    or (CT0, A, B);
    or (CT1, C, D);
    and (ZT, CT0, CT1);
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OA22C.v,v 1.1 1995/11/09 20:42:28 vdkmgr Exp $
 
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module OA22C ( Z, A, B, C, D);
output Z;
input A, B, C, D;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;
 
    buf #(0.0, 0.0)
    ( Z, ZT);
    or (CT0, A, B);
    or (CT1, C, D);
    and (ZT, CT0, CT1);
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OR2A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR2A ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OR2B.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR2B ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OR2C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR2C ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OR2L.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR2L ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OR3A.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR3A ( Z, A, B,C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OR3B.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR3B ( Z, A, B,C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: OR3C.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module OR3C ( Z, A, B,C);
output Z;
input A, B, C;

    parameter