`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: AO7A.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module AO7A ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    or ( CT0, A, B);
    nand ( ZT, CT0, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: AO7C.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module AO7C ( Z, A, B, C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    or ( CT0, A, B);
    nand ( ZT, CT0, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: AOI2222A.v,v 1.1 1995/10/14 00:14:15 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module AOI2222A ( Z, A, B, C, D, E, F, G, H);
output Z;
input A, B, C, D, E, F, G, H;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    and (CT0, A, B);
    and (CT1, C, D);
    and (CT2, E, F);
    and (CT3, G, H);
    or ( ZT1, CT0, CT1);
    or ( ZT2, CT2, CT3);
    nor ( ZT, ZT1, ZT2);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: BAL1.v,v 1.4 1995/02/02 19:03:47 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BAL1 ( A ) ;
inout A;
    parameter 
        CMOS_TO_TTL = 0;
    trireg 
        A;
    buf (A_int, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
 // $Header: BAL1A.v,v 1.3 1995/02/23 23:15:27 vdkmgr Exp $
 `delay_mode_path
 `celldefine
 `suppress_faults
 `enable_portfaults
 `timescale 1 ns / 10 ps
 module BAL1A ( Z,A ) ;
 output Z ;
 input A ;
     parameter 
        CMOS_TO_TTL = 0;
     parameter 
	CLOAD$Z = 0;
     bufif1 #(0.0, 0.0)
		(Z, A, 1'b0);

endmodule
 `nosuppress_faults
 `disable_portfaults
 `endcelldefine
// $Header: BD12DR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD12DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD12PDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD12PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD12PUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD12PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD1DR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD1DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD1PDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD1PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD1PUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD1PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD24ADR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD24ADR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD24APDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD24APDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD24APUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD24APUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD2DR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD2DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD2PDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD2PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD2PUDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD2PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD4DR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD4DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD4FDR.v,v 1.2 1996/04/03 18:14:14 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BD4FDR (IO,Z,A,EN,TN);
output Z ; 
input A,EN,TN ; 
inout IO ; 
    parameter 
        CMOS_TO_TTL$IO = 0;
    parameter 
        CLOAD$IO = 85;
    parameter 
        CLOAD$Z = 0;

    not (ENN, EN);
    nand
        (TN_ENN, TN, ENN);
    buf #(0.0, 0.0)
		(Z, IO);
    bufif0 #(0.0, 0.0)
        (IO, A, TN_ENN);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: BD4PDDR.v,v 1.4 1996/01/12 23:35:34 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BD4PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_SKEW = 0.1;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BD4PDFDR.v,v 1.2 1996/04/03 18:14:14 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BD4PDFDR (IO,Z,A,EN,TN);
output Z ; 
input A,EN,TN ; 
inout IO ; 
    parameter 
        CMOS_TO_TTL$IO = 0;
    parameter 
        CLOAD$IO = 85;
    parameter 
        CLOAD$Z = 0;

    not (ENN, EN);
    nand
        (TN_ENN, TN, ENN);
    buf #(0.0, 0.0)
		(Z, IO);
    bufif0 #(0.0, 0.0)
        (IO, A, TN_ENN);