`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: H0802A.v,v 1.8 1995/12/15 01:36:32 libmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module H0802A (Z,SN,A,S,B);
output Z;
input A,B,S,SN;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
    CSL_MUX22
    M1 (ZT,A,B,S,SN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: H0802B.v,v 1.8 1995/12/15 01:36:35 libmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module H0802B (Z,SN,A,S,B);
output Z;
input A,B,S,SN;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
    CSL_MUX22
    M1 (ZT,A,B,S,SN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: H0802C.v,v 1.8 1995/12/15 01:36:37 libmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module H0802C (Z,SN,A,S,B);
output Z;
input A,B,S,SN;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
    CSL_MUX22
    M1 (ZT,A,B,S,SN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: HA1A.v,v 1.1 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module HA1A (S, CO, A, B);
output S, CO;
input A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    xor #(0.0,0.0)
        (S, A, B);
    and #(0.0,0.0)
        (CO, A, B);
 
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: HA1B.v,v 1.1 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module HA1B (S, CO, A, B);
output S, CO;
input A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    xor #(0.0,0.0)
        (S, A, B);
    and #(0.0,0.0)
        (CO, A, B);
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: HA1C.v,v 1.1 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module HA1C (S, CO, A, B);
output S, CO;
input A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    xor #(0.0,0.0)
        (S, A, B);
    and #(0.0,0.0)
        (CO, A, B);
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IBUFDR.v,v 1.1 1995/10/31 01:58:46 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IBUFDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IBUFFDR.v,v 1.1 1996/03/26 02:27:30 samir Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IBUFFDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IBUFPDDR.v,v 1.1 1995/10/31 01:58:48 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IBUFPDDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IBUFPDFDR.v,v 1.1 1996/03/26 02:27:34 samir Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IBUFPDFDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IBUFPUDR.v,v 1.1 1995/10/31 01:58:50 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IBUFPUDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IBUFPUFDR.v,v 1.1 1996/03/26 02:27:37 samir Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IBUFPUFDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IDIFH2.v,v 1.10 1995/12/15 01:36:41 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IDIFH2 (Z,PO,A,AN,PI,IDDTN);
output Z,PO ;
input A,AN,PI,IDDTN ;
    parameter  CMOS_TO_TTL = 0 ;
    parameter  CLOAD$Z   = 0 ;
    parameter  CLOAD$PO   = 0 ;

nand (PO,Z_int,PI);

    CSL_MUX21 
	U1 (Z_int, 1, i1, IDDTN);

    CSL_MUX21 
	U2 (i1, 1'bx, A, i2);
or (i2,i3,i4);
not (AB, A);
not (ANB, AN);
and (i3,AB,AN);
and (i4,A,ANB);


buf  #(0.0, 0.0)
(Z, Z_int);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IIDDTNDR.v,v 1.1 1995/10/31 01:58:52 vdkmgr Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IIDDTNDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: IIDDTNFDR.v,v 1.1 1996/03/26 02:27:41 samir Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module IIDDTNFDR ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: L1DPLD1TSQN2FA.v,v 1.2 1996/01/25 00:41:56 libmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module L1DPLD1TSQN2FA (QN,D,G0,G1,S0,SN0,S1,SN1);
output QN;
input D, G0, G1, S0, SN0, S1, SN1;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$QN = 0;
    reg
        notifier;

    CSL_LD3 
        (QT0, D, G0, 1'b1, notifier);
    CSL_LD3 
        (QT1, D, G1, 1'b1, notifier);

    xnor (SEL0, S0, SN0);
    xnor (SEL1, S1, SN1);

	notif1 (QN_int, QT0, S0);
	notif0 (QN_int, QT0, SN0);
	notif1 (QN_int, 1'bx, SEL0);

	notif1 (QN_int, QT1, S1);
	notif0 (QN_int, QT1, SN1);
	notif1 (QN_int, 1'bx, SEL1);

    nmos #(0.0, 0.0)
    (QN, QN_int, 1'b1);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LCLKBUF1A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LCLKBUF1A (Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    (Z, A);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LCLKBUF2A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LCLKBUF2A (Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    (Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LCLKBUF3A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LCLKBUF3A (Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    (Z, A);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LCLKBUF7A.v,v 1.1 1995/10/31 01:58:53 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LCLKBUF7A (Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0) 
    (Z, A);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD1QA.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD1QA (Q,D,G);
output Q ;
input D, G ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
    (Q, QT);
    CSL_LD3 (QT, D, G, 1, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD1QC.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD1QC (Q,D,G);
output Q ;
input D, G ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
    (Q, QT);
    CSL_LD3 (QT, D, G, 1, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD1S2QA.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD1S2QA (Q, D, CP, SCK1, SCK2, SI);
output Q ;
input D, CP, SCK1, SCK2, SI;
wire Z;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier1;
    reg 
        notifier2;

    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD1S1 
    M1 (QT, D, CP, SCK1, Z, notifier1);
    CSL_LD3 
    M2 (Z, SI, SCK2, 1, notifier2); 
    
    not (CPN, CP);
    and (SCK2_CPN, SCK2, CPN);

 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD1S2QC.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD1S2QC (Q, D, CP, SCK1, SCK2, SI);
output Q ;
input D, CP, SCK1, SCK2, SI;
wire Z;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier1;
    reg 
        notifier2;

    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD1S1 
    M1 (QT, D, CP, SCK1, Z, notifier1);
    CSL_LD3 
    M2 (Z, SI, SCK2, 1, notifier2); 
    
    not (CPN, CP);
    and (SCK2_CPN, SCK2, CPN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD2QA.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD2QA (Q, D, GN);
output Q;
input  D, GN;
wire G;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD3 
    M1 (QT, D, G, 1, notifier);
    not (G, GN);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD2QC.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD2QC (Q, D, GN);
output Q;
input  D, GN;
wire G;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD3 
    M1 (QT, D, G, 1, notifier);
    not (G, GN);



endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD3QA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD3QA (Q, D, G, CD);
output Q;
input D, G, CD;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD3 
    M1 (QT, D, G, CD, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD3QC.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD3QC (Q, D, G, CD);
output Q;
input D, G, CD;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD3 
    M1 (QT, D, G, CD, notifier);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD4QA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD4QA (Q, D, GN, CD);    
output Q;
input  D, GN, CD;
wire G;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD3
    M1 (QT, D, G, CD, notifier);
    not (G, GN);



endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LD4QC.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LD4QC (Q, D, GN, CD);    
output Q;
input  D, GN, CD;
wire G;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_LD3
    M1 (QT, D, G, CD, notifier);
    not (G, GN);




endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LSR0A.v,v 1.3 1995/02/01 20:15:24 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LSR0A (Q, QN, S, R);
output Q, QN;
input  S, R;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    parameter
        CLOAD$QN = 0;
    reg
        notifier;
    not #(0.0, 0.0)
        (QN, QT);
    not #(0.0, 0.0)
    (Q, QNT);
    CSL_LSR1
        M1 (QT_int, 1'b1, 1'b1, S, 1'b1, 1'b1, R);
    CSL_NOTI 
        M2 (QT, QT_int, notifier); 
    CSL_LSR1N    
        M3 (QNT_int, 1'b1, 1'b1, S, 1'b1, 1'b1, R);
    CSL_NOTI 
        M4 (QNT, QNT_int, notifier);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LSR2A.v,v 1.5 1995/02/01 20:15:58 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LSR2A (Q, QN, S, R, G, SD, RD);
output Q, QN; 
input S, R, G, SD, RD; 

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    parameter
        CLOAD$QN = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
    (Q, QT);
    buf #(0.0, 0.0)
    (QN, QNT);
    CSL_LSR2
    M1 (QT_int, S, R, G, SD, RD);
    CSL_LSR2N
    M2 (QNT_int, S, R, G, SD, RD);
    CSL_NOTI
    (QT, QT_int, notifier);
    CSL_NOTI
    (QNT, QNT_int, notifier);

// timing check related logic
        not ( NG, G);
        and ( Z, NG, S, R);
        or ( COND1, G , Z);
        and ( COND2, RD, SD, NG);
        and ( COND3, SD, R , NG);
        and ( COND4, RD, S, NG);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: LSR2BUFA.v,v 1.2 1995/02/01 20:16:06 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module LSR2BUFA (Q, QN, S, R, G, SD, RD);
output Q, QN; 
input S, R, G, SD, RD; 

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    parameter
        CLOAD$QN = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
    (Q, QT);
    buf #(0.0, 0.0)
    (QN, QNT);
    CSL_LSR2
    M1 (QT_int, S, R, G, SD, RD);
    CSL_LSR2N
    M2 (QNT_int, S, R, G, SD, RD);
    CSL_NOTI
    (QT, QT_int, notifier);
    CSL_NOTI
    (QNT, QNT_int, notifier);

// timing check related logic
        not ( NG, G);
        and ( Z, NG, S, R);
        or ( COND1, G , Z);
        and ( COND2, RD, SD, NG);
        and ( COND3, SD, R , NG);
        and ( COND4, RD, S, NG);

endmodule

`endcelldefine
`nosuppress_faults