parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, CD, SD, notifier);
           
    CSL_MUX21 
	M3 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (CD_SD, CD, SD);
    and
        (DXTI_CD_SD, DXTI, CD_SD);
    and
        (TEN_CD_SD, TEN, CD_SD);
    and
        (TE_CD_SD, TE, CD_SD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD3SQC.v,v 1.6 1995/07/10 21:19:35 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD3SQC (Q,D,CP,CD,SD,TI,TE);
output Q ; 
input D,CP,CD,SD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, CD, SD, notifier);
           
    CSL_MUX21 
	M3 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (CD_SD, CD, SD);
    and
        (DXTI_CD_SD, DXTI, CD_SD);
    and
        (TEN_CD_SD, TEN, CD_SD);
    and
        (TE_CD_SD, TE, CD_SD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD4QA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD4QA (Q,D,CP,SD);
output Q ; 
input D,CP,SD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, 1, SD, notifier);

 

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD4QC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD4QC (Q,D,CP,SD);
output Q ; 
input D,CP,SD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, 1, SD, notifier);

 

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD4SQA.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD4SQA (Q,D,CP,SD,TI,TE);
output Q ; 
input D,CP,SD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, SD, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (DXTI_SD, DXTI, SD);
    and
        (TEN_SD, TEN, SD);
    and
        (TE_SD, TE, SD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD4SQC.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD4SQC (Q,D,CP,SD,TI,TE);
output Q ; 
input D,CP,SD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, SD, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (DXTI_SD, DXTI, SD);
    and
        (TEN_SD, TEN, SD);
    and
        (TE_SD, TE, SD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN1QA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN1QA (Q,D,CPN);
output Q ; 
input D,CPN ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not
        (CP, CPN);
    CSL_FD3_Q 
        M1 (QT, D, CP, 1, 1, notifier);
 

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN1QC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN1QC (Q,D,CPN);
output Q ; 
input D,CPN ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not
        (CP, CPN);
    CSL_FD3_Q
        M1 (QT, D, CP, 1, 1, notifier);
 

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN1SQA.v,v 1.1 1995/10/31 01:58:43 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN1SQA (Q,D,CPN,TI,TE);
output Q ; 
input D,CPN,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not
		(CP, CPN);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    xor
    (DXTI, D, TI);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN1SQC.v,v 1.1 1995/10/31 01:58:45 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN1SQC (Q,D,CPN,TI,TE);
output Q ; 
input D,CPN,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not
		(CP, CPN);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    xor
    (DXTI, D, TI);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN2QA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN2QA (Q,D,CPN,CD);
output Q ; 
input D,CPN,CD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    CSL_FD3_Q 
        M1 (QT, D, CP, CD, 1, notifier);
    buf  #(0.0, 0.0)
        (Q, QT);
    not 
        (CP, CPN);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN2QC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN2QC (Q,D,CPN,CD);
output Q ; 
input D,CPN,CD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    CSL_FD3_Q 
        M1 (QT, D, CP, CD, 1, notifier);
    buf  #(0.0, 0.0)
        (Q, QT);
    not 
        (CP, CPN);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN2SQA.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN2SQA (Q,D,CPN,CD,TI,TE);
output Q ; 
input D,CPN,CD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf  #(0.0, 0.0)
        (Q, QT);
    not
        (CP, CPN);
    CSL_FD3_Q 
        M1 (QT, Y, CP, CD, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (DXTI_CD, DXTI, CD);
    and
        (TEN_CD, TEN, CD);
    and
        (TE_CD, TE, CD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FDN2SQC.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FDN2SQC (Q,D,CPN,CD,TI,TE);
output Q ; 
input D,CPN,CD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf  #(0.0, 0.0)
        (Q, QT);
    not
        (CP, CPN);
    CSL_FD3_Q 
        M1 (QT, Y, CP, CD, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (DXTI_CD, DXTI, CD);
    and
        (TEN_CD, TEN, CD);
    and
        (TE_CD, TE, CD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK1QA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK1QA (Q,J,K,CP);
output Q ; 
input J,K,CP ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, J, K, CP, 1, 1, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK1QC.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK1QC (Q,J,K,CP);
output Q ; 
input J,K,CP ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, J, K, CP, 1, 1, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK1SQA.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK1SQA (Q,J,K,CP,TI,TE);
output Q ;
input J,K,CP,TI,TE ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3S_Q
        M1 (QT, J, K, TI, TE, CP, 1, 1, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (JN, J);
    not (KN, K);
    not (TIN, TI);
    and
    (J_K, J, K);
    and
    (TI_JN_K, TI, JN, K);
    and
    (TIN_J_KN, TIN, J, KN);
    or
    (J_K__TI_JN_K__TIN_J_KN, J_K, TI_JN_K, TIN_J_KN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK1SQC.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK1SQC (Q,J,K,CP,TI,TE);
output Q ;
input J,K,CP,TI,TE ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3S_Q
        M1 (QT, J, K, TI, TE, CP, 1, 1, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (JN, J);
    not (KN, K);
    not (TIN, TI);
    and
    (J_K, J, K);
    and
    (TI_JN_K, TI, JN, K);
    and
    (TIN_J_KN, TIN, J, KN);
    or
    (J_K__TI_JN_K__TIN_J_KN, J_K, TI_JN_K, TIN_J_KN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK2QA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK2QA (Q,J,K,CP,CD);
output Q ;
input J,K,CP,CD ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, J, K, CP, CD, 1, notifier);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK2QC.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK2QC (Q,J,K,CP,CD);
output Q ;
input J,K,CP,CD ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, J, K, CP, CD, 1, notifier);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK2SQA.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK2SQA (Q,J,K,CP,CD,TI,TE);
output Q ; 
input J,K,CP,CD,TI,TE ; 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3S_Q
        M1 (QT, J, K, TI, TE, CP, CD, 1, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    and
        (TEN_CD, TEN, CD);
    and
        (TE_CD, TE, CD);
    not (JN, J);
    not (KN, K);
    not (TIN, TI);
    and
    (J_K, J, K);
    and
    (TI_JN_K, TI, JN, K);
    and
    (TIN_J_KN, TIN, J, KN);
    or
    (J_K__TI_JN_K__TIN_J_KN, J_K, TI_JN_K, TIN_J_KN);
    and
    (J_K__TI_JN_K__TIN_J_KN_CD, J_K__TI_JN_K__TIN_J_KN, CD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK2SQC.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK2SQC (Q,J,K,CP,CD,TI,TE);
output Q ; 
input J,K,CP,CD,TI,TE ; 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3S_Q
        M1 (QT, J, K, TI, TE, CP, CD, 1, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    and
        (TEN_CD, TEN, CD);
    and
        (TE_CD, TE, CD);
    not (JN, J);
    not (KN, K);
    not (TIN, TI);
    and
    (J_K, J, K);
    and
    (TI_JN_K, TI, JN, K);
    and
    (TIN_J_KN, TIN, J, KN);
    or
    (J_K__TI_JN_K__TIN_J_KN, J_K, TI_JN_K, TIN_J_KN);
    and
    (J_K__TI_JN_K__TIN_J_KN_CD, J_K__TI_JN_K__TIN_J_KN, CD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK3QA.v,v 1.5 1995/07/10 21:19:37 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK3QA (Q,J,K,CP,CD,SD);
output Q ;
input J,K,CP,CD,SD ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, J, K, CP, CD, SD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    and
        (CD_SD, CD, SD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK3QC.v,v 1.5 1995/07/10 21:19:39 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK3QC (Q,J,K,CP,CD,SD);
output Q ;
input J,K,CP,CD,SD ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, J, K, CP, CD, SD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    and
        (CD_SD, CD, SD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK3SQA.v,v 1.6 1995/07/10 21:19:42 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK3SQA (Q,J,K,CP,CD,SD,TI,TE);
output Q ; 
input J,K,CP,CD,SD,TI,TE ; 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3S_Q
        M1 (QT, J, K, TI, TE, CP, CD, SD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    and
        (CD_SD, CD, SD);
    and
        (TEN_CD_SD, TEN, CD, SD);
    and
        (TE_CD_SD, TE, CD, SD);
    not (JN, J);
    not (KN, K);
    not (TIN, TI);
    and
    (J_K, J, K);
    and
    (TI_JN_K, TI, JN, K);
    and
    (TIN_J_KN, TIN, J, KN);
    or
    (J_K__TI_JN_K__TIN_J_KN, J_K, TI_JN_K, TIN_J_KN);
    and
    (J_K__TI_JN_K__TIN_J_KN_CD_SD, J_K__TI_JN_K__TIN_J_KN, CD_SD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FJK3SQC.v,v 1.6 1995/07/10 21:19:44 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FJK3SQC (Q,J,K,CP,CD,SD,TI,TE);
output Q ; 
input J,K,CP,CD,SD,TI,TE ; 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3S_Q
        M1 (QT, J, K, TI, TE, CP, CD, SD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    and
        (CD_SD, CD, SD);
    and
        (TEN_CD_SD, TEN, CD, SD);
    and
        (TE_CD_SD, TE, CD, SD);
    not (JN, J);
    not (KN, K);
    not (TIN, TI);
    and
    (J_K, J, K);
    and
    (TI_JN_K, TI, JN, K);
    and
    (TIN_J_KN, TIN, J, KN);
    or
    (J_K__TI_JN_K__TIN_J_KN, J_K, TI_JN_K, TIN_J_KN);
    and
    (J_K__TI_JN_K__TIN_J_KN_CD_SD, J_K__TI_JN_K__TIN_J_KN, CD_SD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FT2QA.v,v 1.1 1995/01/21 01:53:17 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FT2QA (Q,CP,CD);
output Q ; 
input CP,CD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FJK3_Q
        M1 (QT, 1, 1, CP, CD, 1, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: H0261AA.v,v 1.6 1995/12/15 01:35:53 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module H0261AA (P0,P1,P2,P3,LO,A0,B0,A1,B1,A2,B2,A3,B3,SBN,SB,RI,SL0,SL1);
output P0,P1,P2,P3,LO;
input A0,B0,A1,B1,A2,B2,A3,B3,SBN,SB,RI,SL0,SL1;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$P0 = 0;
    parameter
        CLOAD$P1 = 0;
    parameter
        CLOAD$P2 = 0;
    parameter
        CLOAD$P3 = 0;
    parameter
        CLOAD$LO = 0;
 
    CSL_MUX22
			(A3_OUT, A3, B3, SB, SBN),
			(A2_OUT, A2, B2, SB, SBN),
			(A1_OUT, A1, B1, SB, SBN),
			(A0_OUT, A0, B0, SB, SBN);
    CSL_H0261   #(0.0, 0.0)
			(P3, A2_OUT, A3_OUT, SL0, SL1),
			(P2, A1_OUT, A2_OUT, SL0, SL1),
			(P1, A0_OUT, A1_OUT, SL0, SL1),
			(P0, RI, A0_OUT, SL0, SL1);
    buf   #(0.0, 0.0)
            (LO, A3_OUT);
 
 
endmodule