`disable_portfaults 
// $Header: MUX21HA.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21HA ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21HB.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21HB ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21HC.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21HC ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21HL.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21HL ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21LA.v,v 1.1 1995/04/29 02:45:22 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21LA ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21LB.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21LB ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21LC.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21LC ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX21LL.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX21LL ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX31HA.v,v 1.2 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX31HA ( Z, D0, D1, D2, A, B);
output Z;
input D0, D1, D2, A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (ZT, D0, D1, D2, D2, A, B);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX31HC.v,v 1.2 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX31HC ( Z, D0, D1, D2, A, B);
output Z;
input D0, D1, D2, A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (ZT, D0, D1, D2, D2, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX41HA.v,v 1.3 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX41HA ( Z, D0, D1, D2, D3, A, B);
output Z;
input D0, D1, D2, D3, A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (ZT, D0, D1, D2, D3, A, B);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX41HC.v,v 1.3 Exp $



`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX41HC ( Z, D0, D1, D2, D3, A, B);
output Z;
input D0, D1, D2, D3, A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (ZT, D0, D1, D2, D3, A, B);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX61HA.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX61HA ( Z, D0, D1, D2, D3,D4, D5, A, B,C);
output Z;
input D0, D1, D2, D3, D4, D5, A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (CT0, D0, D1, D2, D3, A, B);
             
    CSL_MUX41 
	M2 (ZT, CT0, CT0, D4, D5, A, C);
    
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX61HC.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX61HC ( Z, D0, D1, D2, D3,D4, D5, A, B,C);
output Z;
input D0, D1, D2, D3, D4, D5, A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (CT0, D0, D1, D2, D3, A, B);
             
    CSL_MUX41 
	M2 (ZT, CT0, CT0, D4, D5, A, C);
    
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX81HA.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX81HA ( Z, D0, D1, D2, D3,D4, D5, D6, D7, A, B,C);
output Z;
input D0, D1, D2, D3, D4, D5, D6, D7, A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (CT0, D0, D1, D2, D3, A, B);
             
    CSL_MUX41 
	M2 (CT1, D4, D5, D6, D7, A, B);
            
    CSL_MUX21 
	M3 (ZT, CT0, CT1, C); 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MUX81HC.v,v 1.3 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MUX81HC ( Z, D0, D1, D2, D3,D4, D5, D6, D7, A, B,C);
output Z;
input D0, D1, D2, D3, D4, D5, D6, D7, A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
             
    CSL_MUX41 
	M1 (CT0, D0, D1, D2, D3, A, B);
             
    CSL_MUX41 
	M2 (CT1, D4, D5, D6, D7, A, B);
            
    CSL_MUX21 
	M3 (ZT, CT0, CT1, C); 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MX21LA.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MX21LA ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MX21LB.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MX21LB ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MX21LC.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MX21LC ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: MX21LL.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module MX21LL ( Z, A, B, S);
output Z;
input A, B, S;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
    ( Z, ZT);
            
    CSL_MUX21 
	M1 (ZT, A, B, S);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1A.v,v 1.1 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module N1A ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
       ( Z, A);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1B.v,v 1.1 endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1C.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module N1C ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
       ( Z, A);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1D.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module N1D ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
       ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1E.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module N1E ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
       ( Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1F.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module N1F ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
       ( Z, A);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: N1L.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module N1L ( Z, A);
output Z;
input A;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
       ( Z, A);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NAOI22A.v,v 1.1 1995/10/14 00:14:22 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NAOI22A ( Z, A, B, C, D);
output Z;
input A, B, C, D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    nand (CT0, A, B);
    not  (CT1, D);
    nand (CT2, C, CT1);
    and  ( ZT, CT0, CT2);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: NAOI22C.v,v 1.1 1995/10/14 00:14:24 vdkmgr Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module NAOI22C ( Z, A, B, C, D);
output Z;
input A, B, C, D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
    ( Z, ZT);
    nand (CT0, A, B);
    not  (CT1, D);
    nand (CT2, C, CT1);
    and  ( ZT, CT0, CT2);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND2A.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND2A ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND2B.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND2B ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND2C.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND2C ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND2L.v,v 1.1 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND2L ( Z, A, B);
output Z;
input A, B;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND3A.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND3A ( Z, A, B,C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND3B.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND3B ( Z, A, B,C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND3C.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND3C ( Z, A, B,C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: ND3L.v,v 1.2 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module ND3L ( Z, A, B,C);
output Z;
input A, B, C;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    nand #(0.0, 0.0)
    ( Z, A, B, C);

endmodule