/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)csl_lib.v
***
****************************************************************************
****************************************************************************/
// $Header: AND2A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
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module AND2A
( Z, A, B );
output Z
;
input A
,B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND2B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND2B
( Z, A, B );
output Z
;
input A
,B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND2C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND2C
( Z, A, B );
output Z
;
input A
,B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND2L.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND2L
( Z, A, B );
output Z
;
input A
,B
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND3A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND3A
( Z, A, B, C);
output Z
;
input A
,B
,C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND3B.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND3B
( Z, A, B, C);
output Z
;
input A
,B
,C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND3C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND3C
( Z, A, B, C);
output Z
;
input A
,B
,C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND3L.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND3L
( Z, A, B, C);
output Z
;
input A
,B
,C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND4A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND4A
( Z, A, B, C, D);
output Z
;
input A
,B
,C
,D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AND4C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AND4C
( Z, A, B, C, D);
output Z
;
input A
,B
,C
,D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( ZT, A, B, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO11A.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO11A
(Z, A, B, C, D, E, F);
output Z
;
input A
, B
, C
, D
, E
, F
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and (CT0, A, B);
and (CT1, C, D);
and (CT2, E, F);
nor (ZT, CT0, CT1, CT2);
buf #(0.0, 0.0)
( Z, ZT);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO11C.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO11C
(Z, A, B, C, D, E, F);
output Z
;
input A
, B
, C
, D
, E
, F
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and (CT0, A, B);
and (CT1, C, D);
and (CT2, E, F);
nor (ZT, CT0, CT1, CT2);
buf #(0.0, 0.0)
( Z, ZT);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO12A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO12A
(Z, A, B, C, D, E, F, G, H);
output Z
;
input A
, B
, C
, D
, E
, F
, G
, H
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
or ( CT0, A, B);
or ( CT1, C, D);
or ( CT2, E, F);
or ( CT3, G, H);
nand ( ZT, CT0, CT1, CT2, CT3);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO12C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO12C
(Z, A, B, C, D, E, F, G, H);
output Z
;
input A
, B
, C
, D
, E
, F
, G
, H
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
or ( CT0, A, B);
or ( CT1, C, D);
or ( CT2, E, F);
or ( CT3, G, H);
nand ( ZT, CT0, CT1, CT2, CT3);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO1A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO1A
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT, A, B);
nor ( ZT, CT, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO1C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO1C
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and (CT, A, B);
nor #(0.0, 0.0)
( Z, CT, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO211A.v,v 1.1 1995/10/14 00:14:03 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO211A
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
or ( ZT, CT0, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO211C.v,v 1.1 1995/10/14 00:14:05 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO211C
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
or ( ZT, CT0, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO21A.v,v 1.1 1995/10/14 00:14:07 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO21A
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
or ( ZT, CT0, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO21C.v,v 1.1 1995/10/14 00:14:08 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO21C
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
or ( ZT, CT0, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO21NA.v,v 1.1 1995/10/14 00:14:10 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO21NA
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
nand (CT0, A, B);
nand ( ZT, CT0, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO21NC.v,v 1.1 1995/10/14 00:14:11 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO21NC
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
nand (CT0, A, B);
nand ( ZT, CT0, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO222A.v,v 1.1 1995/10/14 00:14:13 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO222A
( Z, A, B, C, D, E, F);
output Z
;
input A
, B
, C
, D
, E
, F
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, C, D);
and (CT2, E, F);
or ( ZT, CT0, CT1, CT2);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO22A.v,v 1.1 1995/11/09 20:42:21 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
![[Up: spares spare_andor1]](v2html-up.gif)
![[Up: spares spare_andor2]](v2html-up.gif)
![[Up: spares spare_andor3]](v2html-up.gif)
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module AO22A
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, C, D);
or ( ZT, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO22C.v,v 1.1 1995/11/09 20:42:23 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO22C
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, C, D);
or ( ZT, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO2A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO2A
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, C, D);
nor ( ZT, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO2C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO2C
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, C, D);
nor ( ZT, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO3A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO3A
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
or (CT, A, B);
nand ( ZT, CT, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO3C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO3C
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
or (CT, A, B);
nand ( ZT, CT, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO4A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO4A
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
or (CT0, A, B);
or (CT1, C, D);
nand ( ZT, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO4C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO4C
( Z, A, B, C, D);
output Z
;
input A
, B
, C
, D
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
or (CT0, A, B);
or (CT1, C, D);
nand ( ZT, CT0, CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO5A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO5A
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, A, C);
and (CT2, B, C);
nor (ZT, CT0, CT1, CT2);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO5C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO5C
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and (CT0, A, B);
and (CT1, A, C);
and (CT2, B, C);
nor (ZT, CT0, CT1, CT2);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO6A.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO6A
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( CT0, A, B);
nor ( ZT, CT0, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: AO6C.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module AO6C
( Z, A, B, C);
output Z
;
input A
, B
, C
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
( Z, ZT);
and ( CT0, A, B);
nor ( ZT, CT0, C);
endmodule
This page: |
Created: | Thu Aug 19 12:01:20 1999 |
| From: |
../../../sparc_v8/lib/rtl/csl_lib.v
|