CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
or #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OR3L.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module OR3L ( Z, A, B,C);
output Z;
input A, B, C;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
or #(0.0, 0.0)
( Z, A, B, C);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OR4A.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module OR4A ( Z, A, B,C, D);
output Z;
input A, B, C, D;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
or #(0.0, 0.0)
( Z, A, B, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OR4C.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module OR4C ( Z, A, B,C, D);
output Z;
input A, B, C, D;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
or #(0.0, 0.0)
( Z, A, B, C, D);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: OSCIM70DR.v,v 1.1 1995/10/31 01:58:56 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module OSCIM70DR ( ZIB, ZX, A);
output ZIB, ZX;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZIB = 0;
parameter
CLOAD$ZX = 0;
not #(0.0, 0.0)
( ZIB, A);
not #(0.0, 0.0)
( ZX, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PECLIN.v,v 1.2 1995/05/10 15:53:50 vdkmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module PECLIN ( Z,PO,A,VREF,PI,IDDTN ) ;
output Z,PO ;
input A,VREF,PI,IDDTN ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
not
(VREF_int_n, VREF);
not
(IDDN, IDDTN);
and (VN, IDDTN, VREF_int_n);
CSL_MUX21
(Out, A, 1'bx, VN);
or (ZI_int, Out, IDDN);
buf #(0.0, 0.0)
(Z, ZI_int);
nand #(0.0, 0.0)
(PO, PI, ZI_int);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: PECLINDIFF.v,v 1.5 1995/12/15 01:47:09 libmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module PECLINDIFF ( Z,PO,A,AN,PI,IDDTN ) ;
output Z,PO ;
input A,AN,PI,IDDTN ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$PO = 0;
CSL_ZFAZDET u1 (N1, A, AN, N1);
and u2 (N1A, N1, IDDTN);
xor u3 (N2, A, AN);
CSL_ZFAZERR u4 (N3, A, AN, N2);
not u5 (N4, N3);
bufif1 u6 (N5, N1A, N4);
not u7 (IDDN, IDDTN);
or u8 (Z_int, N5, IDDN);
buf #(0.0, 0.0) (Z, Z_int);
nand #(0.0, 0.0) (PO, PI, Z_int);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: PECLINDIFFN.v,v 1.5 1995/12/15 01:47:16 libmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module PECLINDIFFN ( ZN,PO,A,AN,PI,IDDTN ) ;
output ZN,PO ;
input A,AN,PI,IDDTN ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$PO = 0;
CSL_ZFAZDET u1 (N1, A, AN, N1);
and u2 (N1A, N1, IDDTN);
xor u3 (N2, A, AN);
CSL_ZFAZERR u4 (N3, A, AN, N2);
not u5 (N4, N3);
bufif1 u6 (N5, N1, N4);
nand u7 (ZN_int, N5, IDDTN);
buf #(0.0, 0.0) (ZN, ZN_int);
nand #(0.0, 0.0) (PO, PI, ZN_int);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: PECLINN.v,v 1.2 1995/05/10 17:09:48 vdkmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module PECLINN ( ZN,PO,A,VREF,PI,IDDTN ) ;
output ZN,PO ;
input A,VREF,PI,IDDTN ;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$PO = 0;
not
(A_int_n, A);
not (IDDN, IDDTN);
and (VI, VREF, IDDTN);
CSL_MUX21
(C, 1'bx, A_int_n, VI);
or (ZN_int, C, IDDN);
buf #(0.0, 0.0)
(ZN, ZN_int);
nand #(0.0, 0.0)
(PO, PI, ZN_int);
/**
**/
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: PECLOUT25.v,v 1.2 1995/05/10 17:09:54 vdkmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module PECLOUT25 ( Z,A,IDDTN ) ;
output Z ;
input A,IDDTN;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and (X, A, IDDTN);
bufif1 #(0.0, 0.0)
(Z, 1'b1, X);
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: PECLOUT50.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`celldefine
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
module PECLOUT50 ( Z,A,IDDTN ) ;
output Z ;
input A,IDDTN;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
and (X, A, IDDTN);
bufif1 #(0.0, 0.0)
(Z, 1'b1, X);
/**
**/
endmodule
`nosuppress_faults
`disable_portfaults
`endcelldefine
// $Header: PECLOUTDIFF25.v,v 1.2 1995/05/10 17:10:01 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PECLOUTDIFF25 (Z,ZN,A,IDDTN);
output Z,ZN;
input A,IDDTN;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$ZN = 0;
and (Z_int, A, IDDTN);
nand (ZN_int, A, IDDTN);
bufif1 (Z, 1'b1, Z_int);
bufif1 (ZN, 1'b1, ZN_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PECLOUTDIFF50.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PECLOUTDIFF50 (Z,ZN,A,IDDTN);
output Z,ZN;
input A,IDDTN;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
parameter
CLOAD$ZN = 0;
and (Z_int, A, IDDTN);
nand (ZN_int, A, IDDTN);
bufif1 (Z, 1'b1, Z_int);
bufif1 (ZN, 1'b1, ZN_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLAGN.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLAGN (Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 85;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLDLYQA.v,v 1.1 1995/01/21 01:52:24 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLDLYQA ( Z,A ) ;
output Z;
input A;
parameter
CMOS_TO_TTL$Z = 0;
parameter
CLOAD$Z = 0;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLLP2.v,v 1.2 1995/03/01 21:28:57 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLLP2 (IO, A, EN);
input A, EN;
inout IO;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$IO = 85;
and (IO, A, EN);
buf (M0, IO);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLPGMCB.v,v 1.2 1995/11/01 02:21:19 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLPGMCB (LP2,CKOUT,REF,FB,HIGHFRQ,LOWFRQ,S2,S1,IDDTN,PLLVDD,PLLVSS);
output LP2,CKOUT;
input REF,FB,HIGHFRQ,LOWFRQ,S2,S1,IDDTN,PLLVDD,PLLVSS;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CKOUT = 0;
parameter
CLOAD$LP2 = 0;
reg notifier;
buf (PLLVDD_i, PLLVDD),
(PLLVSS_i, PLLVSS);
and (DUMMY1, S2,S1);
buf (DUMMY2, HIGHFRQ);
buf (DUMMY3, LOWFRQ);
CSL_FD3_Q u12 (S13, 1'b1, REF, CD, 1'b1, notifier);
CSL_FD3_Q u10 (S23, 1'b1, FB, CD,1'b1, notifier);
not u14 (FBB, FB);
bufif1 u15 (S13A, S13, FB);
bufif1 u16 (S13A, S13, FBB);
bufif1 u17 (S23A, S23, FB);
bufif1 u18 (S23A, S23, FBB);
not u19 (REFB, REF);
bufif1 u20 (S13D, S13A, REF);
bufif1 u21 (S13D, S13A, REFB);
bufif1 u22 (S23D, S23A, REF);
bufif1 u23 (S23D, S23A, REFB);
nand u24 (CD1, S13D, S23D);
CSL_SPY u25 (CD2, 1'b0, CD1);
and u26 (CD, CD2, CD1);
bufif1 u27 (LP2_I, 1'b1, S13D);
bufif1 u28 (LP2_I, 1'b0, S23D);
nmos #(0.0, 0.0)
u29 (LP2, LP2_I, 1'b1);
CSL_MUX21 #(0.0, 0.0)
(CKOUT, 1'b0, 1'bx, IDDTN);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLPGMCBFI.v,v 1.2 1996/01/15 05:04:11 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLPGMCBFI
(CKOUT,REF,FB,HIGHFRQ,LOWFRQ,S2,S1,HR,EN,IDDTN,PLLVDD,PLLVSS);
output CKOUT;
input REF,FB,HIGHFRQ,LOWFRQ,S2,S1,HR,EN,IDDTN,PLLVDD,PLLVSS;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$CKOUT = 0;
reg notifier;
buf (PLLVDD_i, PLLVDD),
(PLLVSS_i, PLLVSS);
and (DUMMY1, S2,S1);
buf (DUMMY2, HIGHFRQ);
buf (DUMMY3, LOWFRQ);
buf (DUMMY4, HR);
CSL_FD3_Q u12 (S13, 1'b1, REF, CD, 1'b1, notifier);
CSL_FD3_Q u10 (S23, 1'b1, FB, CD,1'b1, notifier);
not u14 (FBB, FB);
bufif1 u15 (S13A, S13, FB);
bufif1 u16 (S13A, S13, FBB);
bufif1 u17 (S23A, S23, FB);
bufif1 u18 (S23A, S23, FBB);
not u19 (REFB, REF);
bufif1 u20 (S13D, S13A, REF);
bufif1 u21 (S13D, S13A, REFB);
bufif1 u22 (S23D, S23A, REF);
bufif1 u23 (S23D, S23A, REFB);
nand u24 (CD1, S13D, S23D);
CSL_SPY u25 (CD2, 1'b0, CD1);
and u26 (CD, CD2, CD1);
bufif1 u27 (LP2_I, 1'b1, S13D);
bufif1 u28 (LP2_I, 1'b0, S23D);
nmos
u29 (LP2, LP2_I, 1'b1);
CSL_MUX21
(CKOUT_int, 1'b0, 1'bx, IDDTN);
and #(0.0, 0.0)
(CKOUT, EN, CKOUT_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLVDD.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLVDD (Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 85;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLLVSS.v,v 1.1 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLLVSS (Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 85;
buf #(0.0, 0.0)
(Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PORA.v,v 1.1 1995/09/15 19:45:15 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PORA (ZN,A);
output ZN;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
not #(0.0, 0.0)
( ZN, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBTZ.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBTZ ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBTZR.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBTZR ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBTZRP.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBTZRP ( ZN, ZP, A, EN, TN);
output ZN, ZP;
input TN, EN, A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$ZP = 0;
not (AB, A);
not (TNB, TN);
nor (ENBL, EN, TNB);
not (ENBLB, ENBL);
or #(0.0, 0.0) (ZP, AB, ENBLB);
and #(0.0, 0.0) (ZN, AB, ENBL);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBZ.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBZ (ZN,ZP,A);
output ZN,ZP ;
input A ;
parameter
CMOS_TO_TTL$ZN = 1;
parameter
CMOS_TO_TTL$ZP = 1;
parameter
CLOAD$ZP = 85;
parameter
CLOAD$ZN = 85;
not #(0.0, 0.0)
(ZP, A);
not #(0.0, 0.0)
(ZN, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBZR.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBZR (ZN,ZP,A);
output ZN,ZP ;
input A ;
parameter
CMOS_TO_TTL$ZN = 1;
parameter
CMOS_TO_TTL$ZP = 1;
parameter
CLOAD$ZP = 85;
parameter
CLOAD$ZN = 85;
not #(0.0, 0.0)
(ZP, A);
not #(0.0, 0.0)
(ZN, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBZREFN.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBZREFN (ZN,ZP,Z,EN0,EN1,EN2,EN3,EN4,EN5,EP0,EP1,EP2,EP3,EP4,EP5,ZIN);
output ZN,ZP,Z ;
input EN0,EN1,EN2,EN3,EN4,EN5,EP0,EP1,EP2,EP3,EP4,EP5,ZIN ;
parameter
CLOAD$ZP = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$Z = 0;
buf (ZIN_int, ZIN);
buf (EP1_int, EP1);
buf (EP2_int, EP2);
buf (EP3_int, EP3);
buf (EP4_int, EP4);
buf (EP5_int, EP5);
buf (EN5_int, EN5);
or (EN123, EN1, EN2, EN3);
and #(0.0, 0.0)
(Z, EN4, EN123);
buf #(0.0,0.0)
(ZN, EN0);
not #(0.0,0.0)
(ZP, EP0);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBZREFP.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBZREFP (ZN,ZP,Z,EN0,EN1,EN2,EN3,EN4,EN5,EP0,EP1,EP2,EP3,EP4,EP5,ZIN);
output ZN,ZP,Z ;
input EN0,EN1,EN2,EN3,EN4,EN5,EP0,EP1,EP2,EP3,EP4,EP5,ZIN ;
parameter
CLOAD$ZP = 0;
parameter
CLOAD$ZN = 0;
parameter
CLOAD$Z = 0;
buf (ZIN_int, ZIN);
buf (EP5_int, EP5);
buf (EN1_int, EN1);
buf (EN2_int, EN2);
buf (EN3_int, EN3);
buf (EN4_int, EN4);
buf (EN5_int, EN5);
not (EP4N, EP4);
nand (EP123, EP1, EP2, EP3);
nand #(0.0, 0.0)
(Z, EP4, EP123);
buf #(0.0,0.0)
(ZN, EN0);
not #(0.0,0.0)
(ZP, EP0);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PREBZRP.v,v 1.1 1996/04/09 18:21:05 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PREBZRP (ZN,ZP,A);
output ZN,ZP ;
input A ;
parameter
CMOS_TO_TTL$ZN = 1;
parameter
CMOS_TO_TTL$ZP = 1;
parameter
CLOAD$ZP = 85;
parameter
CLOAD$ZN = 85;
not #(0.0, 0.0)
(ZP, A);
not #(0.0, 0.0)
(ZN, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRECHC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRECHC ( Z, PCH);
output Z;
input PCH;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not ( PCHN, PCH);
bufif0 #(0.0, 0.0)
( Z, PCHN, PCH);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRECLKC12I.v,v 1.1 1995/10/31 01:58:58 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRECLKC12I ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRECLKC16I.v,v 1.1 1995/10/31 01:59:00 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRECLKC16I ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRECLKC2I.v,v 1.1 1995/10/31 01:59:01 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRECLKC2I ( Z, A);
output Z;
input A;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Z = 0;
not #(0.0, 0.0)
( Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PRECLKC4I.v,v 1.1 1995/10/31 01:59:02 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PRECLKC4I ( Z, A);
output Z;
input A;
| This page: |
Created: | Thu Aug 19 12:01:32 1999 |
| From: |
../../../sparc_v8/lib/rtl/csl_lib.v
|