`disable_portfaults
// $Header: BZ25PDDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ25PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ25PUDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ25PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ33DR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ33DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ33PDDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ33PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ33PUDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ33PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ50DR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ50DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ50PDDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ50PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ50PUDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ50PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ66DR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ66DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ66PDDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ66PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ66PUDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ66PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ75DR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ75DR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ75PDDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ75PDDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZ75PUDR.v,v 1.1 1996/04/09 18:18:48 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
 
module BZ75PUDR (IO,Z,AP,AN);
output Z ;
input AN,AP;
inout IO ;
trireg F;
    parameter
        CMOS_TO_TTL$IO = 0;
    parameter
        CLOAD$IO = 85;
    parameter
        CLOAD$Z = 0;

    parameter LCBG10P_BZ_SKEW = 0.5;

    wire B;
    reg notifier;

    initial
       @B notifier = 1'b0;
 
    buf (AN_int, AN);
    buf (AP_int, AP);

    always @ (posedge B)
       if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
       begin
          #LCBG10P_BZ_SKEW
          if ( (AP_int === 1'b1) && (AN_int === 1'b0) )
             notifier = ~notifier;
       end
 
    xor (B, AN_int, AP_int);
    CSL_IO_SKEW (IENB, B, notifier);
 
    and (G, B, AN_int);
    CSL_MUX21 (IEN, IENB, 1'bx, G);
 
    pmos (F, 1'b1, AP_int);
    nmos (F, 1'b0, AN_int);

    bufif1 #(0.0, 0.0) (IO, F, IEN);

    buf (IO_int, IO);
    buf #(0.0, 0.0) (Z, IO_int);
 
 
endmodule
 
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZCMPS.v,v 1.1 1996/04/09 18:20:03 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BZCMPS (Z,DATA,REF,VN,VN_1,IDDTN);
output Z ;
input DATA,REF,VN,VN_1,IDDTN ;
    parameter
        CMOS_TO_TTL$Z = 1;
    parameter
        CLOAD$Z  = 85;

    buf (REF_int, REF);
    buf (VN_int, VN);
    buf (VN_1_int, VN_1);
    and #(0.0,0.0)
        (Z, DATA, IDDTN);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: BZDELAY.v,v 1.1 1996/04/09 18:20:03 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BZDELAY (Z,A);
output Z ;
input A ;
    parameter
        CMOS_TO_TTL$Z = 1;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
        (Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: BZDIODE.v,v 1.1 1996/04/08 20:01:55 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BZDIODE (Z,A);
output Z ;
input A ;
    parameter
        CMOS_TO_TTL$Z = 1;
    parameter
        CLOAD$Z = 0;

    buf #(0.0, 0.0)
        (Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: BZIVS.v,v 1.1 1996/04/09 18:20:03 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BZIVS (Z,A);
output Z ;
input A ;
    parameter
        CMOS_TO_TTL$Z = 1;
    parameter
        CLOAD$Z = 0;

    not #(0.0, 0.0)
        (Z, A);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: BZRESET.v,v 1.1 1996/06/10 18:18:13 libmgr Exp $
 
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module BZRESET (Z,A);
  output Z;
  input  A;
 
     buf #(0.0,0.0) (Z, A);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: BZVREF.v,v 1.1 1996/04/08 20:01:55 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module BZVREF (IO,Z,A,EN1,EN2,EN3,EN4,EN5,EP1,EP2,EP3,EP4,EP5);
output IO,Z ;
input A,EN1,EN2,EN3,EN4,EN5,EP1,EP2,EP3,EP4,EP5 ;
    parameter
        CMOS_TO_TTL$IO = 1;
    parameter
        CLOAD$Z = 0;
    parameter
        CLOAD$IO = 0;

	buf (IO, 1'bx);

	buf (EN1_int, EN1);
	buf (EN2_int, EN2);
	buf (EN3_int, EN3);
	buf (EN4_int, EN4);
	buf (EN5_int, EN5);
	buf (EP1_int, EP1);
	buf (EP2_int, EP2);
	buf (EP3_int, EP3);
	buf (EP4_int, EP4);
	buf (EP5_int, EP5);
    not #(0.0, 0.0)
        (Z, A);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: C004.v,v 1.5 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module C004 (S,CO,CIN,A,B);
output S, CO;
input CIN, A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    buf #(0.0,0.0)
        ( S, ST);
    buf #(0.0,0.0)
        ( CO, COT);
    xor (ST, CIN, AB);
    xor (AB, A, B);
           
    CSL_MUX21 
	M2 (COT, A, CIN, AB);
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: C004GA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module C004GA (S,CO,A,B);