`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: EON1C.v,v 1.2 Exp $

`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module EON1C (Z, A, B, C, D);
output Z;
input A, B, C, D;

    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Z = 0;

    or ( CT0, A, B);
    nand ( CT1, C, D);
    nand #(0.0, 0.0)
    ( Z, CT0, CT1);
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FA1AA.v,v 1.4 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FA1AA (S, CO, CI, A, B);
output S, CO;
input CI, A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    buf #(0.0,0.0)
        ( S, ST);
    buf #(0.0,0.0)
        ( CO, COT);
    xor (ST, CI, AB);
    xor (AB, A, B);
           
    CSL_MUX21 
	M1 (COT, B, CI, AB);
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FA1AB.v,v 1.4 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FA1AB (S, CO, CI, A, B);
output S, CO;
input CI, A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    buf #(0.0,0.0)
        ( S, ST);
    buf #(0.0,0.0)
        ( CO, COT);
    xor (ST, CI, AB);
    xor (AB, A, B);
           
    CSL_MUX21 
	M1 (COT, B, CI, AB);
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FA1AC.v,v 1.4 Exp $


`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FA1AC (S, CO, CI, A, B);
output S, CO;
input CI, A, B;
 
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$CO = 0;
    parameter
        CLOAD$S = 0;
 
    buf #(0.0,0.0)
        ( S, ST);
    buf #(0.0,0.0)
        ( CO, COT);
    xor (ST, CI, AB);
    xor (AB, A, B);
           
    CSL_MUX21 
	M1 (COT, B, CI, AB);
 
endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1QA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine


module FD1QA (Q,D,CP);
output Q; 
input D,CP ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, 1, 1, notifier);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1QC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1QC (Q,D,CP);
output Q; 
input D,CP ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, 1, 1, notifier);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SLQA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SLQA (Q,D,CP,LD,TI,TE);
output Q ; 
input D,CP,LD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not (DN, D);
    CSL_FD2SL
        M1 (QT, TI, TE, DN, LD, CP, 1, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
        (DXTI, D, TI);
    and
        (LD_TEN, TEN, LD);
    and
        (DXTI_LD, DXTI, LD);
 

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SLQC.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SLQC (Q,D,CP,LD,TI,TE);
output Q ; 
input D,CP,LD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not (DN, D);
    CSL_FD2SL
        M1 (QT, TI, TE, DN, LD, CP, 1, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
        (DXTI, D, TI);
    and
        (LD_TEN, TEN, LD);
    and
        (DXTI_LD, DXTI, LD);
 

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SQA.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SQA (Q,D,CP,TI,TE);
output Q ; 
input D,CP,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    xor
    (DXTI, D, TI);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SQC.v,v 1.3 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SQC (Q,D,CP,TI,TE);
output Q ; 
input D,CP,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    xor
    (DXTI, D, TI);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SSOA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SSOA (Q,SQ,D,CP,TI,TE);
output Q,SQ ; 
input D,CP,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    parameter 
        CLOAD$SQ = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    buf #(0.0, 0.0)
        (SQ, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    xor
    (DXTI, D, TI);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SSOC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SSOC (Q,SQ,D,CP,TI,TE);
output Q,SQ ; 
input D,CP,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    parameter 
        CLOAD$SQ = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    buf #(0.0, 0.0)
        (SQ, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    xor
    (DXTI, D, TI);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SSQA.v,v 1.5 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SSQA (Q,D,SEL,CP,SCK,TI,TE);
output Q ; 
input D,CP,SEL,SCK,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, DATA, CLOCK, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (DATA, D, TI, TE);
           
    CSL_MUX21 
	M3 (CLOCK, CP, SCK, SEL);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    not (CPN, CP);
    not (SELN, SEL);
    not (SCKN, SCK);
    xor
    (DXTI, D, TI);
    and
        (DXTI_SELN, DXTI, SELN);
    and
        (DXTI_SEL, DXTI, SEL);
    and
        (DXTI_EN1, DXTI, CPN, SCK);
    and
        (DXTI_EN2, DXTI, CP, SCKN);
    and
        (TEN_SELN, TEN, SELN);
    and
        (TE_SELN, TE, SELN);
    and
        (TEN_SEL, TEN, SEL);
    and
        (TE_SEL, TE, SEL);
    and
        (CPN_SCK_TEN, CPN, SCK, TEN);
    and
        (CPN_SCK_TE, CPN, SCK, TE);
    and
        (CP_SCKN_TEN, CP, SCKN, TEN);
    and
        (CP_SCKN_TE, CP, SCKN, TE);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD1SSQC.v,v 1.5 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD1SSQC (Q,D,SEL,CP,SCK,TI,TE);
output Q ; 
input D,CP,SEL,SCK,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, DATA, CLOCK, 1, 1, notifier);
           
    CSL_MUX21 
	M2 (DATA, D, TI, TE);
           
    CSL_MUX21 
	M3 (CLOCK, CP, SCK, SEL);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    not (CPN, CP);
    not (SELN, SEL);
    not (SCKN, SCK);
    xor
    (DXTI, D, TI);
    and
        (DXTI_SELN, DXTI, SELN);
    and
        (DXTI_SEL, DXTI, SEL);
    and
        (DXTI_EN1, DXTI, CPN, SCK);
    and
        (DXTI_EN2, DXTI, CP, SCKN);
    and
        (TEN_SELN, TEN, SELN);
    and
        (TE_SELN, TE, SELN);
    and
        (TEN_SEL, TEN, SEL);
    and
        (TE_SEL, TE, SEL);
    and
        (CPN_SCK_TEN, CPN, SCK, TEN);
    and
        (CPN_SCK_TE, CPN, SCK, TE);
    and
        (CP_SCKN_TEN, CP, SCKN, TEN);
    and
        (CP_SCKN_TE, CP, SCKN, TE);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2ESSA.v,v 1.5 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2ESSA (Q,SQ,D,CP,CD,TI,TE,CE);
output Q,SQ ; 
input D,CP,TI,TE,CD,CE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    parameter 
        CLOAD$SQ = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    buf #(0.0, 0.0)
        (SQ, QT);
    or
        (CD__CE, CD, CE);
    CSL_FD3_Q
        M1 (QT, Y, CP, CD__CE, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
    (TEN_CD__CE, TEN, CD__CE);
    and
    (TE_CD__CE, TE, CD__CE);
    and
    (DXTI_CD__CE, DXTI, CD__CE);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2ESSC.v,v 1.5 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2ESSC (Q,SQ,D,CP,CD,TI,TE,CE);
output Q,SQ ; 
input D,CP,TI,TE,CD,CE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    parameter 
        CLOAD$SQ = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    buf #(0.0, 0.0)
        (SQ, QT);
    or
        (CD__CE, CD, CE);
    CSL_FD3_Q
        M1 (QT, Y, CP, CD__CE, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (TEN, TE);
    xor
    (DXTI, D, TI);
    and
    (TEN_CD__CE, TEN, CD__CE);
    and
    (TE_CD__CE, TE, CD__CE);
    and
    (DXTI_CD__CE, DXTI, CD__CE);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2LQA.v,v 1.2 1996/01/17 22:28:46 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2LQA (Q,D,CP,CD,LD);
output Q ; 
input D,CP,CD,LD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;

    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD2SL
        (QT, D, LD, 1'b0, 1'b0, CP, CD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>

    and
       (CD_LD, CD, LD);




endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2LQC.v,v 1.2 1996/01/17 22:28:46 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2LQC (Q,D,CP,CD,LD);
output Q ; 
input D,CP,CD,LD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;

    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD2SL
        (QT, D, LD, 1'b0, 1'b0, CP, CD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>

    and
       (CD_LD, CD, LD);




endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2QA.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2QA (Q,D,CP,CD);
output Q ; 
input D,CP,CD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, CD, 1, notifier);



endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2QC.v,v 1.2 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2QC (Q,D,CP,CD);
output Q ; 
input D,CP,CD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, CD, 1, notifier);



endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2SL2QA.v,v 1.2 1996/02/01 20:17:24 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2SL2QA (Q,D,CP,CD,TI,TE,LD);
output Q ;
input D,CP,LD,TI,TE,CD ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not
        (DN, D);
    CSL_FD2SL
        M1 (QT, TI, TE, DN, LD, CP, CD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (LDN, LD);

    xor (DXTI, D, TI);
    and (LDN_TE_CD, LDN, TE, CD);
    and (LD_CD, LD, CD);
    and (DXTI_LD_CD, DXTI, LD, CD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2SL2QC.v,v 1.3 1996/04/11 16:27:33 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2SL2QC (Q,D,CP,CD,TI,TE,LD);
output Q ;
input D,CP,LD,TI,TE,CD ;
    parameter
        CMOS_TO_TTL = 0;
    parameter
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    not
        (DN, D);
    CSL_FD2SL
        M1 (QT, TI, TE, DN, LD, CP, CD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not (LDN, LD);

    xor (DXTI, D, TI);
    and (LDN_TE_CD, LDN, TE, CD);
    and (LD_CD, LD, CD);
    and (DXTI_LD_CD, DXTI, LD, CD);

endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2SQA.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2SQA (Q,D,CP,CD,TI,TE);
output Q ; 
input D,CP,CD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, CD, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not
        (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (DXTI_CD, DXTI, CD);
    and
        (TEN_CD, TEN, CD);
    and
        (TE_CD, TE, CD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD2SQC.v,v 1.4 Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD2SQC (Q,D,CP,CD,TI,TE);
output Q ; 
input D,CP,CD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, Y, CP, CD, 1, notifier);
           
    CSL_MUX21 
	M2 (Y, D, TI, TE);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    not
        (TEN, TE);
    xor
    (DXTI, D, TI);
    and
        (DXTI_CD, DXTI, CD);
    and
        (TEN_CD, TEN, CD);
    and
        (TE_CD, TE, CD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD3QA.v,v 1.4 1995/07/10 21:19:08 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD3QA (Q,D,CP,CD,SD);
output Q ; 
input D,CP,CD,SD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, CD, SD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    and
        (CD_SD, CD, SD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD3QC.v,v 1.4 1995/07/10 21:19:27 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD3QC (Q,D,CP,CD,SD);
output Q ; 
input D,CP,CD,SD ; 
    parameter 
        CMOS_TO_TTL = 0;
    parameter 
        CLOAD$Q = 0;
    reg
        notifier;
    buf #(0.0, 0.0)
        (Q, QT);
    CSL_FD3_Q
        M1 (QT, D, CP, CD, SD, notifier);

// <<<<<<<<<<<<<<<<<<<< Additional Logic Provided for Timing Checks >>>>>>>>>>>>>>>>>>

    and
        (CD_SD, CD, SD);


endmodule

`endcelldefine
`nosuppress_faults
`disable_portfaults 
// $Header: FD3SQA.v,v 1.6 1995/07/10 21:19:32 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine

module FD3SQA (Q,D,CP,CD,SD,TI,TE);
output Q ; 
input D,CP,CD,SD,TI,TE ; 
    parameter 
        CMOS_TO_TTL = 0;