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Xilinx Answer #8561 : WebPACK: What is WebPACK?
Xilinx Answer #8380 : WEBFITTER, LOGIBLOX: WebFitter error about "invalid filename extensions" on .NGC files produced by LogiBLOX
Xilinx Answer #8375 : ABEL: Signal properties ignored: Warning 18818:Could not find signal or instance <signal_name> associated with property <property_name>.
Xilinx Answer #8140 : XPLA Pro: Error: "No output bin/isp file generated, download aborted"
Xilinx Answer #8095 : 2.1i 9500/XL Hitop: Designs that fit in 1.5x do not fit in 2.1i
Xilinx Answer #8018 : WebPACK: Window95/98 environment variables incorrectly overwritten on installation
Xilinx Answer #7017 : WEBPACK: Can I use a VHDL or Verilog source file, or is the tool ABEL based?
Xilinx Answer #6090 : Hitop: Impelemented Equations within the Fitter Report don't have the .pin or .fb extensions when using ABEL.
Xilinx Answer #6054 : A1.5s2/F1.5is2: 95288XL Programming support and jedec file creation support
Xilinx Answer #6040 : A1.5isp2/F1.5isp2: 9500XL Designs with FDCE, FDPE, or other CE elements require this new jedec file creation update.
Xilinx Answer #5856 : 1.5i SP2 Hitop - Hitop fails with an application fault when used w. newer vers. of MSVCRT.DLL
Xilinx Answer #5847 : 1.5i SP2 9500XL Hprep6 - Incorrect implementation of XOR3 and greater in hprep6
Xilinx Answer #5834 : 1.5i SP2 Hitop - Hitop fails to select 9536XL and 9572XL devices in autoselect mode.
Xilinx Answer #5829 : 1.5i SP2 Hitop - ERROR:cl244 - [Internal Error] Corrupt partition product term.
Xilinx Answer #5479 : Webfitter: JavaScript Error: https://xapps1.xilinx.com/webfitter/cgi-bin/buttons.cgi, line 35:
Xilinx Answer #5478 : Webfitter: Left Hand Side (contents) of Help window is inactive (Java not enabled)
Xilinx Answer #5111 : F1.5i/2.1i: Taengine produces Timing report with no data - too many paths to trace
Xilinx Answer #4943 : Abel macro feedthroughs are being ignored in F1.5
Xilinx Answer #4770 : A1.5/F1.5 CPLD - Signature/User Code always generates "sign" when not using default option.
Xilinx Answer #4544 : A1.5 CPLD - CPLD update is available with faster speed grades and other changes.
Xilinx Answer #4469 : A1.4/F1.4 CPLD - The XC9500 timing table has been updated due to improved speed of the XC9500
Xilinx Answer #4174 : 1.5i 9500/XL Fitter - Uses 2 macrocells instead of 1 for combinatorial latch
Xilinx Answer #4067 : M1.4 EPLD-FIT (1.4): Dr. Watson for Windows NT: hitop.exe
Xilinx Answer #4051 : M1.4 CPLD(9500): FPGA-EXPRESS - VHDL, Input to toggle control of FF inverted instead of the output.
Xilinx Answer #4048 : M1.4 Fitter/Hitop - Incorrect logic generated.
Xilinx Answer #3937 : M1.4 TSIM - ERROR:basnu:115 - logical net "b_reset" has both active and tristate drivers.
Xilinx Answer #3803 : M1.4 CPLD - Fitter report & timing simulation (F1.4) gives incorrect equations.
Xilinx Answer #3802 : M1.4 CPLD - Timing violation: Slow simulation model produced with the "Use Local Macrocell Feedback" switch
Xilinx Answer #3801 : M1.4 CPLD - A software update is available to support the new CSP48 package in the XC9000 family.
Xilinx Answer #3733 : M1.4 Hitop - Optimization disregards that control signals can have only 1 pterm.
Xilinx Answer #3732 : M1.4 Hitop - hitop error: Error:rg119
Xilinx Answer #3730 : M1.4 CPLD Fitter: Combinatorial logic duplicated with multilevel logic optimization
Xilinx Answer #3720 : M1.3/M1.4: Hitop hangs for 9500 design
Xilinx Answer #3686 : M1.4: FATAL_ERROR:baslo:basloglobal.c:35:1.9 - on line 972 of file "baslodriver.c"
Xilinx Answer #3533 : A1.4/F1.4 CPLD - List of all CPLD patches available in A1.4/F1.4.
Xilinx Answer #3442 : M1.4 CPLD - A patch is available for several issues.
Xilinx Answer #3387 : M1.3/M1.4: Hitop, Done: Failed with exit code: 002
Xilinx Answer #3384 : XABEL M1.3 - Slew rate property does not work with EPLD patches
Xilinx Answer #3307 : M1.3/M1.4 hplusas6: JEDEC File generator not writing ABEL test vectors in the JED file
Xilinx Answer #3275 : CPLD M1.3(patch),M1.4: Pin location assignments for 9500 designs are not seen
Xilinx Answer #3242 : M1.3 Hitop - Fitter fails to meet Period timespec for easy design.
Xilinx Answer #3241 : M1.3 CPLD - Bitmap is incorrect for XC95288.
Xilinx Answer #3240 : M1.3 CPLD - There have been pinout changes for the XC95144 device.
Xilinx Answer #3239 : M1.3 CPLD - A -6 speed grade has been added for XC9536.
Xilinx Answer #3238 : M1.3 CPLD - CPLD Patch available for several issues
Xilinx Answer #3237 : M1.3 CPLD - Fitter drops inverter from Express XNF when IBUF drives OBUFT.
Xilinx Answer #3213 : M1.3 Hitop - Hitop core dumps on a specific case.
Xilinx Answer #3210 : M1.3 CPLD - The XC95144 pinout has changed
Xilinx Answer #3208 : M1.3.7 Hitop - Hitop crashes if there are more than 20 timespecs in the .ncf file.
Xilinx Answer #3207 : M1.3 Hitop - Unnecessary warning about 95108 UPGs not supported
Xilinx Answer #3142 : TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock pin *.CLKF
Xilinx Answer #3127 : M1.4 CPLD: Possible solution for excessive run time of Bus Error problems with the fitter
Xilinx Answer #3121 : HITOP: xr52:[Warning]NET 'xxxx' is driven by 'yyy' and 'zzz'.
Xilinx Answer #3008 : CPLD: CPLD command-line does not support reading PART attribute from netlist.
Xilinx Answer #2956 : M1.4 CPLD: Interactive Timing Analyzer gives unhelpful messages when invoked on a 7K design
Xilinx Answer #2913 : M1.4 CPLD: The OFFSET timing constraint does not force the fitter to use global clocks
Xilinx Answer #2910 : M1.4 CPLD: Some designs which used to fit in M1.3 failed with M1.4.
Xilinx Answer #2906 : M1.4 CPLD: How to reserve a pin or a macrocell for future use?
Xilinx Answer #2897 : The detail timing report contains some signals with a .Q extension.
Xilinx Answer #2866 : GSR and GTS pads don't work in SXNF netlists from Synopsys for CPLDs.
Xilinx Answer #2794 : M1: Taengine -> abnormal program termination
Xilinx Answer #2752 : M1.3.7 - CPLD patch available for several issues
Xilinx Answer #2732 : CPLD: XC9500/XL: How to control Timing in a CPLD
Xilinx Answer #2731 : M1.3 CPLD: taengine - Assertion failed: !i->RetOutput(iot,ZeroIfNew)
Xilinx Answer #2729 : CPLD: 9500/XL : How to control Logic Optimization in a CPLD
Xilinx Answer #2727 : M1.3.7 Hitop error: Hitop caused an invalid page fault in module HITOP.EXE at 0137-00436952
Xilinx Answer #2724 : M1.3: FATAL_ERROR:baspm.baspmdlm.c:99:1.17 - dll library <mtrne> does not exist.
Xilinx Answer #2719 : CPLD: 9500/XL: How to lock the pins on a CPLD
Xilinx Answer #2717 : CPLD: XC9500/XL : How to control Power Consumption in a CPLD
Xilinx Answer #2704 : M1 CPLD: How does the CPLD Auto Device Selection Work
Xilinx Answer #2661 : M1.3 CPLD: Synopsys I/O ports cause xr5100 and nd201 warnings and pin name changes.
Xilinx Answer #2660 : **M1.3/M1.4 CPLD: Exemplar netlists use IOBUFE which is not expanded by 9k library.
Xilinx Answer #2654 : M1.3 CPLD: Synopsys set_pad_type -slewrate command causes disconnected OBUF in CPLD.
Xilinx Answer #2584 : Hitop: hi12:[Error]Keyword PIN_FREEZE:servo_cpu_decoder.gyd in the CTL file is invalid.
Xilinx Answer #2579 : CPLD : 9500: How to utilize the Wired-AND (WAND) in the UIM
Xilinx Answer #2336 : M1.3/M1.4 : 9500 : Hitop: Fitter warning xr5049 - invalid 'BUFG' parameter
Xilinx Answer #2334 : M1.3/M1.4 CPLD: Fitter warning xr5100 - Inserting an output buffer
Xilinx Answer #2327 : M1 CPL: PWR_MODE attribute cannot be placed on non-logic symbols
Xilinx Answer #2307 : M1.3/M1.4 CPLD: Fitter issues spurious nd14 warnings
Xilinx Answer #2243 : M1.3/M1.4/M1.5 CPLD: Fitter takes more than 200 Megs of RAM while fitting a design
Xilinx Answer #2217 : What do the Xs and @s mean in the Fitter report?
Xilinx Answer #2215 : CPLD: OPT=MERGE
Xilinx Answer #2146 : CPLD: XC9500: How to place a macrocell/signal in low power mode (LOWPWR or PWR_MODE)