What's a Module? 

Modules are one-hour sessions which consist of topics that focus specifically on product solutions and audience types. Instead of taking an entire course that may cover material you are already familiar with, take a module and focus only on what you do not know.

Training for modules is conducted electronically via the web. This brings training right to your desktop, thus offering students both flexibility and convenience. We call this desktop service "E-Learning". We are always in the process of creating new modules so watch this site for frequent updates. Once you find a module that fits your training needs, look at our E-Learning delivery schedule to find a time that is convenient for you. To register for an E-Learning session, contact the registrar at 877-XLX-CLASS. For more information about enrollment, visit our registration page.

Modules that are Available

Version 2.1i

Version 1.5i

Advanced Simulator Usage (2.1i)
Basic Virtex Architecture (2.1i)
Board Layout I (2.1i)
Coding Tips for Spartan Devices I (2.1i)
Coding Tips for Spartan Devices II (2.1i)
Coding Tips for Virtex Devices I (2.1i)
Coding Tips for Virtex Devices II (2.1i)
Command Line Implementation (2.1i)
Configuration for Spartan/XC4000) (2.1i)
Configuration for Virtex (2.1i)
CORE Generator System (2.1i)
Creating your own RPM (2.1i)
Floorplanner I: Viewing Your Design (2.1i)
Floorplanner II: Effective Layout (2.1i)
Floorplanner III: Editing Placement (2.1i)
Flow Engine I: GUI Implementation Options (2.1i)
Foundation Tools Update - (2.1i)
FPGA Design II (2.1i)
FPGA Editor I (2.1i)
FPGA Editor II (2.1i)
HDL Editor & State Editor (2.1i)
Help Resources - Getting Answers Fast! (2.1i)
Implementation Tools Update - (2.1i)
Introduction to Efficient Synthesis & Simulation (2.1i)
Introduction to FPGA Design (2.1i)
Introduction to Xilinx Products (2.1i)
LogiBLOX and the CORE Generator (2.1i)
ModelSim XE - I Projects
ModelSim XE 5.3 - II Simulation
ModelSim XE 5.3 - III Scripting
Project Manager (2.1i)
Reading Reports (2.1i)
Schematic Design Entry (2.1i)
Schematic Editor (2.1i)
Simulator (2.1i)
Spartan Architecture (2.1i)
Timing Analyzer I (2.1i)
Timing Constraints in the UCF (2.1i)
Timing Constraints in the UCF II (2.1i)
Timing Constraints I (2.1i)
Timing Constraints II (2.1i)
Timing Constraints III (2.1i)
Verilog: Advanced Process Statements (2.1i)
Verilog: Behavioral Modeling (2.1i)
Verilog: Data Flow Modeling (2.1i)
Verilog: Gate Level Modeling (2.1i)
Verilog: Hardware Modeling (2.1i)
Verilog: Language Concepts (2.1i)
Verilog: Modules & Ports (2.1i)
Verilog: Operators & Expressions (2.1i)
Verilog: Project Management with Verilog HDL (2.1i)
Verilog: Targeting Xilinx with Verilog (2.1i)
Verilog: Tasks & Functions (2.1i)
Verilog: Testbenches (2.1i)
VHDL: Advanced Coding Issues (2.1i)
VHDL: Advanced Process Statements (2.1i)
VHDL: Behavioral 2 RTL Coding (2.1i)
VHDL: Concurrent & Sequential Statements (2.1i)
VHDL: Controlled Operation Statements (2.1i)
VHDL: Design Management (2.1i)
VHDL: Functions & Procedures (2.1i)
VHDL: Hardware Modeling Overview (2.1i)
VHDL: Language Concepts (2.1i)
VHDL: Operators & Expressions (2.1i)
VHDL: Signals & Datatypes (2.1i)
VHDL: Targeting (2.1i)
VHDL: Testbenches (2.1i)
VHDL: Vital (2.1i)
Virtex Architecture I
Virtex Architecture II
Virtex E Architecture
Xilinx Tool Flow (2.1i)

Coding Tips for Spartan Devices I (1.5)
Coding Tips for Spartan Devices II (1.5)
Floorplanner I:  Viewing Your Design (1.5)
Floorplanner II:  Effective Layout (1.5)
Floorplanner III:  How to Edit the Placement (1.5)
FPGA Configuration I (1.5)
FPGA Design II:  Performance by Design (1.5)
Help Resources - Getting Answers Fast! (1.5)
Introduction to Efficient Synthesis and Simulation (1.5)
Introduction to FPGA Design (1.5)
Reading Reports (1.5)
Timing Analyzer I (1.5)
Timing Constraints I (1.5)
Timing Constraints II (1.5)
Xilinx Tool Flow (1.5)